DETAILED ACTION
This Office action is in response to the application filed on 22 January 2024.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lyn et al. US 2021/0258023 A1.
As to claim 1, Lyn discloses substantially the invention as claimed, including a transmitter (Figures 1, 2, the transmit chain 252 in the transceiver 126 in the mobile device 102), comprising:
an upconverter circuit (Figure 2, the UP-Converters (UPC) 136) including one or more inputs (including I, Q baseband signals as inputs to the transmitter 252, [55]) coupled to one or more transmit chains of the transmitter (Figures 2-5 and associated paragraphs);
an inverter buffer (Figures 2-5, the tunable filter 138 may be implemented with the driver amplifier 134 included in the Mixer load 132, [60]-[64]) including an input coupled to a first output of the upconverter circuit (Figures 2-5, and associated paragraphs) (it is obvious that Lyn’s tunable filter 138 provides an input to the driver amplifier 134 as a design option instead of being as the instant inverter buffer 434 provides an input to the driver amplifier 422 for the purpose of supporting a wide range operation of a transmission chain frequency and sharing at RF across multiple radio frequency ranges, [30], [31] as in instant application in instant paragraph [17]); and
at least one amplifier (Figures 2-5, the driver amplifier 134) coupled to a first output of the inverter buffer (Figures 2-5 and associated paragraphs).
As to claim 2, Lyn discloses, wherein a maximum output power capability of the upconverter circuit is less than a power consumption of the at least one amplifier for transmission using a first frequency band (a band for 5G communication, [30], [31]) (Figures 2-5 and associated paragraphs).
As to claim 3, Lyn discloses, wherein the transmitter is configured to support the first frequency band and a second frequency band (a band for 2G communications, [30], [31]) having a lower center frequency than the first frequency band (Figures 2-5 and associated paragraphs).
As to claim 4, Lyn discloses, wherein the inverter buffer comprises a resistive element coupled between the input of the inverter buffer and the first output of the inverter buffer (It is well known in the design of the inverter buffer including a resister element as in Figures 2, 3, 6 and [51] in Chen US 2010/0141337 A1).
As to claim 5, Lyn discloses, an inductive element with a first terminal (Figure 7, the L1) coupled to the first output of the inverter buffer (Figure 7, the output node 702-2) and a tap (Figures 4, 7, the Vin {To: Main Amplifier 402}) coupled to an input of the at least one amplifier (the DA 134).
As to claim 6, Lyn discloses, wherein: the inductive element includes a second terminal (Figure 7, the L2) coupled to a second output of the inverter buffer; and the transmitter further comprises a capacitive element (Figure 7, the C_low 710) coupled between the first terminal and the second terminal of the inductive element (Figures 4, 7 and associated paragraphs).
As to claim 7, Lyn discloses, wherein the capacitive element comprises a variable capacitive element (Figures 4, 7 and associated paragraphs).
As to claim 8, Lyn discloses, an alternating-current (AC)-coupling capacitive element (the C_adj element 506) coupled between the first output of the inverter buffer and the first terminal of the inductive element (Figures 4, 7 and associated paragraphs).
As to claim 9, Lyn discloses, wherein the inverter buffer comprises: a first transistor with a source coupled to a voltage rail and a drain coupled to the first output of the inverter buffer; a second transistor with a source coupled to a reference potential node and a drain coupled to the first output of the inverter buffer; and a resistive element coupled between the first output of the inverter buffer and gates of the first transistor and the second transistor (It is well known in the design of the inverter buffer including a first transistor 314, a second transistor 312, a resistive element 322 as in Figures 2, 3, 6 and associated paragraphs in Chen US 2010/0141337 A1).
As to claim 10, Lyn discloses, wherein the inverter buffer further comprises an AC-coupling capacitive element (the Cac+ element in Figure 5) coupled between the first output of the upconverter circuit and the gates of the first transistor (the gate 602 +, in Figure 6) and the second transistor (the gate 602 -, in Figure 6) (It is well known in the design of the inverter buffer including a first transistor 314, a second transistor 312 as in Figures 2, 3, 6 and associated paragraphs in Chen US 2010/0141337 A1).
As to claim 11, Lyn discloses, wherein the upconverter circuit comprises a passive mixer (Figures 2-5 and associated paragraphs, the mixer load 132).
As to claim 12, Lyn discloses, wherein the at least one amplifier comprises: a first amplifier (Figures 2-6, the DA 134) including an input coupled to a first output of the inverter buffer (the tunable filter 138); a transformer (Figure 6, a transformer of the a balun 306) including a primary winding coupled to an output of the first amplifier; a second amplifier (the main Amplifier 402) including an input coupled to a secondary winding of the transformer; and another transformer (Figure 6, a transformer of the a balun 306) including a primary winding coupled to an output of the second amplifier (Figures 2-7 and associated paragraphs).
As to claim 13, Lyn discloses, wherein the one or more transmit chains comprise a first transmit chain for an in-phase (I) signal and a second transmit chain for a quadrature (Q) signal (Figures 2-5 and associated paragraphs).
As to claim 14, Lyn discloses, wherein each of the one or more transmit chains comprises a digital-to-analog converter (DAC) and a baseband filter (Figures 2-5 and associated paragraphs).
Claims 15-19 correspond to the method claims of the transmitter claims 1-3, 5-6; therefore, they are rejected under the same rationale as in the transmitter claims 1-3, 5-6 as shown above.
Claim 20 corresponds to the wireless device having the transmission chain claim of the transmitter claim 1; therefore, they are rejected under the same rationale as in the transmitter claim 1 as shown above.
The prior art cited in this Office action are: Lyn et al. US 2021/0258023 A1; Chen US 2010/0141337 A1.
Conclusion
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/HAI V NGUYEN/Primary Examiner, Art Unit 2649