DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Hung et al. (US 10,164,766).
Referring to Claim 1, Hung teaches a near-field communication (NFC) apparatus (see col. 4, lines 7-14 which shows NFC communication), comprising:
a clock extractor configured to perform clock recovery based on a first carrier signal from an NFC card reader to obtain a field clock signal (see col. 4, lines 39-53 which shows a carrier sent from a card reader and the TX extracting a recovery clock signal from the carrier);
a digital phase-locked loop configured to perform frequency tracking on the field clock signal to output a first clock signal (see fig. 3 which shows recovery clock signal entered into a PLL described as Lock Loop in fig. 3 where the output of Pre 328 is the first clock signal input to PFD 322);
a digital baseband chip configured to perform load modulation based on the first clock signal to generate a second carrier signal (see see col. 2, lines 13-29 which shows the DBB process on the clock signal which leads to the output of the PA as the output signal 510 as the second carrier signal); and a controller, configured to:
detect a frequency of the field clock signal or a phase of the field clock signal to obtain a frequency detection result or a phase detection result (see recovery clock signal input to phase and frequency detector 322 in fig. 3); and
selectively perform open-loop control on the digital phase-locked loop based on the frequency detection result or the phase detection result (see col. 2, lines 55-62 which shows the selective disabling of the PFD in order to open a loop).
Claim 11 has similar limitations as claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 7, 12, 17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Kundu et al. (US 2022/0393688).
Referring to Claims 2 and 12, Hung does not teach performing closed-loop control on the digital phase-locked loop when the frequency detection result or the phase detection result has no deviation; or generating a first open-loop control signal when the frequency detection result or the phase detection result has the deviation and performing the open-loop control on the digital phase-locked loop using the first open-loop control signal. Kundu teaches performing closed-loop control on the digital phase-locked loop when the frequency detection result or the phase detection result has no deviation; or generating a first open-loop control signal when the frequency detection result or the phase detection result has the deviation and performing the open-loop control on the digital phase-locked loop using the first open-loop control signal (see paragraph 120 which shows operating in an open or closed loop based on impedance and paragraph 17 which shows phase difference affecting change in impedance further noting that the claim does not specifically state which loop state the device operates in as it only states closed and open loop control). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Kundu to the device of Hung in order to more effectively output a more ideal signal to the other NFC device.
Referring to Claims 7 and 17, Kundu also teaches receiving the first carrier signal; detecting an amplitude of the first carrier signal; and further perform the closed-loop control on the digital phase-locked loop when the amplitude of the first carrier signal is greater than a preset value (see paragraph 68 which shows power consumption compared to a max power consumption limit where the power is the amplitude and the power consumption determines the frequency which determines open or closed loop operation in paragraph 120).
Referring to Claim 20, Kundu also teaches receiving, by a frequency divider of the digital phase-locked loop, the first clock signal; and performing, by the frequency divider, frequency division on the first clock signal to reduce a frequency of the first clock signal to be equal to or close to the frequency that is recovered by the clock extractor (see paragraph 16 which shows divider 102e which divides frequency of VCOOut of PLL 102).
Claim(s) 10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung and Kundu and further in view of Desai et al. (US 2022/0069810).
Referring to Claims 10 and 19, the combination of Hung and Kundu does not teach the load modulation is an active load modulation, wherein the digital baseband chip is further configured to generate a second open-loop control signal to output the second carrier signal, and wherein the controller further comprises a multiplexer (MUX) configured to selectively perform the open-loop control on the digital phase- locked loop based on at least one of the first open-loop control signal or the second open-loop control signal. Desai teaches the load modulation is an active load modulation, wherein the digital baseband chip is further configured to generate a second open-loop control signal to output the second carrier signal, and wherein the controller further comprises a multiplexer (MUX) configured to selectively perform the open-loop control on the digital phase- locked loop based on at least one of the first open-loop control signal or the second open-loop control signal (see paragraph 15 which shows the active load modulation and paragraph 52 which shows two control signals for a multiplexer, one to operate in open loop and the other to operate in closed loop further noting that a second open loop control signal includes a signal to discontinue open loop operations since there are no specifics to state otherwise). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Desai to the modified device of Hung and Kundu in order to more effectively reduce unwanted noise.
Allowable Subject Matter
Claims 3-6, 8-9, 13-16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claims 3 and 13, Hung, Kundu, and Desai do not teach receiving the first clock signal from the digital phase-locked loop; performing frequency multiplication on the first clock signal to obtain a second clock signal; sampling the field clock signal using the second clock signal to obtain a sampling result; and detecting the frequency of the field clock signal or the phase of the field clock signal based on the sampling result.
Regarding Claims 8 and 18, Hung, Kundu, and Desai do not teach an amplitude detection circuit configured to:
receive the first carrier signal; detect the amplitude; and generate an amplitude detection result based on the amplitude, wherein the amplitude detection result is a second voltage level when the amplitude is greater than the preset value;
a delay circuit configured to:
delay outputting the amplitude detection result for a preset time; and output the amplitude detection result after the delay; and
a digital circuit configured to:
receive the amplitude detection result; and further perform the closed-loop control on the digital phase-locked loop based on the amplitude detection result.
Regarding Claim 9, Hung, Kundu, and Desai do not teach the digital phase-locked loop comprising:
a time-to-digital converter configured to:
receive the first open-loop control signal; stop obtaining a first value based on the first open-loop control signal; and keep a second value that is obtained before receiving the first open-loop control signal;
a digital filter configured to:
receive the first open-loop control signal; stop obtaining the first value based on the first open-loop control signal; and keep the second value before receiving the first open-loop control signal;
a digitally controlled oscillator configured to:
maintain an oscillation signal that is received before an open-loop state to be oscillating; and output the first clock signal; and
a frequency divider configured to:
receive the first clock signal; and perform frequency division on the first clock signal to reduce a frequency of the first clock signal to be equal to or close to the frequency that is recovered by the clock extractor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE YUN whose telephone number is (571)272-7860. The examiner can normally be reached 9am-5pm.
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/EUGENE YUN/ Primary Examiner, Art Unit 2648