Office Action Predictor
Last updated: April 16, 2026
Application No. 18/418,700

CALIBRATED DELAY LINES FOR GENERATION OF ACCURATE AND PROGRAMMABLE PHASE DELAYS BETWEEN OUTPUTS OF FREQUENCY DIVIDERS

Final Rejection §103
Filed
Jan 22, 2024
Examiner
POOS, JOHN W
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., LTD.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
2y 0m
To Grant
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
1277 granted / 1365 resolved
+25.6% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
36 currently pending
Career history
1401
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
29.4%
-10.6% vs TC avg
§102
58.1%
+18.1% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1365 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-2, 4, 11-12, and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-2 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bell (US 2003/0011414), in view of Pandita et al. (US 2019/0052278). In regard to Claim 1: Bell discloses, in Figure 1, a method for generating accurate and programmable phase delay output signals, the method comprising: determining, via a phase detector unit (150), a phase disparity signal (142, 143); generating, via a digital calibration logic unit (124), a control signal (119-0, 119-N) based on the phase disparity signal (142, 143); and generating, via a tunable delay lines unit (112), the phase delay output signals (114, 116) based on the control signal (119-0, 119-N), but does not disclose a phase disparity signal based on a phase error between two or more consecutive outputs of a frequency divider unit cell. Pandita discloses, in Figure 1, a phase disparity signal (102 output) based on a phase error (Paragraph 0021) between two or more consecutive outputs (FB, Claim 10) of a frequency divider unit cell (170). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the phase detector output taught by Pandita with the phase detector taught by Bell, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385). In regard to Claim 2: Pandita further discloses, in Figure 1, the method of Claim 1, further comprising: partitioning, via the frequency divider unit (170), a frequency of a signal (VCO) received from a voltage-controlled oscillator (VCO) (155, 160; Paragraph 0034) or a digitally-controlled oscillator (DCO) to obtain the frequency-divided signal. In regard to Claim 11: Bell discloses, in Figure 1, an electronic device for generating accurate and programmable output signals, the electronic device comprising: a phase detector unit (150) configured to determine a phase disparity signal (142, 143); a digital calibration logic unit (124) configured to generate a control signal (119-0, 119-N) based on the phase disparity signal (142, 143); and a tunable delay lines unit (112) configured to generate the phase delay output signals (114, 116) based on the control signal (119-0, 119-N), but does not disclose a phase disparity signal based on a phase error between two or more consecutive outputs of a frequency divider unit cell. Pandita discloses, in Figure 1, a phase disparity signal (102 output) based on a phase error (Paragraph 0021) between two or more consecutive outputs (FB, Claim 10) of a frequency divider unit cell (170). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the phase detector output taught by Pandita with the phase detector taught by Bell, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385). In regard to Claim 12: Pandita further discloses, in Figure 1, the electronic device of Claim 11, wherein the frequency divider unit (170) is configured to partition a frequency of a signal (VCO) received from a voltage-controlled oscillator (VCO) (155, 160; Paragraph 0034) or a digitally-controlled oscillator (DCO) to obtain the frequency-divided signal. Allowable Subject Matter Claims 3-10 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN W POOS/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Jan 22, 2024
Application Filed
Aug 27, 2025
Non-Final Rejection — §103
Nov 28, 2025
Applicant Interview (Telephonic)
Nov 28, 2025
Examiner Interview Summary
Dec 01, 2025
Response Filed
Feb 09, 2026
Final Rejection — §103
Apr 13, 2026
Response after Non-Final Action

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.3%)
2y 0m
Median Time to Grant
Moderate
PTA Risk
Based on 1365 resolved cases by this examiner. Grant probability derived from career allow rate.

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