Prosecution Insights
Last updated: April 19, 2026
Application No. 18/418,939

DISPLAY APPARATUS

Final Rejection §103
Filed
Jan 22, 2024
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seoul Semiconductor Co. Ltd.
OA Round
4 (Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
2y 6m
To Grant
78%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
858 granted / 1060 resolved
+12.9% vs TC avg
Minimal -3% lift
Without
With
+-3.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
47 currently pending
Career history
1107
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
52.0%
+12.0% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1060 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-6,9-13,16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomoda et al (PG Pub 2017/0140679 A1) and Okada et al (PG Pub 2010/0277919 A1). Regarding claim 1, Tomoda teaches a display device comprising: a support (240, figs. 3, 4, 10) including conductors (118, which is connected to drive circuit 111, figs. 10 and 11, paragraph [0073]); a substrate (212/223) disposed on the support and electrically connected to the support (wire 219 connects to 118 to transmits image signals, paragraphs [0073][0076]); and a light emitter (LEDs in pixels 211, fig. 3, paragraph [0060]) disposed on the substrate and configured to emit light, wherein the substrate includes a recess (224, fig. 8) depressed from a side surface of the substrate, wherein a connection electrode (225 to 227, fig. 8) is formed in the recess, wherein an upper pad (219, fig. 11) is formed on an upper region of the substrate adjacent to the recess (219 near the recess where connection electrode 225 is formed, fig. 11; connection electrode 225 is formed in recess 224, fig. 8) and electrically connects the connection electrode to the light emitter (drive circuit 111 transmit image signals from 118 and 216 through 219 and 225 from one panel to the next, paragraphs [0076][0077]); the connection electrode is disposed on the substrate (fig. 11), wherein a region of the protection insulative material is exposed to the outside (exposed to the viewer, fig. 11); and wherein the light emitter is electrically connected to the conductors through the connection electrode (to receive image signals, paragraphs [0073][0076][0077]). Tomoda does not teach explicitly use the terms “an upper pad”. Comparing “upper pad” 123a in fig. 3 of Applicant’s drawing and element 219 in fig. 11 of Tomoda, they appear analogous. Thus, 219 in Tomoda reads on the claimed “an upper pad.” “The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required.” In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). Tomoda does not teach the upper pad intersecting a same location on the upper region of the substrate that supports the light emitter. Tomoda teaches image signals are transmitted through side electrodes (in recessed region 224, paragraph [0078]), implying that electrodes 225-227 in recessed region 224 are electrically connected to LEDs/pixels 210 (fig. 3) through wiring 219 (fig. 11). In the same field of endeavor, Okada teaches an upper pad (21Rc and 21Rb, fig. 7) intersecting a same location on the upper region of the substrate that supports a light emitter (3R, paragraph [0045]), for the benefit of electrically connecting the pad to the light emitter (fig. 7). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the upper pad intersect a same location on the upper region of the substrate that supports the light emitter for the benefit of electrically connecting the pad to the light emitter for the light emitter to receive the image signal to display image. Tomoda does not teach that the substrate includes a protection insulative material. It would have been obvious to the skilled in the art before the effective filing date of the invention to make the wherein the substrate to include a protection insulative material (by making the glass insulative, paragraph [0061] of Tomoda), such as on the upper surface where wires 219 are disposed (fig. 11a) and on the side surfaces of the display panels where connectors 225 are disposed, for the known benefit of preventing (or protecting against) shorting wires 219 and connectors 225. As a result, the at least one of the connection electrodes is disposed on the protection insulative material, wherein a region of the protection insulative material (top surface) is exposed to the outside. Regarding claim 2, Tomoda teaches the display device of claim 1, wherein the connection electrode includes a side electrode (227 of 225 in recess 224, figs. 8 and 11). Regarding claim 3, Tomoda teaches the display device of claim 2, wherein the side electrode is disposed on the side surface of the substrate (figs. 8 and 11). Regarding claim 4, Tomoda teaches the display device of claim 2, wherein the side electrode is connected to the upper pad (drive circuit 111 transmit image signals from 118 and 216 through 219 and 225 from one panel to the next, paragraphs [0076][0077]). Regarding claim 5, Tomoda teaches the display device of claim 1, wherein the substrate includes a protrusion on an end surface thereof (fig. 8). Regarding claim 6, Tomoda teaches the display device of claim 1, wherein the recess is filled with the connection electrode (figs. 7 and 11). Regarding claim 9, Tomoda (see claims 1-3) teaches a display device comprising: a support including conductors; a substrate electrically connected to the support; and a light emitter disposed on the substrate, wherein the substrate includes a recess depressed from at least one side surface of the substrate, wherein a connection electrode is formed in the recess, wherein the connection electrode includes a side electrode (conductive coating 227 of 225 formed in recess 224, fig. 8) disposed on a side surface of the substrate and that includes a region (227) that is disposed in the recess, is wherein the substrate includes a protection insulative material, wherein the connection electrode is disposed on the protection insulative material, wherein a region of the protection insulative material is exposed to the outside, and wherein the light emitter is electrically connected to one of the conductors through the connection electrode. Regarding claim 10, Tomoda teaches (see claim 1) the display device of claim 9, wherein the substrate includes an upper pad electrically connected to the connection electrode. Regarding claim 11, Tomoda teaches (see claim 4) the display device of claim 10, wherein the side electrode is connected to the upper pad. Regarding claim 12, Tomoda teaches (see claim 5) the display device of claim 9, wherein the substrate includes a protrusion on an end surface. Regarding claim 13, Tomoda teaches the display device of claim 9, wherein the recess is filled with the connection electrode (see claim 6). Regarding claim 16, Tomoda (see claims 1-3) teaches a display module comprising: a substrate including a recess depressed from at least one side surface of the substrate; a connection electrode formed in the recess; a light emitter disposed on the substrate and including a plurality of semiconductor io layers, wherein the substrate comprises a conductive region and a non-conductive region including a protection insulative material, wherein an upper pad is formed on an upper region of the substrate adjacent to the recess and electrically connects the connection electrode to the light emitter, wherein the connection electrode includes a side electrode disposed on a surface of the substrate and that includes a region that is disposed in the recess, and wherein the connection electrode is disposed on the non-conductive region. Tomoda does not teach the upper pad intersecting a same location on the upper region of the substrate that supports the light emitter. Tomoda teaches image signals are transmitted through side electrodes (in recessed region 224, paragraph [0078]), implying that electrodes 225-227 in recessed region 224 are electrically connected to LEDs/pixels 210 (fig. 3) through wiring 219 (fig. 11). In the same field of endeavor, Okada teaches an upper pad (21Rc and 21Rb, fig. 7) intersecting a same location on the upper region of the substrate that supports a light emitter (3R, paragraph [0045]), for the benefit of electrically connecting the pad to the light emitter (fig. 7). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the upper pad intersect a same location on the upper region of the substrate that supports the light emitter for the benefit of electrically connecting the pad to the light emitter for the light emitter to receive the image signal to display image. Regarding claim 17, Tomoda (see claim 1) teaches the display module of claim 16, wherein the side electrode is connected to the upper pad. Regarding claim 18, Tomoda teaches (See claim 5) the display module of claim 16, wherein the substrate includes a protrusion on an end surface. Regarding claim 19, Tomoda teaches (see claim 6) the display module of claim 16, wherein the recess is filled with the connection electrode. Regarding claim 20, Tomoda teaches (see claim 8) the display module of claim 16, further comprising: a connection wire (219, fig. 11) disposed on an upper surface of the substrate and connected to the connection electrode. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomoda et al (PG Pub 2017/0140679 A1) and Okada et al (PG Pub 2010/0277919 A1) as applied to claim 1 above, and further in view of Su et al (PG Pub 2020/0111771 A1). Regarding claim 7, Tomoda remains as applied in claim 1. Tomoda further teaches the connection electrode electrically contacts the conductor (drive circuit 111 transmit image signals from 118 and 216 through 219 and 225 from one panel to the next, paragraphs [0076][0077]). Tomoda does not teach the conductors of the support are disposed on a surface of the support facing the substrate. In the same field of endeavor, Su teaches the conductors (246a, 242, fig. 5) of the support (210) are disposed on a surface of the support facing the substrate (222), for the benefit of interconnecting an element on the support (driver 230) and elements on the substrate (pads/wiring 246c on top surface of substrate 222). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to dispose the conductors of the support on a surface of the support facing the substrate, for the benefit of interconnecting an element on the support (drive circuit 111 in Tomoda) and elements on the substrate (pads/wiring 219 in fig. 11 of Tomoda), through via interconnect (connection electrode 225, fig. 11 of Tomoda). Regarding claim 8, Tomoda remains as applied in claim 1. Tomoda further teaches the display device of claim 1, further comprising: a connection wire (219, fig. 11, paragraphs [0073][0076]) disposed on an upper surface of the substrate and connected to the connection electrode. Tomoda does not teach a back connection wire disposed on a lower surface of the substrate. In the same field of endeavor, Su teaches a back connection wire (246a, fig. 5) disposed on a lower surface of the substrate (222) and connected to the through electrodes (246b), wherein the back connection wire is connected to the support via a ball grid array (BGA) or a conductive material (244), for the benefit of interconnecting an element on the support (driver 230) and elements on the substrate (pads/wiring 246c on top surface of substrate 222). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to dispose a back connection wire on a lower surface of the substrate and connected to the at least one of the connection electrodes, wherein the back connection wire is connected to the support via a ball grid array (BGA) or a conductive material, for the benefit of interconnecting an element on the support (drive circuit 111 in Tomoda) and elements on the substrate (pads/wiring 219 in fig. 11 of Tomoda) to send image signals from driver 111 to light emitting elements in the pixels (paragraphs [0073][0076][0077] of Tomoda). Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomoda et al (PG Pub 2017/0140679 A1) as applied to claim 9 above, and further in view of Su et al (PG Pub 2020/0111771 A1). Regarding claim 14, Tomoda in view of Su teaches (see claim 7) the display device of claim 9, wherein the conductors of the support are disposed on a surface of the support facing the substrate, and the connection electrode electrically contacts at least one of the conductors. Regarding claim 15, Tomoda in view of Su teaches (see claim 8) the display device of claim 9, further comprising: a connection wire disposed on an upper surface of the substrate and connected to the connection electrode; and a back connection wire disposed on a lower surface of the substrate and connected to the connection electrode, wherein the back connection wire is connected to the support via a ball grid array (BGA) or a conductive bonding material. Response to Arguments Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the currently cited Okada teaches the added features. See rejection above. Applicant's arguments filed October 31, 2025 regarding “the substrate includes a protective insulative material” have been fully considered but they are not persuasive. Applicant argues that (pages 3 and 4) However, the asserted benefit of preventing shorting wires 219 and connectors 225 in Tomoda does not necessarily lead to all of the features of "the substrate includes a protection insulative material, wherein the connection electrode is disposed on the protection insulative material, wherein a region of the protection insulative material is exposed to the outside," as required by Claim 9. In response, Tomoda teaches the connection electrode is disposed on the substrate (fig. 11), wherein a region of the protection insulative material is exposed to the outside (exposed to the viewer, fig. 11). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Jan 22, 2024
Application Filed
Nov 12, 2024
Non-Final Rejection — §103
Feb 18, 2025
Response Filed
Apr 17, 2025
Final Rejection — §103
Jun 20, 2025
Response after Non-Final Action
Jul 21, 2025
Request for Continued Examination
Jul 23, 2025
Response after Non-Final Action
Jul 30, 2025
Non-Final Rejection — §103
Oct 31, 2025
Response Filed
Dec 22, 2025
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
78%
With Interview (-3.0%)
2y 6m
Median Time to Grant
High
PTA Risk
Based on 1060 resolved cases by this examiner. Grant probability derived from career allow rate.

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