DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Miscellaneous
The Applicant has cancelled claims 16, 18-20 and added new claim 21; therefore, only claims 1-15, 17 and 21 remain for this Office Action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 12-13, 17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parker et al. (US 2023/0163761).
In regards to claim 1, Parker discloses of a machine-memory cell comprising: a pair of parallel branches (comprised of mndiodel, mndnl and mndioder, mndnr); each of the branches consisting of: a first transistor (mndiodel, mndioder) configured to be always-ON when the memory cell is powered (see Fig 7, both have their gate connected to Vcc which would result in them being always-ON); and a second transistor (mndnl, mndnr) cross-coupled to an opposite one of the branches (see Fig 7).
In regards to claim 2, Parker discloses of the machine-memory cell of claim 1, wherein the branches join at a power node (Vcc, see Fig 7).
In regards to claim 3, Parker discloses of the machine-memory cell of claim 2, wherein the branches join at a grounded node (see Fig 7).
In regards to claim 4, Parker discloses of the machine-memory cell of claim 1, wherein the first transistor and the second transistor are NMOS-type devices (see Fig 7 and Paragraphs 0033-0035).
In regards to claim 8, Parker discloses of the machine-memory cell of claim 1, wherein each of the branches is coupled to a common power node (Vcc, see Fig 7).
In regards to claim 12, Parker discloses of a physically unclonable function cell consisting of, between a power node (Vcc) and a ground node: a pair of cross-coupled transistors (mndnl, mndnr) each arranged in series with a corresponding always-ON transistor (mndiodel, mndioder) in separate parallel branches (see Fig 7); and wherein the cross-coupled transistors (mndnl, mndnr) and the always-ON transistors (mndiodel, mndioder) are all a same MOS type (see Fig 7 and Paragraphs 0033-0035).
In regards to claim 13, Parker discloses of the physically unclonable function cell of claim 12, wherein the MOS type is NMOS (see Fig 7 and Paragraphs 0033-0035).
In regards to claim 17, Parker discloses of the physically unclonable function cell of claim 12, wherein the always-ON transistors comprise NMOS transistors (mndiodel, mndioder) gate-connected to a power supply (Vcc) of the physically unclonable function cell (see Fig 7).
In regards to claim 21, Parker discloses of a machine-memory cell comprising: a power node (Vcc) and a ground node; between the power node (Vcc) and the ground node, the machine-memory cell consisting of a pair of parallel branches (comprised of mndiodel, mndnl and mndioder, mndnr), each of the branches consisting of: a first transistor configured to be always-ON (mndiodel, mndioder) when the memory cell is powered; and a second transistor (mndnl, mndnr) cross-coupled to an opposite one of the branches (see Fig 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Parker et al. (US 2023/0163761).
In regards to claim 6, Parker discloses of the machine-memory cell of claim 1 as found within the explanation above.
Parker does not explicitly disclose of each branch consisting of wherein the first transistor and the second transistor are PMOS-type devices.
However, Parker does further disclose of an alternative HCI PUF circuit embodiment (in Fig 1) comprising: a pair of parallel branches; each of the branches comprising: a first transistor configured to be always-ON (see M1, M2) when the memory cell is powered; and a second transistor (see MN2, MN3) cross-coupled to an opposite one of the branches (see Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have an alternative embodiment with PMOS transistors in place of NMOS as taught by Parker and as notoriously well-known in the art and to account for and/or utilize the intrinsic variations of the different transistors types in the alternative embodiments.
In regards to claims 14 and 15, Parker discloses of the unclonable function cell of claim 12 as found within the explanation above.
However. Parker does not explicitly disclose of wherein the MOS type is PMOS, and wherein the always-ON transistors are grounded-gate PMOS transistors.
However, Parker does further disclose of an alternative HCI PUF circuit embodiment (in Fig 1) comprising: a pair of parallel branches; each of the branches comprising: a first transistor configured to be always-ON (see M1, M2) when the memory cell is powered; and a second transistor (see MN2, MN3) cross-coupled to an opposite one of the branches (see Fig 1); wherein the MOS type is PMOS (see Fig 1 and Paragraph 0018); and the always-ON transistors (M1, M2) are grounded PMOS transistors (see Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have an alternative embodiment with PMOS transistors in place of NMOS as taught by Parker and as notoriously well-known in the art and to account for and/or utilize the intrinsic variations of the different transistors types in the alternative embodiments.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Parker et al. (US 2023/0163761) in view of Shen et al. (US 2020/0106625).
In regards to claim 5, Parker discloses of the machine-memory cell of claim 4 as found within the explanation above.
However, Parker does not explicitly disclose of the machine-memory cell branches consisting of the four transistors as claimed above, and further comprising an NMOS-type footer transistor.
Shen discloses of a machine-memory cell comprising: a pair of parallel branches; each of the branches comprising: a first transistor configured to be always-ON (see MN4, MN5) when the memory cell is powered; and a second transistor (see MN2, MN3) cross-coupled to an opposite one of the branches; and further comprising an NMOS-type footer transistor (MN1, see Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have a machine-memory cell with an NMOS-type footer as further taught by Shen for improving efficiency by providing a current source connection that will help pull to ground.
In regards to claim 7, Parker discloses of the machine-memory cell of claim 6 as found within the explanation above.
However, Parker does not explicitly disclose of the machine-memory cell branches consisting of the four transistors as claimed above, and further comprising an PMOS-type header transistor.
Shen discloses of a machine-memory cell comprising: a pair of parallel branches; each of the branches comprising: a first transistor configured to be always-ON (see MP4, MP5) when the memory cell is powered; and a second transistor (see MP2, MP3) cross-coupled to an opposite one of the branches; and further comprising an PMOS-type header transistor (MP1, see Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have a machine-memory cell with a PMOS-type header as further taught by Shen for improving efficiency by providing a current source connection pulling the supply voltage.
Allowable Subject Matter
Claims 9-11 are allowed. The following is an examiner’s statement of reasons for allowance:
In regards to claim 9, the prior art does not disclose of nor render obvious the emphasized subject matter below, and including a circuit comprising: a plurality of physically unclonable function cells, each consisting of, in a pair of parallel branches coupled between a power node and a ground node, a pair of transistors configured to be always-ON when power is applied to the physically unclonable function cell, and a pair of cross-coupled transistors; and logic to selectively enroll the physically unclonable function cells for use in key generation, nor would it have been obvious to one of ordinary skill in the art to do so. Claims 10 and 11 are also allowed as being dependent on claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-15, 17 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844