DETAILED ACTION
Response to Amendment
This is in response to Applicants amendment filed 03/03/2026 which has been entered. Claims 1, 13, 15, 16 and 20 have been amended. Claims 5 and 14 have been cancelled. No Claims have been added. Claims 1-4, 6-13 and 15-20 are still pending in this application, with Claims 1, 13 and 20 being independent.
Response to Arguments
Applicant’s arguments with respect to Claim(s) 1-4, 6-13 and 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Bonne et al (11,625,353 B1) in view of Clad et al (2020/0322264 A1).
As per Claim 1, Bonne teaches a method of operating a network device, comprising: obtaining data packets; conveying the incoming data packets through a parallel data bus; and with a demultiplexer, splitting the incoming data packets being conveyed through the parallel data bus onto a plurality of separate data paths within the network device (Figure 1 – References 150, 160 and 162; Column 3, Lines 16-47).
(Note: In Column 3, Lines 16-29; Bonne indicates that a receiver includes a de-serializer circuit and indicates that the receiver is part of an integrated circuit which may includes a processor, accelerator, controller [i.e. network interface controller], memory, peripheral device, etc. Bonne also indicates the receiver may provide deserialized data [i.e. incoming data packets being conveyed through the parallel data bus onto a plurality of separate data paths within the network device])
(Note: In Column 3, Lines 30-47; Bonne describes performing time division demultiplexing to re-parallelize data sequences received into parallel data sequences. Bonne indicates that after the de-serialization the parallel data sequences are provided to one or more destinations [e.g. a receiver component, external component, one or more destination outside of the network device] for processing)
Bonne does not teach incoming data packets being conveyed through the parallel data bus onto a plurality of separate data paths within the network device in an alternating fashion. However, Clad teaches incoming data packets being conveyed through the parallel data bus onto a plurality of separate data paths within the network device in an alternating fashion (Page 2, Paragraph [0018] and [0020]; Page 3, Paragraphs [0027] and [0028]).
(Note: In paragraph [0027], Clad describes segment routing for traffic engineering [SR-TE] policies used to steer traffic through a network. Clad indicates that each SR-TE policy may be a local SR-TE per-destination policy or a local SR-TE per-flow policy. Clad also indicates that a per-flow policy may be configured with a forward-class 0 associated with a per-destination policy P1 and also that that a per-flow policy may be configured with a forward-class 1 associated with a per-destination policy P2)
(Note: In paragraph [0028], Clad indicates that the Forward-Class marking is an attribute that is passed along with the packet during its processing on the router and provides an example where voice traffic is distinguished from other traffic [e.g. Voice traffic is marked with forward class 1 while the rest of the traffic is marked with forward class 0]. As a result, voice traffic may be sent on paths associated with low latency while all other traffic may be sent over high latency paths – i.e. incoming data packets being conveyed through the parallel data bus onto a plurality of separate data paths within the network device in an alternating fashion)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne with the method taught by Clad to provide aggregated traffic received from a multiplexer to a network packet broker [i.e. steering network] to enable real-time parsing of packet headers allowing the routing of latency sensitive traffic [e.g. voice or video] through the most direct or fastest pathways ensure quality of service [QoS] requirements and service level agreements [SLAs] are met.
As per Claim 2, Bonne teaches with an ingress port, receiving data bits; and with a network interface receiver, converting the received data bits to obtain the incoming data packets (Figure 8 – References 808 and 812; Column 2, Lines 41-54; Column 12, Lines 35-64).
As per Claim 3, Bonne teaches buffering at least some of the incoming data packets being conveyed through the parallel data bus (Figure 2 – Reference 202; Column 4, Lines 21-27).
As per Claim 4, Bonne teaches packing the incoming data packets back-to-back on the parallel data bus (Figure 1 – Reference 150; Column 2, Line 59 – Column 3, Line 15).
As per Claim 8, Bonne teaches with a multiplexer, aggregating data packets from the plurality of data paths onto an egress parallel data bus (Figure 1 – References 110 and 112; Figure 8 – References 808 and 812; Column 2, Lines 41-54; Column 10, Lines 56-66; Column 12, Lines 35-64).
Claim(s) 6, 7, 9-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bonne et al (11,625,353 B1) in view of Clad et al (2020/0322264 A1) as applied to Claims 1 and 13 above, and further in view of Richter et al (2020/0110714 A1).
As per Claims 6, 7, 15 and 16, the combination of Bonne and Clad teaches the method of Claims 1 and 13. Bonne also teaches wherein the parallel data bus has a first bus width; a first of the plurality of data paths has a second bus width equal to the first bus width; a second of the plurality data paths has a third bus width equal to the first bus width (Column 2, Lines 36-47).
(Note: Bus width is a reference to the number of bits transferring simultaneously – as an example an 8-bit bus moves 8 times more data per cycle than a 2-bit bus enabling faster data transfer and processing. Therefore an 8-bit bus is wider than a 2-bit bus. In Column 2, Lines 36-47; Bonne indicates that parallel data segments may be implemented as one or more data signals. Boone also indicates data segments may be a 1-bit data bus, 2-bit data bus, 8-bit data bus or a 16-bit data bus)
(Note: So, in a circumstance where there are three data paths each carrying 2-bits then the parallel data bus has a first bus width; a first of the plurality of data paths has a second bus equal to the first bus width; and a second of the plurality of data paths has a third bus equal to the first bus width. Additionally, in a circumstance where a first data path is 16-bit and a second and third paths are 8-bit the recitation of the claims are read upon)
The combination of Bonne and Clad does not teach at least one of the data packets includes a number of bits greater than the second bus width. However, Richter teaches at least one of the data packets including a number of bits greater than the second bus width (Page 10, Paragraph [0099]; Page 11, Paragraph [0102]).
(Note: In paragraph [0099], Richter describes a quantity of bits to be transferred [e.g. packet size for a read or write operation] during 6 clock cycles as being 240 bits which breaks down to 40 bits per clock cycle. Richter also describes a quantity of control bits to be transferred [e.g. for two read operations] as being 48 bits which breaks down to 24 bits per clock cycle. As described above, Boone also indicates data segments may be a 1-bit data bus, 2-bit data bus, 8-bit data bus or a 16-bit data bus. Both of the packets described by Richter are greater than the bus width described by Bonne meeting the recitations of the claimed language)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claims 9 and 17, the combination of Bonne, Clad and Richter teaches wherein at least some of the data packets being aggregated onto the egress parallel data bus are separated by one or more gaps. (Note: The primary advantage of having gaps between aggregated data packets on an egress parallel data bus is to prevent signal integrity issues allowing essential processing steps thereby ensuring reliable and efficient high-speed data transmission)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claims 10 and 18, the combination of Bonne, Clad and Richter teaches wherein at least some of the data packets being aggregated onto the egress parallel data bus are not separated by one or more gaps. (Note: The primary advantage of having gaps between aggregated data packets on an egress parallel data bus is the significant improvement of performance by maximizing bandwidth utilization and increasing throughput while simultaneously minimizing latency and overhead)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claim 11, the combination of Bonne, Clad and Richter teaches with a network interface transmitter, converting the aggregated data packets on the egress parallel data bus into corresponding output data bits; and transmitting the output data bits via an egress port as described in Claims 1 and 8 above.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claim 12, the combination of Bonne, Clad and Richter teaches buffering at least some of the aggregated data packet traversing through the multiplexer as described in Claims 1 and 3. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claim 13, the combination of Bonne, Clad and Richter teaches a method of operating a network device. Boone teaches conveying first data packets through a first parallel data path, conveying second data packets through a second parallel data path having a second bus; and with a multiplexer, aggregating the first data packets being conveyed through the first parallel data path and the second data packets being conveyed through the second parallel data path onto an egress parallel data bus as described in Claim 1.
The combination of Bonne, Clad and Richter teaches wherein at least one of the first data packets includes a first number of bits that are conveyed through the first parallel data path over consecutive cycles, and wherein the first parallel data path has a first bus width less than the first number of bits; and conveying second data packets through a second parallel data path having a second bus width equal to the first bus width (See Claim 6 for evidence of a second parallel data path having a second bus width equal to the first bus width).
(Note: In paragraph [0099], Richter describes a quantity of bits to be transferred [e.g. packet size for a read or write operation] during 6 consecutive clock cycles as being 240 bits which breaks down to 40 bits per clock cycle. Richter also describes a quantity of control bits to be transferred [e.g. for two read operations] as being 48 bits which breaks down to 24 bits per clock cycle. As described above, Boone also indicates data segments may be a 1-bit data bus, 2-bit data bus, 8-bit data bus or a 16-bit data bus)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claim 19, the combination of Bonne, Clad and Richter teaches obtaining incoming data packets based on data bits received via an ingress port; conveying the incoming data packets through an ingress parallel data bus; and with a demultiplexer, splitting the incoming data packets being conveyed through the ingress parallel data bus into the first data packets to be conveyed through the first parallel data path and the second data packets to be conveyed through the second parallel data path as described above in Claims 1, 2 and 13.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Bonne and Clad with the method taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
As per Claim 20, the combination of Bonne, Clad and Richter teaches the network device as described in Claims 1 and 13. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and device taught by Bonne and Clad with the method and device taught by Richter to increase data transfer speed and improve bus efficiency over shorter distances by leveraging the parallel bus’s inherent ability to move multiple bits of data simultaneously.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al (2014/0029611 A1), Gummalla et al (2003/0072304 A1), Song et al (2013/0111122 A1), SUDHAKARAN et al (2013/0266047 A1), Parthasarathy (2005/0094734 A1), Kajigaya et al (2013/0082404 A1), Issac et al (2011/0255411 A1), Cowell et al (2006/0107186 A1), Tran (2005/0190690 A1) and Ono (7,149,932 B2). Each of these describes systems and methods to transmit data packets using a plurality of buses.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHARYE POPE whose telephone number is (571)270-5587. The examiner can normally be reached Monday - Friday 8AM - 4PM.
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KHARYE POPE
Primary Examiner
Art Unit 2693
/KHARYE POPE/Primary Examiner, Art Unit 2693
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