DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Response to Arguments
3. Applicant’s argument filed on 07/24/2026 with respect claims 1-20 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of " determine a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding."
Examiner respectfully disagrees and asserts the reference of Xiong et al. (US 11,146,290 B1)" in column 13, lines 11-28 and Fif. 4 teaches such limitation. For example, in 440, the decoder 130 (e.g., the flipping test module 350) may perform a test according to the flipping probabilities to determine at least one target bit node that is required to be flipped. In the flipping tests, each bit node in the group may be determined whether to be flipped according to its corresponding flipping probability. For example, a bit node with a 70% flipping probability may have a 70% chance to be flipped and a 30% (i.e., 1-70%) chance not to be flipped in the flipping test. For illustration purposes, for the bit node with a 70% flipping probability, a random value between 0 to 1 may be generated. If the generated random value is within the range of 0 to 0.7 (which corresponds to the 70% flipping probability), the bit node may be required to be flipped. If the generated random value is within the range of 0.7 to 1 (which corresponds to the 30% non-flipping probability), the bit node may not be flipped. After the flipping tests, the bit node(s) that is required to be flipped may be determined as the target bit node(s).
Also, the applicant contends that the cited references fail to teaches or suggest “bypass flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration.” The examiner respectfully disagrees and asserts the reference of Zhang et al. (US 2021/0143836 A1) in paragraphs [0062] and [0075] teaches the limitation above. For example, the adaptive flipping threshold T is generated based on the iteration number, the number of unsatisfied check nodes of the previous iteration, and/or the number of variable nodes flipped in the previous iteration. See paragraph [0062].
The conditional bit-flipping is followed by recomputing the syndrome (s_new) and the checksum value (C) 820. If the checksum value is equal to zero (operation 825), then the bit-flipping decoder is stopped since the received codeword has been correctly decoded. If the checksum is not equal to zero, then the syndrome and checksum values are updated 830, and the threshold is updated 835. In an example, the threshold is updated based on the iteration number, the number of unsatisfied check nodes of the previous iteration, and/or the number of variable nodes flipped in the previous iteration. See paragraph [0075].
As described above, it’s clear that the decoder 130 (e.g., the flipping test module 350) may perform a test according to the flipping probabilities to determine at least one target bit node that is required to be flipped (which is similar to the claim feature “an indication of a bit of a subset of bits previously flipped in a previous iteration) because in step 445 the decoder 130 (e.g., the processing module 330) may flip the at least one target bit node to update a value (the value from previous iteration at step 440) of the at least one target bit node. Emphasis added. For the Applicant’s convenience, see Fig. 4 is reproduced below.
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Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
4. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claim 1:
The claim recites “A method comprising: receiving a codeword from a memory device, wherein the codeword includes a plurality of bits and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding; determining a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding; selecting a current bit of the plurality of bits in a current iteration of bit flipping; determining the current bit satisfies a bit flipping criterion; detecting a risk of a stall condition in the multiple iterations; determining, using the bit flip data structure, the current bit was flipped in the previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion; and bypassing flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim recites a series of steps and, therefore, is a process, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “determining a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding; selecting a current bit of the plurality of bits in a current iteration of bit flipping; determining the current bit satisfies a bit flipping criterion; detecting a risk of a stall condition in the multiple iterations; determining, using the bit flip data structure, the current bit was flipped in the previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion; and bypassing flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “receiving a codeword from a memory device, wherein the codeword includes a plurality of bits and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding” does not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering. These extra-solution activities do not provide practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. Therefore, the claim is not patent eligible.
As per claim 8:
The claim recites “A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a codeword from a memory device, wherein the codeword includes a plurality of bits and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding;
determine a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding; select a current bit of the plurality of bits in a current iteration of bit flipping; determine the current bit satisfies a bit flipping criterion; detect a risk of a stall condition in the multiple iterations; determine, using the bit flip data structure, the current bit was flipped in the previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion; and bypass flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim recites a non-transitory computer-readable storage medium and, therefore, is a machine/manufacture, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “determine a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding; select a current bit of the plurality of bits in a current iteration of bit flipping; determine the current bit satisfies a bit flipping criterion; detect a risk of a stall condition in the multiple iterations; determine, using the bit flip data structure, the current bit was flipped in the previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion; and bypass flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “receive a codeword from a memory device, wherein the codeword includes a plurality of bits and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding” does not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering. These extra-solution activities do not provide practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “A non-transitory computer-readable storage medium” is generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept.
As per claim 15:
The claim recites “A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to: receive a codeword from a memory device, wherein the codeword includes a plurality of bits and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding; determine a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding; select a current bit of the plurality of bits in a current iteration of bit flipping; determine the current bit satisfies a bit flipping criterion; detect a risk of a stall condition in the multiple iterations, wherein detecting the risk of the stall condition includes determining that an iteration count of the multiple iterations satisfies an iteration count threshold; determine, using the bit flip data structure, the current bit was flipped in a previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion; and bypass flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim recites a system and, therefore, is a machine/manufacture, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “determine a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding; select a current bit of the plurality of bits in a current iteration of bit flipping; determine the current bit satisfies a bit flipping criterion; detect a risk of a stall condition in the multiple iterations, wherein detecting the risk of the stall condition includes determining that an iteration count of the multiple iterations satisfies an iteration count threshold; determine, using the bit flip data structure, the current bit was flipped in a previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion; and bypass flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “receive a codeword from a memory device, wherein the codeword includes a plurality of bits and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding” does not integrate the abstract idea into a practical application because is generic computer function of data mere data gathering. These extra-solution activities do not provide practical application. At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “A system, “a memory device,” “a processing device” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Dependent claims 2-7, 9-14, and 16-20 are extended elements of the abstract idea of the independent claims and the claims are abstract in nature falling withing Mental Processes. The dependent claims do not add any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstracts idea. Therefore, the dependent claims are not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1, 4, 7, 8, 11, 14, 15, and 18 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Xiong et al. (US 11,146,290 B1)"herein after as Xiong" in view of Zhang et al. (US 2021/0143836 A1) "herein after as Zhang."
As per claims 1, 8, and 15:
Xiong substantially teaches or discloses a method comprising: receiving a codeword from a memory device (see abstract, column 1, lines 35-36, herein a system for decoding a received LDPC codeword may be provided, and Fig. 4 step 405), wherein the codeword includes a plurality of bits (see column 1, lines 43-44, herein the received LDPC codeword including a plurality of bits) and decoding the codeword includes flipping one or more bits over multiple iterations of bit flipping decoding (see column 1, lines 46-50, herein decoding the received LDPC codeword by estimating values with respect to the LDPC codeword at the plurality of bit nodes and the plurality of check nodes in an iterative process including one or more iterations); determining a bit flip data structure including an indication of a bit of a subset of bits previously flipped in a previous iteration of bit flipping decoding (see column 13, lines 11-19, herein In 440, the decoder 130 (e.g., the flipping test module 350) may perform a test according to the flipping probabilities to determine at least one target bit node that is required to be flipped. In the flipping tests, each bit node in the group may be determined whether to be flipped according to its corresponding flipping probability. For example, a bit node with a 70% flipping probability may have a 70% chance to be flipped and a 30% (i.e., 1-70%) chance not to be flipped in the flipping test, and Fig. 4, step 440); selecting a current bit of the plurality of bits in a current iteration of bit flipping (see column 1, lines 46-58, herein decoding the received LDPC codeword by estimating values with respect to the LDPC codeword at the plurality of bit nodes and the plurality of check nodes in an iterative process including one or more iterations. At least one iteration of the one or more iterations may include: determining a syndrome weight based on current values of the plurality of bit nodes and the parity check matrix; determining whether the syndrome weight is equal to zero; in response to determining that the syndrome weight is not equal to zero, determining one or more flipping reliabilities of the plurality of bit nodes, each flipping reliability representing a reliability of a flipping operation on one of the plurality of bit nodes); determining, using the bit flip data structure, the current bit satisfies a bit flipping criterion (see column 6, lines 46-50, herein A conventional bit-flipping method usually decides whether to flip a bit node simply based on the flipping energy. For example, if the flipping energy is greater than a threshold, the hard decision of the bit node is flipped; otherwise, the hard decision of the bit node is not flipped); detecting a risk of a stall condition in the multiple iterations (see column 1, lines 52-56, herein determining a syndrome weight based on current values of the plurality of bit nodes and the parity check matrix; determining whether the syndrome weight is equal to zero; in response to determining that the syndrome weight is not equal to zero; and column 9, lines 18-22); determining the current bit was flipped in a previous iteration of bit flipping in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion (see column 1, lines 55-59, herein in response to determining that the syndrome weight is not equal to zero, determining one or more flipping reliabilities of the plurality of bit nodes, each flipping reliability representing a reliability of a flipping operation on one of the plurality of bit nodes; and column 2, lines 22-25, herein in response to determining that the syndrome weight is greater than the syndrome weight threshold, designating a preset flipping reliability as the one or more flipping reliabilities of the plurality of bit nodes, and Fig. 4, step 440). Xiong does not explicitly teach bypassing flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration. However, Zhang in the same the field of endeavor teaches bypassing flipping of the current bit in response to determining, using the bit flip data structure, the current bit was flipped in the previous iteration (see paragraph [0075], herein the conditional bit-flipping is followed by recomputing the syndrome (s_new) and the checksum value © 820. If the checksum value is equal to zero (operation 825), then the bit-flipping decoder is stopped since the received codeword has been correctly decoded. If the checksum is not equal to zero, then the syndrome and checksum values are updated 830, and the threshold is updated 835. In an example, the threshold is updated based on the iteration number, the number of unsatisfied check nodes of the previous iteration, and/or the number of variable nodes flipped in the previous iteration, and Fig. 8 steps 820 &825). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Xiong with the teachings of Zhang by bypassing flipping of the current bit in response to determining the current bit was flipped in the previous iteration.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the bypassing flipping of the current bit in response to determining the current bit was flipped in the previous iteration would have improved the convergence of a bit-flipping decoder (see paragraph [0074] of Zhang).
As per claims 4, 11, and 18:
Zhang teaches that setting the current bit to a next bit of the plurality of bits; determining the current bit was not flipped in a previous iteration of bit flipping in response to determining the current bit satisfies the bit flipping criterion; and flipping the current bit in response to determining the current bit satisfies the bit flipping criterion and was not flipped in the previous iteration (see paragraph [0075], herein the conditional bit-flipping is followed by recomputing the syndrome (s_new) and the checksum value (C) 820. If the checksum value is equal to zero (operation 825), then the bit-flipping decoder is stopped since the received codeword has been correctly decoded. If the checksum is not equal to zero, then the syndrome and checksum values are updated 830, and the threshold is updated 835. In an example, the threshold is updated based on the iteration number, the number of unsatisfied check nodes of the previous iteration, and/or the number of variable nodes flipped in the previous iteration, and Fig. 8 steps 820 &825).
As per claims 7 and 14:
Xiong teaches that wherein detecting the risk of the stall condition includes determining that an iteration count of the multiple iterations satisfies an iteration count threshold (see column 2, lines 19-25, herein the determining one or more flipping reliabilities of the plurality of bit nodes may include: determining whether the syndrome weight is greater than a syndrome weight threshold; and in response to determining that the syndrome weight is greater than the syndrome weight threshold, designating a preset flipping reliability as the one or more flipping reliabilities of the plurality of bit nodes).
6. Claims 2, 3, 5, 6, 9, 10, 12, 13, 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Xiong et al. (US 11,146,290 B1)"herein after as Xiong" in view of Zhang et al. (US 2021/0143836 A1) "herein after as Zhang" in further view of Pele et al. (US 11,838,032 B1) "herein after as Pele."
As per claims 2, 9, and 16:
Xiong-Zhang as combined does not teach removing the indication in the bit flipping memory the current bit was previously flipped in response to bypassing flipping of the current bit. However, Pele in the same the field of endeavor teaches removing the indication in the bit flipping memory the current bit was previously flipped in response to bypassing flipping of the current bit (see column 10, lines 47-58, herein FIG. 4C illustrates a third state 440 of error correcting code according to at least one example. After the second bit 405 and its connected error code bits 410 in the second state 420 (shown in FIG. 4B) are flipped, the system reaches the third decoding state 440. At this point, the first bit 405 is still in error from the first state 400 (shown in FIG. 4A) and the two error code bits 410 connected to the first bit 405 are set to one. Since the two error code bits 410 for the first data bit 405 are set to one, the system selects the first data bit 405 and its two connected error code bits 410 to be flipped. After these bits are flipped, then the system has removed all of the errors and returned to the first state 400). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Xiong-Zhang as combined with the teachings of Pele by removing the indication in the bit flipping memory the current bit was previously flipped in response to bypassing flipping of the current bit.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the removing the indication in the bit flipping memory the current bit was previously flipped in response to bypassing flipping of the current bit improved the system performance.
As per claims 3, 10, and 17:
Xiong-Zhang as combined does not teach setting the current bit to a next bit of the plurality of bits; and removing an indication in a bit flipping memory the current bit was previously flipped in response to determining the current bit does not satisfy the bit flipping criterion. However, Pele in the same the field of endeavor teaches setting the current bit to a next bit of the plurality of bits; removing the indication in the bit flipping memory the current bit was previously flipped in response to bypassing flipping of the current bit (see column 10, lines 47-58, herein FIG. 4C illustrates a third state 440 of error correcting code according to at least one example. After the second bit 405 and its connected error code bits 410 in the second state 420 (shown in FIG. 4B) are flipped, the system reaches the third decoding state 440. At this point, the first bit 405 is still in error from the first state 400 (shown in FIG. 4A) and the two error code bits 410 connected to the first bit 405 are set to one. Since the two error code bits 410 for the first data bit 405 are set to one, the system selects the first data bit 405 and its two connected error code bits 410 to be flipped. After these bits are flipped, then the system has removed all of the errors and returned to the first state 400). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Xiong-Zhang as combined with the teachings of Pele by setting the current bit to a next bit of the plurality of bits; and removing an indication in a bit flipping memory the current bit was previously flipped in response to determining the current bit does not satisfy the bit flipping criterion.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the setting the current bit to a next bit of the plurality of bits; and removing an indication in a bit flipping memory the current bit was previously flipped in response to determining the current bit does not satisfy the bit flipping criterion improved the system performance.
As per claims 5, 12, and 19:
Pele teaches that adding an indication in a bit flipping memory that the current bit was flipped, wherein the indication is one of a plurality of indications in the bit flipping memory evaluated in a subsequent iteration of bit flipping decoding to determine if a subsequent current bit in the subsequent iteration was previously flipped (see column 13, lines 15-19, herein if the current clock is less than the maximum clock, the system determines (525) the current SW for the simulation episode by adding together all of the error code bits (e.g., error code bits 410 (FIG. 4A)) or counting the number of error code bits that are not zero).
As per claims 6, 13, and 20:
Pele teaches that removing an oldest indication in the bit flipping memory in response to determining there is insufficient storage for the indication that the current bit was flipped (see column 10, lines 52-59, herein the first bit 405 is still in error from the first state 400 (shown in FIG. 4A) and the two error code bits 410 connected to the first bit 405 are set to one. Since the two error code bits 410 for the first data bit 405 are set to one, the system selects the first data bit 405 and its two connected error code bits 410 to be flipped. After these bits are flipped, then the system has removed all of the errors and returned to the first state 400, and column 13, lines 32-44).
Examiner Notes
7. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
8. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
Prosecution Insights