DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 12-21 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 2015/0162307 in view of Kuan et al. US 2023/0124098.
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Chen et al. US 2015/0162307
Regarding claim 1, Chen et al. in Fig. 5A and [0035]-[0038] disclose an integrated circuit device package comprising:
a substrate 18;
at least two integrated circuit dies 10, 12 mounted to the substrate 18; and
a thermally conductive stiffener (i.e. contour lid 62/22) attached to the substrate 18, the stiffener:
having a first portion (annotated above) in a thermally conductive relationship with a surface of a first integrated circuit die 12 among the at least two integrated circuit dies to provide a first heat dissipation mode for the first integrated circuit die, and
having a second portion (annotated above), different from the first portion, the second portion configured to provide a second heat dissipation mode, different from the first heat dissipation mode, for a second integrated circuit die 10 among the at least two integrated circuit dies.
Chen et al. do not expressly disclose the contour lid 62/66 is attached to the substrate 18 to counteract warping of the substrate and an electrically conductive adhesive 60 disposed between the thermally conductive stiffener and the substrate for attaching the stiffener to the substrate, the adhesive and the stiffener being configured to form a shielding enclosure to shield one or more of the at least two integrated circuit dies from electromagnetic interference.
Kuan et al. teach in Fig. 5 and [0038] a semiconductor package with warpage control including an electrically conductive and/or non-conductive adhesive 550 used when a stiffener 530 is made of an electrically conductive material. In one aspect, an electrically conductive adhesive 550 can be disposed such that the adhesive 550 will be in contact with ground contact pads 590 on the package substrate 510 and the stiffener 530 to ground the stiffener and thereby enable the stiffener 530 to provide electromagnetic interference or radio-frequency interference shielding benefits when the stiffener 530 is made of an electrically conductive material.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kuan et al. in the integrated circuit of Chen et al. for the purpose of warpage control and to protect the integrated circuit dies from electromagnetic interference.
Regarding claim 2, Chen et al. in view of Kuan et al. teach the device package of claim 1. Chen et al. in Fig. 5A and [0035]-[0038] teach wherein the stiffener 62/66 [0020]-[0038] is configured to:
overlay the first integrated circuit die 12 among the at least two integrated circuit dies; and
define an opening 70 [0023] at least partially exposing a surface of the second integrated circuit die 10 among the at least two integrated circuit dies to provide the second heat dissipation mode for the second integrated circuit die 10 among the at least two integrated circuit dies.
Regarding claim 3, Chen et al. in view of Kuan et al. teach the device package of claim 2. Chen et al. in Fig. 5A and [0035]-[0038] teach the device package of claim 2, further comprising a heat sink 72a, 72b [0023]-[0037] the heat sink being:
disposed in a thermally conductive relationship with the second integrated circuit die 10 among the at least two integrated circuit dies through the opening in the stiffener 62/66 [0020]-[0038]; and
configured to dissipate heat from the second integrated circuit die 10 among the at least two integrated circuit dies.
Regarding claim 4, Chen et al. in view of Kuan et al. teach the device package of claim 3. Chen et al. in Fig. 5A and [0035]-[0038] teach wherein the heat sink 72a, 72b [0023]-[0037] is disposed in a thermally conductive relationship with the second integrated circuit die 10 among the at least two integrated circuit dies without being in thermally conductive contact with the first integrated circuit die 12 among the at least two integrated circuit dies.
Regarding claim 5, Chen et al. in view of Kuan et al. teach the device package of claim 1. Chen et al. in Fig. 5A and [0035]-[0038] teach the device package of claim 1, further comprising a heat sink 72a, 72b [0023]-[0037] disposed in a thermally conductive relationship with the stiffener 62/66 [0020]-[0038], the heat sink 72a, 72b [0023]-[0037] being configured to dissipate heat from the first integrated circuit die 12 [0026] among the at least two integrated circuit dies.
Regarding claim 6, Chen et al. in view of Kuan et al. teach the device package of claim 1. Chen et al. in Fig. 5A and [0035]-[0038] teach the device package of claim 1, further comprising a thermal interface material (TIM) 58b [0019] disposed between the first portion of the stiffener and the surface of the first integrated circuit die 12 among the at least two integrated circuit dies, the TIM thermally coupling the first portion of the stiffener 62/66 [0020]-[0038] to the first integrated circuit die 12 among the at least two integrated circuit dies.
Regarding claim 7, Chen et al. in view of Kuan et al. teach the device package of claim 6. Chen et al. in Fig. 5A and [0035]-[0038] teach wherein the TIM 58b comprises a thermally-conductive polymer [0019].
Regarding claim 8, Chen et al. in view of Kuan et al. teach the device package of claim 6. Chen et al. in Fig. 5A and [0035]-[0038] teach wherein the TIM 58b is a metallic TIM comprising at least one of indium or gallium [0019].
Regarding claim 9, Chen et al. in view of Kuan et al. teach the device package of claim 1. Kuan et al. in [0031] teach wherein the stiffener 230 comprises at least one of stainless steel or nickel-coated copper.
Regarding claim 12, Chen et al. in view of Kuan et al. teach the device package of claim 1. Kuan et al. in [0038] teach wherein the adhesive 550 is electrically grounded.
Regarding claim 13, Chen et al. in [0010]-[0038] disclose method for packaging an integrated circuit comprising:
a substrate 18; and at least two integrated circuit dies 10, 12 mounted to the substrate 18; the method comprising:
attaching a thermally conductive stiffener (i.e. contour lid 62/22) to the substrate 18,
arranging a first portion (annotated above) of the stiffener in a thermally conductive relationship with a surface of a first integrated circuit die 12 among the at least two integrated circuit dies to provide a first heat dissipation mode for the first integrated circuit die, and
arranging a second portion (annotated above) of the stiffener, different from the first portion, the second portion configured to provide a second heat dissipation mode, different from the first heat dissipation mode, for a second integrated circuit die 10 among the at least two integrated circuit dies.
Chen et al. do not expressly disclose attaching the stiffener to the substrate 18 with an electrically conductive adhesive disposed between the thermally conductive stiffener and the substrate, to counteract warping of the substrate and to form a shielding enclosure to shield one or more of the at least two integrated circuit dies from electromagnetic interference.
Kuan et al. teach in Fig. 5 and [0038] a semiconductor package and method of making the semiconductor package with warpage control including an electrically conductive and/or non-conductive adhesive 550 used when a stiffener 530 is made of an electrically conductive material. In one aspect, an electrically conductive adhesive 550 can be disposed such that the adhesive 550 will be in contact with ground contact pads 590 on the package substrate 510 and the stiffener 530 to ground the stiffener and thereby enable the stiffener 530 to provide electromagnetic interference or radio-frequency interference shielding benefits when the stiffener 530 is made of an electrically conductive material.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kuan et al. in the integrated circuit of Chen et al. for the purpose of warpage control and to protect the integrated circuit dies from electromagnetic interference.
Regarding claim 14, Chen et al. in view of Kuan et al. teach the method according to claim 13 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach the method, further comprising:
configuring the stiffener 62/66 [0020]-[0038] to overlay the first integrated circuit die 12 among the at least two integrated circuit dies; and
at least partially exposing, through an opening 70 [0023] in the stiffener 62/66, a surface of the second integrated circuit die 10 among the at least two integrated circuit dies to provide the second heat dissipation mode for the second integrated circuit die 10 among the at least two integrated circuit dies.
Regarding claim 15, Chen et al. in view of Kuan et al. teach the method according to claim 14 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach the method, further comprising:
disposing a heat sink 72a, 72b [0023]-[0037] in a thermally conductive relationship with the second integrated circuit die 10 among the at least two integrated circuit dies through the opening 70 [0023] in the stiffener 62/66; and
configuring the heat sink 72a,72b [0023]-[0037] to dissipate heat from the second integrated circuit die 10 among the at least two integrated circuit dies.
Regarding claim 16, Chen et al. in view of Kuan et al. teach the method according to claim 15 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach the method, further comprising:
disposing the heat sink 72a, 72b [0023]-[0037] in a thermally conductive relationship with the second integrated circuit die 10 among the at least two integrated circuit dies without being in thermally conductive contact with the first integrated circuit die 12 among the at least two integrated circuit dies.
Regarding claim 17, Chen et al. in view of Kuan et al. teach the method according to claim 13 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach the method, further comprising:
disposing a heat sink 72a, 72b [0023]-[0037] in a thermally conductive relationship with the stiffener 62/66 [0020]-[0038], the heat sink 72a, 72b being configured to dissipate heat from the first integrated circuit die 12 among the at least two integrated circuit dies [0023]-[0037].
Regarding claim 18, Chen et al. in view of Kuan et al. teach the method according to claim 13 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach the method, further comprising:
disposing a thermal interface material (TIM) 58b [0019] between the first portion of the stiffener 62/66 [0020]-[0038] and the surface of the first integrated circuit die 12 among the at least two integrated circuit dies, the TIM 58b thermally coupling the first portion of the stiffener 62/66 to the first integrated circuit die 12 among the at least two integrated circuit dies.
Regarding claim 19, Chen et al. in view of Kuan et al. teach the method according to claim 18 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach wherein disposing the TIM 58b comprises disposing a heat-dissipating polymer [0019].
Regarding claim 20, Chen et al. in view of Kuan et al. teach the method according to claim 18 for packaging an integrated circuit. Chen et al. in Fig. 5A and [0010]-[0038] teach wherein disposing the TIM 58b comprises disposing a metallic TIM comprising at least one of indium or gallium [0019].
Regarding claim 21, Chen et al. in view of Kuan et al. teach the method according to claim 13 for packaging an integrated circuit. Kuan et al. in [0031] teach wherein attaching the stiffener 230 comprises attaching a stiffener comprising at least one of stainless steel or nickel-coated copper.
Regarding claim 24, Chen et al. in view of Kuan et al. teach the method according to claim 13 for packaging an integrated circuit. Kuan et al. in [0038] teach the method, further comprising: electrically grounding the adhesive 550.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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