DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4,6-10 and 12-22 are pending for examination.
This Office Action is Non-Final.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/18/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIU et al. (US 20210349777 A1, hereinafter “LIU”).
Regarding Claim 8, LIU discloses a method implemented by a first device (Fig. 2; [0072]: first PCIe device GPU 2052), wherein the method comprises:
generating, when a fault occurs in a first transceiver of the first device ([0068]: when the hardware fault occurs on the first PCIe device, a fault packet may be sent to the fault processing apparatus. The fault packet is used to notify the fault processing apparatus that a PCIe link (or a PCIe device) communicating with the fault processing apparatus is faulty. PCIe link of first PCIe device is a first transceiver), fault information comprising an index value corresponding to a fault cause of the first transceiver of the fault ([0072]: if the hardware fault occurs on the first PCIe device, the first PCIe device may send a fault report message to the root complex 203. The fault report message carries information such as a fault type of the PCIe device and a device identifier of the PCIe device. [0068]: fault packet used to notify that a PCIe link (or a PCIe device) is faulty. [0076]: fault type includes correctable error (CE) or uncorrectable error (UCE) of the PCIe link. Sending encompasses generating the message before sending. Fault cause interpreted as fault type. Consistent with [0028] of Spec, where “fault cause includes at least one of single-bit fault in a memory, a multi-bit fault in the memory, and an internal bus transmission fault.” Specific value of fault cause written in the message interpreted as an index value); and
sending, to a second device (Fig. 2: root complex 203 + CPU 201), the fault information, wherein, when the fault occurs, the first device sends the index value corresponding to the fault cause and does not send an interrupt signal indicating that the fault occurs ([0072]: see above – sent to root complex 203 of (root complex 203 + CPU 201) as a message, not as an NMI or SMI interrupt signal as described as generated by other components after message is sent).
Regarding Claim 9, LIU discloses the method of claim 8, as referenced above, further comprising determining, based on a preset correspondence, the index value ([0072]; [0076]: two fault types: CE or UCE. Therefore, to send the fault report message, which carries the fault type, the fault type value of the message (“index”) is effectively determined to be included in the message. Fault type value may be chosen among the two possible types, CE or UCE (preset correspondence)), and wherein the preset correspondence comprises a one-to-one correspondence between the fault cause and the index value ([0072]; [0076]: fault cause is a fault type (see claim 8). By definition, CE and UCE are mutually exclusive. Thus, the value of the first PCIe device’s fault type is a 1:1 correspondence to {CE, UCE}).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 14-18, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of McDonald et al. (US 6496900 B1, hereinafter “McDonald”).
Regarding Claim 1, LIU discloses a system (Fig. 2) comprising:
a first device comprising a first transceiver (Fig. 2; [0072]: first PCIe device is GPU 2052. [0060]: GPU 2052 connected through hardware layer 20 (e.g., root complex 203) through a PCIe link (“transceiver”)) and configured to:
generate, when a fault occurs in the first transceiver, fault information comprising an index value corresponding to a fault cause of the fault of the first transceiver ([0068]: when the hardware fault occurs on the first PCIe device, a fault packet may be sent to the fault processing apparatus. The fault packet is used to notify the fault processing apparatus that a PCIe link (or a PCIe device) communicating with the fault processing apparatus is faulty. [0072]: The fault report message carries information such as a fault type of the PCIe device and a device identifier of the PCIe device … if the hardware fault occurs on the first PCIe device, the first PCIe device may send a fault report message to the root complex 203. Sending the fault report message encompasses generating the message before sending. Fault cause interpreted as fault type. Consistent with [0028] of Spec, where “fault cause includes at least one of single-bit fault in a memory, a multi-bit fault in the memory, and an internal bus transmission fault.” Specific value of fault cause written in the message interpreted as an index value); and
send the fault information, wherein, when the fault occurs, the first device sends the index value corresponding to the fault cause and does not send an interrupt signal indicating that the fault occurs ([0072]: see above – sent to root complex 203 as a message, not as an NMI or SMI interrupt signal as described as generated by other components after message is sent); and
a second device (Fig. 2; [0072]: root complex 203 + CPU 201) comprising:
a second transceiver comprising a storage space (Fig. 2; [0072]: root complex 203 + (not shown) corresponding register) and configured to:
receive the fault information ([0072]: root complex 203 receives the fault reporting message and writes information such as the device identifier and fault type of the first PCIe device that are carried in the message into a register corresponding to the root complex);
store the fault information in the storage space ([0072]); and
send a notification signal ([0072]: root complex 203 generates an SMI interrupt signal and reports the SMI interrupt signal to BIOS); and
a processor coupled to the second transceiver (Fig. 2: CPU 201 coupled to root complex 203) and configured to:
receive the notification signal ([0072]: BIOS receives SMI interrupt signal. Examiner takes Official Notice that it is inherent that BIOS is executed by a processor. Therefore, all data received by BIOS (e.g., SMI interrupt signal) is also received by the processor (e.g., CPU 201) executing BIOS); and
LIU does not teach:
read the fault information from the storage space.
However, McDonald teaches:
a processor… configured to: read the fault information from the storage space (Col 4, lines 6-11: the host processor may read an error register to determine the type of error that occurred, and then invoke an appropriate error handler)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU and McDonald by implementing the register read taught by McDonald. One of ordinary skill in the art would be motivated to make this modification in order to invoke the appropriate error handler (McDonald: Col 4, lines 6-11).
Regarding Claim 2, LIU in view of McDonald teaches the system of claim 1, as referenced above, wherein the first device is further configured to determine, based on a preset correspondence, the index value (LIU: [0076]: two fault types: correctable error (CE) and uncorrectable error (UCE). [0072]: when fault occurs on first PCIe device, the first PCIe device sends a fault report message. The fault report message carries information such as a fault type and device ID. First PCIe device of PCIe device group 205 determines fault type value (index value) to create and send the fault report message), wherein the preset correspondence comprises a one-to-one correspondence between the fault cause and the index value (LIU: [0076]: by definition, CE and UCE are mutually exclusive. Thus, the value of the first PCIe device’s fault type is a 1:1 correspondence to {CE, UCE}), and wherein the processor is configured to determine, based on the preset correspondence, the fault cause (LIU: [0073]: BIOS may generate an NMI interrupt signal and send the NMI interrupt signal to a fault recovery module. The NMI interrupt signal carries the first hardware fault information. [0072]: first hardware fault information includes fault type of the first PCIe device. [0076]: two fault types: (1) CE, (2) UCE. Therefore, CPU 201 executing BIOS (see Claim 1) determines the fault cause (which is a 1:1 mapping to the possible fault types) to embed the fault type in the NMI signal).
Regarding Claim 4, LIU in view of McDonald teaches the system of claim 2, as referenced above, wherein the second transceiver is further configured to generate the notification signal based on the index value (LIU: [0072]: root complex 203 generates SMI interrupt signal to allow BIOS to read the first hardware fault information, including fault type value of the first PCIe device).
Regarding Claim 14, LIU discloses a method (Fig. 2; [0072]-[0073]) comprising:
receiving, by a second transceiver of a second device ([0072]: by root complex 203 of (root complex 203 + CPU 201)), fault information that is from a first device and that is generated by the first device ([0072]: root complex 203 receives fault report message from the first PCIe device [GPU 2052] of PCIe device group 205. First PCIe device sends a fault report message when a fault occurs on the first PCIe device. Sending encompasses generating the message before sending), wherein the fault information indicates a fault cause of a fault in a first transceiver of the first device ([0072]: fault report message carries information such as a fault type of the PCIe device and a device identifier of the PCIe device. [0076]: CE and UCE fault types. [0068]: sends fault packet to notify that a PCIe link (or a PCIe device) is faulty. Fault cause interpreted as fault type. Consistent with [0028] of Spec, where “fault cause includes at least one of single-bit fault in a memory, a multi-bit fault in the memory, and an internal bus transmission fault.” PCIe link of the first PCIe device is a first transceiver), and wherein the second transceiver receives the fault information comprising an index value corresponding to the fault cause and does not receive an interrupt signal indicating that the fault occurs ([0072]: see above. Specific value of fault cause written in the message interpreted as an index value. Sent to root complex 203 as a message, not as an NMI or SMI interrupt signal as described as generated by other components after message is sent);
storing, by the second transceiver, the fault information in a storage space of the second transceiver ([0072]: root complex 203 receives the fault reporting message and writes information such as the device identifier and fault type of the first PCIe device that are carried in the message into a register corresponding to the root complex);
sending, by the second transceiver, a notification signal to a processor of the second device ([0072]: root complex 203 generates and sends SMI interrupt signal to BIOS. Examiner takes Official Notice that it is inherent that a processor executes BIOS. Therefore, all data sent to/received by BIOS (e.g., SMI interrupt signal) is also sent to/received by the processor (e.g., CPU 201) executing BIOS);
receiving, by the processor, the notification signal ([0072]: BIOS receives SMI interrupt signal); and
LIU does not disclose:
reading, by the processor, the fault information.
However, McDonald teaches:
reading, by the processor, the fault information (Col 4, lines 6-11: the host processor may read an error register to determine the type of error that occurred, and then invoke an appropriate error handler).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU and McDonald by implementing the register read taught by McDonald. One of ordinary skill in the art would be motivated to make this modification in order to invoke the appropriate error handler (McDonald: Col 4, lines 6-11).
Regarding Claim 15, LIU in view of McDonald teaches the method of claim 14, as referenced above, further comprising determining, by the processor and based on a preset correspondence, the fault cause (LIU: [0073]: BIOS may generate an NMI interrupt signal and send the NMI interrupt signal to a fault recovery module. The NMI interrupt signal carries the first hardware fault information. [0072]: first hardware fault information includes fault type of the first PCIe device. [0076]: two fault types: (1) CE, (2) UCE. Therefore, CPU 201 executing BIOS (see Claim 14) determines the fault cause (which is a 1:1 mapping to the possible fault types) to embed the fault type in the NMI signal), and wherein the preset correspondence comprises a one-to-one correspondence between the fault cause and the index value (LIU: [0076]: by definition, CE and UCE are mutually exclusive. Thus, the value of the first PCIe device’s fault type is a 1:1 correspondence to {CE, UCE}).
Regarding Claim 16, LIU in view of McDonald teaches the method of claim 15, as referenced above, wherein the fault cause comprises an internal bus transmission fault (LIU: [0072]; [0076]: CE and UCE fault types. Uncorrectable error includes a fatal error, where the fatal fault usually needs an operation such as resetting, causing a data loss on a PCIe link).
Regarding Claim 17, LIU in view of McDonald teaches the method of claim 15, as referenced above, wherein before sending the notification signal, the method further comprises generating, by the second transceiver, the notification signal based on the index value (LIU: [0072]: root complex 203 generates SMI interrupt signal to allow BIOS to read the first hardware fault information, including fault type of the first PCIe device. Then sends the generated SMI interrupt signal to BIOS).
Regarding Claim 18, LIU in view of McDonald teaches the method of claim 15, as referenced above, wherein before sending the notification signal, the method further comprises generating, by the second transceiver, the notification signal based on an interrupt signal and the index value, and wherein the interrupt signal indicates the fault ([0072]: after receiving the fault report message from the first PCIe device, root complex 203 generates and reports the SMI interrupt signal to allow BIOS to read the first hardware fault information, including fault type of the first PCIe device. Before reporting/sending the SMI interrupt signal (“notification”), root complex 203 generates the SMI interrupt signal, which is an interrupt signal, used to read the fault type value (“index value”), and indicates a fault to perform fault detection on).
Regarding Claim 21, LIU in view of McDonald teaches the system of claim 1, as referenced above, wherein the second transceiver is further configured to store the index value in the storage space before sending the notification signal (LIU: [0072]: root complex 203 may write, into a register corresponding to the root complex, information such as the device identifier and the fault type of the first PCIe device that are carried in the message, and generate an SMI interrupt signal to indicate that a hardware fault occurs on a PCIe device communicating with the root complex 203).
Regarding Claim 22, LIU in view of McDonald teaches the system of claim 21, as referenced above, wherein the processor is further configured to determine the fault cause using the index value stored in the storage space (McDonald: Col 4, lines 6-11: the host processor may read an error register to determine the type of error that occurred, and then invoke an appropriate error handler. Value in error register interpreted as index value translated/determined by processor as a specific fault type/cause).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of McDonald, in further view of Laity et al. (US 20170351570 A1, hereinafter “Laity”).
Regarding Claim 3, LIU in view of McDonald teaches the system of claim 2, as referenced above.
LIU in view of McDonald does not teach:
wherein the fault cause comprises a single-bit fault in a memory.
However, However, Laity teaches:
wherein the fault cause comprises a single-bit fault in a memory ([0049]: The footer field 358-2 may encode information related to detection of data errors in data intended to be utilized in performance of the read operation… The error notification field 369 may be a one-bit field that, for example, may report detection of a data error… When a data error has been detected, the footer field 358-2 may report a type of data error in an error type (ERRTYPE) field 368. The type of data error, as described herein, may be reported from a selection of various types, such as a single-bit correctable error (SCE), a multi-bit correctable error (MCE), and/or a multi-bit uncorrectable error (MUE), among other possible types of error. [0055]: read request on memory array)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, and Laity by implementing the error type notification taught by Laity. One of ordinary skill in the art would be motivated to make this modification in order to specify the type and degree of correctable and uncorrectable errors for further context (Laity: [0049]).
Claim 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of McDonald, in further view of Pan et al. (US 20230345239 A1, hereinafter “Pan”)*, in further view of Du et al. (US 20150324268 A1, hereinafter “Du”).
*Please note that Pan is a continuation of PCT/CN2020/140012, filed Dec. 28, 2020 and is entitled to priority.
Regarding Claim 6, LIU in view of McDonald teaches the system of claim 1, as referenced above, wherein the storage space is a register (LIU: [0072]: register corresponding to the root complex), and wherein the processor is a processing chip (Fig. 2: CPU 201).
LIU in view of McDonald does not teach:
wherein the first device is a camera, wherein the second device is a mobile data center, wherein the first transceiver is a serializer, wherein the second transceiver is a deserializer
However, Pan teaches:
wherein the first device is a camera, wherein the second device is a mobile data center ([0106]: data transmission between vehicle-mounted devices in a vehicle. The data transmission may be wired through, for example a CAN bus, or may be wireless transmission. Data is transmitted between a first vehicle mounted device (e.g., camera) and a second vehicle mounted device (e.g., mobile data center))…
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, and Pan by implementing the data transmission between a camera and MDC as taught by Pan. One of ordinary skill in the art would be motivated to make this modification in order to determine driving decisions in autonomous driving (Pan: [0103]; [0106]).
LIU in view of McDonald, in further view of Pan does not teach:
…wherein the first transceiver is a serializer, wherein the second transceiver is a deserializer…
However, Du teaches:
wherein the first transceiver is a serializer, wherein the second transceiver is a deserializer (Fig. 3; [0040]-[0041]: PCIe link between PCIe apparatus 1 305 and root complex 303 contains 16 serdes (Serializer/Deserializer) circuits such that (PCIe apparatus 1 305 + PCIe link) includes a serializer, and (root complex 303 + PCIe link) includes a deserializer)…
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, Pan, and Du by implementing the serdes link taught by Du. One of ordinary skill would be motivated to make this modification to improve the bandwidth of the PCIe link (Du: [0004]) proportionally by the quantity of lanes of the link.
Regarding Claim 19, LIU in view of McDonald teaches the method of claim 14, as referenced above, wherein the storage space is a register (LIU: [0072]: register corresponding to the root complex), and wherein the processor is a processing chip (Fig. 2: CPU 201).
LIU in view of McDonald does not teach:
wherein the first device is a camera, wherein the second device is a mobile data center, wherein the first transceiver is a serializer, wherein the second transceiver is a deserializer
However, Pan teaches:
wherein the first device is a camera, wherein the second device is a mobile data center ([0106]: data transmission between vehicle-mounted devices in a vehicle. The data transmission may be wired through, for example a CAN bus, or may be wireless transmission. Data is transmitted between a first vehicle mounted device (e.g., camera) and a second vehicle mounted device (e.g., mobile data center))
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, and Pan by implementing the data transmission between a camera and MDC as taught by Pan. One of ordinary skill in the art would be motivated to make this modification in order to determine driving decisions in autonomous driving (Pan: [0103]; [0106]).
LIU in view of McDonald, in further view of Pan does not teach:
wherein the first transceiver is a serializer, wherein the second transceiver is a deserializer
However, Du teaches:
wherein the first transceiver is a serializer, wherein the second transceiver is a deserializer (Fig. 3; [0040]-[0041]: PCIe link between PCIe apparatus 1 305 and root complex 303 contains 16 serdes (Serializer/Deserializer) circuits such that (PCIe apparatus 1 305 + PCIe link) includes a serializer, and (root complex 303 + PCIe link) includes a deserializer)…
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, Pan, and Du by implementing the serdes link taught by Du. One of ordinary skill would be motivated to make this modification to improve the bandwidth of the PCIe link (Du: [0004]) proportionally by the quantity of lanes of the link.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of McDonald, in further view of LEE et al. (US 20220032904 A1, hereinafter “LEE”), in further view of Du.
Regarding Claim 7, LIU in view of McDonald teaches the system of claim 1, as referenced above, wherein the storage space is a register (LIU: [0072]: register corresponding to the root complex), and wherein the processor is a processing chip (Fig. 2: CPU 201).
LIU in view of McDonald does not teach:
wherein the first device is a display, wherein the second device is a cockpit controller, wherein the first transceiver is a deserializer, wherein the second transceiver is a serializer
However, LEE teaches:
wherein the first device is a display ([0192]; [0225]: navigation app of central information display (CID) SoC updates a screen based on information received from navigation assistant of ADAS SoC), wherein the second device is a cockpit controller ([0192]; [0225]: advanced driver assistant system (ADAS) SoC responsible for monitoring current speed and position along with calculating whether lane change is necessary)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, and LEE by implementing the data transmission between CID SoC and ADAS SoC taught by LEE. One of ordinary skill in the art would be motivated to make this modification in order to correct navigation information when network and GPS connections are disconnected due to driving through a tunnel (LEE: [0225]).
LIU in view of McDonald, in further view of LEE does not teach:
wherein the first transceiver is a deserializer, wherein the second transceiver is a serializer
However, Du teaches:
wherein the first transceiver is a deserializer, wherein the second transceiver is a serializer (Fig. 3; [0040]-[0041]: PCIe link between PCIe apparatus 1 305 and root complex 303 contains 16 serdes (Serializer/Deserializer) circuits such that (PCIe apparatus 1 305 + PCIe link) includes a deserializer, and (root complex 303 + PCIe link) includes a serializer)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, LEE, and Du by implementing the serdes link taught by Du. One of ordinary skill would be motivated to make this modification to improve the bandwidth of the PCIe link (Du: [0004]) proportionally by the quantity of lanes of the link.
Regarding Claim 20, LIU in view of McDonald teaches the method of claim 14, as referenced above, wherein the storage space is a register (LIU: [0072]: register corresponding to the root complex), and wherein the processor is a processing chip (Fig. 2: CPU 201).
LIU in view of McDonald does not teach:
wherein the first device is a display, wherein the second device is a cockpit controller, wherein the first transceiver is a deserializer, wherein the second transceiver is a serializer
However, LEE teaches:
wherein the first device is a display ([0192]; [0225]: navigation app of central information display (CID) SoC updates a screen based on information received from navigation assistant of ADAS SoC), wherein the second device is a cockpit controller ([0192]; [0225]: advanced driver assistant system (ADAS) SoC responsible for monitoring current speed and position along with calculating whether lane change is necessary)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, and LEE by implementing the data transmission between CID SoC and ADAS SoC taught by LEE. One of ordinary skill in the art would be motivated to make this modification in order to correct navigation information when network and GPS connections are disconnected due to driving through a tunnel (LEE: [0225]).
LIU in view of McDonald, in further view of LEE does not teach:
wherein the first transceiver is a deserializer, wherein the second transceiver is a serializer
However, Du teaches:
wherein the first transceiver is a deserializer, wherein the second transceiver is a serializer (Fig. 3; [0040]-[0041]: PCIe link between PCIe apparatus 1 305 and root complex 303 contains 16 serdes (Serializer/Deserializer) circuits such that (PCIe apparatus 1 305 + PCIe link) includes a deserializer, and (root complex 303 + PCIe link) includes a serializer)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, McDonald, LEE, and Du by implementing the serdes link taught by Du. One of ordinary skill would be motivated to make this modification to improve the bandwidth of the PCIe link (Du: [0004]) proportionally by the quantity of lanes of the link.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of Echevarria et al. (US 20110276843 A1, hereinafter “Echevarria”), in further view of Laity.
Regarding Claim 10, LIU discloses the method of claim 8, as referenced above.
LIU does not disclose:
further comprising sending, to the second device, the fault information when a priority of the fault cause is greater than a preset priority threshold, wherein the fault cause comprises a multi-bit fault in a memory.
However, Echevarria teaches:
further comprising sending, to the second device, the fault information when a priority of the fault cause is greater than a preset priority threshold ([0034]: notification module 312 may be configured to send a notification 206 to a system admin or other device when various conditions are satisfied. These conditions may include whether notification threshold is reached, whether the priority of an error or error group is sufficient to warrant sending a notification…),
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine implement the notification priority taught by Echevarria when transmitting the fault report message to root complex 203 (LIU: [0072]). One of ordinary skill in the art would be motivated to make this modification in order to prevent the receiving device from being overloaded with notifications (Echevarria: [0034]).
LIU in view of Echevarria does not teach:
wherein the fault cause comprises a multi-bit fault in a memory.
However, Laity teaches:
wherein the fault cause comprises a multi-bit fault in a memory ([0049]: The footer field 358-2 may encode information related to detection of data errors in data intended to be utilized in performance of the read operation… The error notification field 369 may be a one-bit field that, for example, may report detection of a data error… When a data error has been detected, the footer field 358-2 may report a type of data error in an error type (ERRTYPE) field 368. The type of data error, as described herein, may be reported from a selection of various types, such as a single-bit correctable error (SCE), a multi-bit correctable error (MCE), and/or a multi-bit uncorrectable error (MUE), among other possible types of error. [0055]: read request on memory array).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, Echevarria, and Laity by implementing the error type notification taught by Laity. One of ordinary skill in the art would be motivated to make this modification in order to specify the type and degree of correctable and uncorrectable errors for further context (Laity: [0049]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of Pan, in further view of Du.
Regarding Claim 12, LIU discloses the method of claim 8, as referenced above.
LIU does not disclose:
wherein the first device is a camera, wherein the first transceiver is a serializer, and wherein the second device is a mobile data center.
However, Pan teaches:
wherein the first device is a camera, and wherein the second device is a mobile data center ([0106]: data transmission between vehicle-mounted devices in a vehicle. The data transmission may be wired through, for example a CAN bus, or may be wireless transmission. Data is transmitted between a first vehicle mounted device (e.g., camera) and a second vehicle mounted device (e.g., mobile data center)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU and Pan by implementing the data transmission between a camera and MDC as taught by Pan. One of ordinary skill in the art would be motivated to make this modification in order to determine driving decisions in autonomous driving (Pan: [0103]; [0106]).
LIU in view of Pan does not teach:
wherein the first transceiver is a serializer
However, Du teaches:
wherein the first transceiver is a serializer (Fig. 3; [0040]-[0041]: PCIe link between PCIe apparatus 1 305 and root complex 303 contains 16 serdes (Serializer/Deserializer) circuits such that (PCIe apparatus 1 305 + PCIe link) includes a serializer)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, Pan, and Du by implementing the serdes link taught by Du. One of ordinary skill would be motivated to make this modification to improve the bandwidth of the PCIe link (Du: [0004]) proportionally by the quantity of lanes of the link.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over LIU in view of LEE, in further view of Du.
Regarding Claim 13, LIU discloses the method of claim 8, as referenced above.
LIU does not disclose:
wherein the first device is a display, wherein the first transceiver is a deserializer, and wherein the second device is a cockpit controller.
However, LEE teaches:
wherein the first device is a display ([0192]; [0225]: navigation app of central information display (CID) SoC updates a screen based on information received from navigation assistant of ADAS SoC)), and wherein the second device is a cockpit controller ([0192]; [0225]: advanced driver assistant system (ADAS) SoC responsible for monitoring current speed and position along with calculating whether lane change is necessary).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU and LEE by implementing the data transmission between CID SoC and ADAS SoC taught by LEE. One of ordinary skill in the art would be motivated to make this modification in order to correct navigation information when network and GPS connections are disconnected due to driving through a tunnel (LEE: [0225]).
LIU in view of LEE does not teach:
wherein the first transceiver is a deserializer
However, Du teaches:
wherein the first transceiver is a deserializer (Fig. 3; [0040]-[0041]: PCIe link between PCIe apparatus 1 305 and root complex 303 contains 16 serdes (Serializer/Deserializer) circuits such that (PCIe apparatus 1 305 + PCIe link) includes a deserializer)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine LIU, LEE, and Du by implementing the serdes link taught by Du. One of ordinary skill would be motivated to make this modification to improve the bandwidth of the PCIe link (Du: [0004]) proportionally by the quantity of lanes of the link.
Response to Arguments
Applicant’s arguments filed on 08/10/2026 regarding 35 U.S.C. 102/103 have been fully considered but they are not persuasive.
Applicant’s arguments, see Page 7, with respect to claim objections have been fully considered and are persuasive. The objection of Claim 16 has been withdrawn.
Applicant’s arguments, see Page 7, with respect to 35 U.S.C. 112(b) have been fully considered and are persuasive. The rejection of Claim 10 has been withdrawn.
Regarding 35 U.S.C. 102/103, Applicant argues:
“Liu, paragraph 72 (emphasis added). As shown above, Liu teaches that when a hardware fault occurs on a first PCIe device, the first PCIe device sends a fault report message carrying fault information such as a fault type and device identifier to a root complex. The Examiner further relies on Liu's disclosure that the fault report message serves as an interrupt signal that prompts the root complex to process the fault and generate an SMI interrupt signal. While Liu generates an interrupt signal in response to the fault, Liu does not send an index value corresponding to a fault cause without sending an interrupt signal. As such, Liu fails to disclose that when a fault occurs, the first device sends the index value corresponding to the fault cause and does not send an interrupt signal indicating that the fault occurs, as claimed. Thus, Liu fails to teach each and every element of independent claim 8, and consequently fails to anticipate claims 8-9.”
Examiner respectfully disagrees.
To clarify, LIU discloses indirectly sending an interrupt signal (SMI interrupt signal) to the second device (CPU 201 of root complex 203 + CPU 201) by prompting the root complex 203 to generate said signal via the fault report message ([0072]). The only hardware fault interrupt signals directly sent are SMI and NMI, which are sent by root complex 203 and BIOS, respectively, not by the first PCIe device GPU 2052. Further, LIU discloses the hardware fault interrupt signal as an NMI signal, a DPC interrupt signal, an MSI interrupt signal, another interrupt signal, and the like ([0070]). The fault report message is not the same as a message signaled interrupt (MSI), as an MSI is described to be sent in another example ([0074]) other than the example described in [0072]-[0073]. The message is also not another interrupt signal as the message/fault packet is described as a separate entity than the hardware fault interrupt signal generated in response to the packet in [0068]. Therefore, the 35 U.S.C. 102 rejections are maintained. Similar reasons apply towards arguments regarding 35 U.S.C. 103.
Conclusion
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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