DETAILED ACTION
This application is responsive to the following: the application and information disclosure statement January 23, 2024.
Claims 1-20 are pending. Claims 1 and 11 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
Claims 1-8, 10-16 and 18-19 refer to multiple different “control circuits,” such as “first,” “second,” “row,” “copy,” and “sense amplifier” control circuits. These circuits are disclosed as structural limitations in apparatus claims. However, no structure for these circuits are disclosed. They are described in the specification and in the drawings as “black boxes” in terms of how they function (i.e. processing some input(s) and outputting some output(s)) and not what their structures entail. Therefore, any circuits or combinations of circuits that can be said to perform the same functions is interpreted as the same as these “control circuits.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wentzlaff et al (US 11043259 B2).
Regarding Independent Claim 1, Wentzlaff teaches A processing-in-memory (PIM) device (Fig. 1: 10) comprising:
a memory cell array including a plurality of memory cells coupled to a plurality of word lines (fig. 1: 18) and a plurality of bit lines (fig. 1: 20);
a sense amplifier circuit (Fig. 1: 28) coupled to the plurality of bit lines (fig. 1: 20); and
a control circuit (Fig. 1: 34) configured to perform a row data copy operation that copies data of a first word line to a second word line, among the plurality of word lines (col 6 lines 42-44 “three basic in-memory operations are able to be performed: row copy (a copy of data from one row to another)”),
wherein the control circuit (Fig. 1: 34) is configured to sequentially perform operations according to an active control signal (Fig. 3: ACT(R1)), a row close control signal (Fig. 3: PRE), and a row open control signal 1 to perform the row data copy operation.
Regarding Claim 2, Wentzlaff teaches the limitations of Claim 1. Wentzlaff further teaches wherein the control circuit (Fig. 1: 34) is configured to activate the first word line and to enable the sense amplifier circuit, based on the active control signal, the data of the memory cells of the first word line being sensed and amplified in the sense amplifier circuit (Fig. 4: 1, 2; col 7 lines 14-19 “In step 1, the first ACTIVATE command is sent, which opens the row R.sub.1. Step 2 shows the result of the charge sharing, and the sense amplifier 28 starting to drive both the cell in R.sub.1 and the bit-line 38 to V.sub.dd. This step lasts for a while to allow R.sub.1 to recover the charge in its cell.”).
Regarding Claim 3, Wentzlaff teaches the limitations of Claim 2. Wentzlaff further teaches wherein, based on the row close control signal (fig. 3: PRE), the control circuit (Fig. 1: 34) is configured to control the first word line to be closed. (col 7 lines 19-25 “In step 3, the PRECHARGE command is executed, which will attempt to close row R.sub.1 and drive the bit-line 38 to V.sub.dd/2. The state of the column after a period of T.sub.2 from executing the PRECHARGE command is shown in step 4. At this point, the word-line 36 of R.sub.1 has been zeroed out to close R.sub.1, but the bit-line 38 did not have enough time to be fully discharged to V.sub.dd/2 yet, and the bit-line voltage level is way above the middle point.”)
Regarding Claim 4, Wentzlaff teaches the limitations of Claim 3. Wentzlaff further teaches wherein, based on the row open control signal (Fig. 3: ACT(R2)), the control circuit (Fig. 1: 34) is configured to control the second word line to be opened, the data sensed and amplified in the sense and amplifier circuit being stored in the memory cells of the second word line. (col 7 lines 25-37 “At the same time, the second ACTIVATE command is executed so as to interrupt the PRECHARGE process. The second ACTIVATE opens row R.sub.2 and the charge starts to flow from the bit-line 38 to the cells in R.sub.2. As the capacitance of the bit-line 38 is much larger than the capacitance of the cell, a relatively significant amount of charge is stored in the bit-line 38, and the bit-line voltage can still be larger than V.sub.dd/2 after the charge sharing, as shown in step 5. Thus, when the sense amplifier 28 is enabled to drive the bit-line 38, together with the cell in R.sub.2, it will reinforce their values to V.sub.dd. This successfully completes the copy of data from row R.sub.1 to row R.sub.2 in step 6.”)
Regarding Claim 5, Wentzlaff teaches the limitations of Claim 4. Wentzlaff further teaches wherein the control circuit (Fig. 1: 34) is configured to disable the sense amplifier circuit based on a precharge control signal. (col 5 lines 25-28 “The ACTIVATE command targets a specific row 18. Before an ACTIVATE is issued, a PRECHARGE command must be sent to the corresponding bank 16 to ensure the initial voltage on the bit-line is V.sub.dd/2. ”)
Regarding Claim 6, Wentzlaff teaches the limitations of Claim 1. Wentzlaff further teaches wherein the sense amplifier circuit (Fig 1: 28) includes a plurality of sense amplifiers respectively coupled to the plurality of bit lines (col 19 lines 8-12 “wherein each sub-array comprises a plurality of bit-lines configured to connect all cells in one bit of column to a sense amplifier of a local row buffer.”),
wherein the control circuit (Fig. 1: 34) includes:
a row control circuit (Fig. 1: 24) configured to, in response to the active control signal at a first logic level, transmit a first row control signal (Fig. 3: ACT(R1)) for activating the first word line designated by a first row address signal to the memory cell array; (Fig. 4: 1; col 7 lines 14-19 “In step 1, the first ACTIVATE command is sent, which opens the row R.sub.1. Step 2 shows the result of the charge sharing, and the sense amplifier 28 starting to drive both the cell in R.sub.1 and the bit-line 38 to V.sub.dd. This step lasts for a while to allow R.sub.1 to recover the charge in its cell.”) and
a sense amplifier control signal configured to, in response to the active control signal at the first logic level, transmit a switching-on signal for turning on the sense amplifiers to the sense amplifier circuit (Fig. 4: 1; col 7 lines 14-19 “In step 1, the first ACTIVATE command is sent, which opens the row R.sub.1. Step 2 shows the result of the charge sharing, and the sense amplifier 28 starting to drive both the cell in R.sub.1 and the bit-line 38 to V.sub.dd. This step lasts for a while to allow R.sub.1 to recover the charge in its cell.”), and
wherein the turned-on sense amplifiers are configured to sense and amplify data of the memory cells of the activated first word line (col 5 lines 38-40 “a sense amplifier 28 is enabled which drags the voltage to V.sub.dd or GND, thereby amplifying the value held in the bit-line 38.”).
Regarding Claim 7, Wentzlaff teaches the limitations of Claim 6. Wentzlaff further teaches wherein the row control circuit is configured to:
transmit a second row control signal (Fig. 3: PRE) for controlling the first word line to be closed to the memory cell array in response to the row close control signal at the first logic level, (col 7 lines 19-25 “In step 3, the PRECHARGE command is executed, which will attempt to close row R.sub.1 and drive the bit-line 38 to V.sub.dd/2. The state of the column after a period of T.sub.2 from executing the PRECHARGE command is shown in step 4. At this point, the word-line 36 of R.sub.1 has been zeroed out to close R.sub.1, but the bit-line 38 did not have enough time to be fully discharged to V.sub.dd/2 yet, and the bit-line voltage level is way above the middle point.”)
and
transmit a third row control signal (Fig. 3: ACT(R2) for controlling the second word line to be opened to the memory cell array in response to the row open control signal at the first logic level, the data sensed and amplified by the second amplifiers being stored in the memory cells of the second word line. (col 7 lines 25-37 “At the same time, the second ACTIVATE command is executed so as to interrupt the PRECHARGE process. The second ACTIVATE opens row R.sub.2 and the charge starts to flow from the bit-line 38 to the cells in R.sub.2. As the capacitance of the bit-line 38 is much larger than the capacitance of the cell, a relatively significant amount of charge is stored in the bit-line 38, and the bit-line voltage can still be larger than V.sub.dd/2 after the charge sharing, as shown in step 5. Thus, when the sense amplifier 28 is enabled to drive the bit-line 38, together with the cell in R.sub.2, it will reinforce their values to V.sub.dd. This successfully completes the copy of data from row R.sub.1 to row R.sub.2 in step 6.”)
Regarding Claim 8, Wentzlaff teaches the limitations of Claim 7. Wentzlaff further teaches wherein the sense amplifier control circuit is configured to transmit a switching-off signal for disabling the sense amplifier circuit to the sense amplifier circuit in response to the precharge control signal at the first logic level. (col 5 lines 25-28 “The ACTIVATE command targets a specific row 18. Before an ACTIVATE is issued, a PRECHARGE command must be sent to the corresponding bank 16 to ensure the initial voltage on the bit-line is V.sub.dd/2. ”)
Regarding Claim 9, Wentzlaff teaches the limitations of Claim 8. Wentzlaff further teaches comprising an operating circuit (Fig. 1: 46) configured to receive data of the memory cell array to perform operations,
wherein the operating circuit is configured to receive the data sensed and amplified by the second amplifiers between a time point at which the first word line is closed and a time point at which the second word line is opened and configured to perform the operations using the received data (col 5 lines 47-49 “the corresponding columns of data in the global row buffer 42 are read out to or written from the I/O pins 46.”).
Regarding Claim 10, , Wentzlaff teaches the limitations of Claim 8. Wentzlaff further teaches wherein the operating circuit (Fig. 1: 46) is configured to transmit operation result data generated as a result of performing the operations to the sense amplifiers, and
wherein the row control circuit is configured to, in response to the row open control signal at the first logic level to the memory cell array, transmit a third row control signal for controlling a third word line designated by a third row address signal to be opened, the operation result data transmitted to the sense amplifiers being stored in memory cells of the third word line. (col 7 lines 19-25 “In step 3, the PRECHARGE command is executed, which will attempt to close row R.sub.1 and drive the bit-line 38 to V.sub.dd/2. The state of the column after a period of T.sub.2 from executing the PRECHARGE command is shown in step 4. At this point, the word-line 36 of R.sub.1 has been zeroed out to close R.sub.1, but the bit-line 38 did not have enough time to be fully discharged to V.sub.dd/2 yet, and the bit-line voltage level is way above the middle point.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wentzlaff et al (US 11043259 B2) in view of Skadron et al (US 20230072191 A1).
Regarding Independent Claim 11, Wentzlaff teaches a processing-in-memory (PIM) device (Fig. 1: 10) comprising:
sub memory cell arrays (Fig. 1: 26), each including a plurality of memory cells coupled to a plurality of word lines (fig. 1: 18) and a plurality of bit lines (fig. 1: 20), the sub memory cell arrays including a first sub memory cell array (Fig. 1: 26; upper) including a plurality of first memory cells coupled to a plurality of first word lines (fig. 1: 18) and a plurality of first bit lines (fig. 1: 20) and a plurality of second sub memory cell array (Fig. 1: 26; lower) including a plurality of second memory cells coupled to a plurality of second word lines (fig. 1: 18) and a plurality of second bit lines (fig. 1: 20);
a first sense amplifier circuit (Fig. 1: 28) coupled to the plurality of first bit lines (fig. 1: 20) of the first sub memory cell array (Fig. 1: 26; upper);
a second sense amplifier circuit (Fig. 1: 28) coupled to the plurality of second bit lines (fig. 1: 20) of the second sub memory cell array (Fig. 1: 26; lower);
a control circuit (Fig. 1: 34) configured to control a row data copy operation between the sub memory cell arrays by copying data of the first memory cells of a source word line, which is one of the plurality of first word lines, to the second memory cells of a target word line, which is one of the plurality of second word lines,
wherein the control circuit (Fig. 1: 34) is configured to sequentially perform operations between the sub memory cell arrays according to a first active control signal (Fig. 3: ACT(R1)), the first row close control signal (Fig. 3: PRE), the second row open control signal (Fig. 3: ACT(R2)),
However, Wentzlaff fails to teach a copy circuit configured to, based on a copy control signal, control an electrical connection of the plurality of first bit lines and the plurality of second bit lines; and
a copy control circuit configured to generate the copy control signal based on a first row open control signal, a first row close control signal, a second row open control signal, and a second row close control and configured to transmit the copy control signal to the copy circuit;
Skadron teaches a copy circuit (Fig 9: ISO-0) configured to, based on a copy control signal, control an electrical connection of the plurality of first bit lines and the plurality of second bit lines; and
a copy control circuit (para 12 “a control circuit configured to store respective reference sequences”)
Wentzlaff explicitly raises the motivation of row copy between sub arrays stating (col 12 lines 5-17) “As computation progresses and the variable space grows, it may be required to move data across bank sub-arrays 26. However, this cannot be achieved using the in-memory row copy operation, as rows 18 in different sub-arrays 26 do not share the same bit-lines 38. In such cases, it is disclosed to read the whole row 18 from the source sub-array 26, store the data in the MC 34, and then write it into the destination sub-array 26. Although the MC 34 would require multiple READ/WRITE commands to go through the columns 20 of the entire row 18, this approach is preferable to the alternative of moving the data between the memory 10 and processor 32, as it reduces the distance that data has to travel.” Explicitly pointing out a motivation to copy between subarrays, but citing the limitation of separate bit lines in the subarrays. The Isolation transistors taught by Skadron overcome this limitation by allowing the bit lines of Sub arrays to be electrically connected for the purposes of copy row data from one sub array to another.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Skadron to the teachings of Wentzlaff to produce a subarrays with separate bit lines that can become electrically connected by a copy circuit when performing a row copy operation.
Regarding Claim 20, Wentzlaff and Skadron teach the limitations of claim 11. Wentzlaff further teaches a first operating circuit (Fig. 1: 26, 30; upper) configured to receive data of the first sub memory cell array (Fig. 1: 26; upper) to perform a first operation; and
a second operating circuit (Fig. 1: 26, 30; upper) configured to receive data of the second sub memory cell array (Fig. 1: 26; lower) to perform a second operation.
Allowable Subject Matter
Claims 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 12 is allowable for requiring the limitation that the control circuits would apply the sequence of signals necessary to perform the row copy operation. While a similar operation performed in a single subarray is suggest, Wentzlaff is silent with respect to the operational steps required to perform a row copy operation across sub arrays. Skadron teaches a similar method of operation in figure 9, but that method of operation is transferring data form one set of SA to another through the isolation circuits in order to eventually reach a compute buffer. It does not describe a method copying data from one row of a sub array to the row of another sub array. Therefore, this claim would be allowable if written in independent form.
Claims 13-19 are allowable for be dependent on Claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
Prosecution Insights