Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the communication filed on 12/29/2025.
Claims 1-20 are examined and rejected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 12/29/2025 has been entered.
Response to Arguments
As per Applicant’s argument dated 12/29/2025 are considered.
Applicant argues that Di Cosmo does not teach two secure circuits complying with different telecommunication network certification authorities.
Examiner acknowledges the argument and submits the response below.
Examiner’s response as following: –
Examiner does not find argument persuasive, as combination of references teaches the following limitation(s) as described below –
Hsiao Fig 1 and 2 element 112 and 102 and element 11 para 24-26 teaches where trusted zone unit controller set unit 11 are different security protocols where one is based on main and digital key and other is based on role-based access. Further Hsiao Fig 1 and 2 further para 34 teaches signature verification such as AES encryption module and first (multiple channel modules.
Examiner interprets signature verification same as getting functions complied with network certification authorities of claim limitation in broad view of claim limitations.
Further in broad view of claim limitation, examiner interprets ‘compliance with telecom network certification authorities as authentication / verification of device which is well known in art. As claim(s) lack distinct definition of what does ‘compliance with telecom network certification authorities’ mean, is it external authorities, is it internal or network-based authorities, is it each circuit complies with multiple authorities or one authority ?. Examiner requests that distinct recitation of claim functions will assist examiner in conducting focused search.
Examiner concludes that Hsiao (and combination of references) teaches argued limitation as described above.
Examiner is open for phone call interview to discuss further with applicant’s representative for the purpose of compact prosecution.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable by U.S. Publication 2022/0353062 to Hsiao et al. (hereinafter known as “Hsiao”) and in view of U.S. Publication 2020/0137034 to Di Cosmo et al. (hereinafter known as “Di Cosmo”).
As per claim 1 Hsiao teaches, an integrated circuit comprising: at least two secure circuits having similar functions but complying with different telecommunication network certification authorities (Hsiao Fig 1 and 2 element 112 and 102 and element 11 para 24-26 teaches where trusted zone unit controller set unit 11 are different security protocols where one is based on main and digital key and other is based on role-based access. Further Hsiao Fig 1 and 2 further para 34 teaches signature verification such as AES encryption module and first (multiple channel modules. Examiner interprets signature verification same as getting functions complied with network certification authorities of claim limitation in broad view of claim limitations).
Hsiao does not teach, Di Cosmo teaches,
a hardware selector comprising:
a control terminal coupled to a terminal of the integrated circuit (Di Cosmo Fig 1 para 19-22 where element 12 application processor is interpreted as control terminal as it control what application is processed as per profile and accessibility);
at least two inputs, each input coupled to a respective one of the at least two secure circuits; and
an output coupled to other circuits of the integrated circuit (Di Cosmo Fig 1 and 2 – para 19, 22-26 teaches Secure element – eSE device and eUICC, which is tamper resistant device or platform. Additionally, the Secure element is a different device with respect to the eUICC in that it is managed directly by the OEM (Original Equipment Manufacturer). With reference to the layer diagram of FIG. 2 showing ISO layers for both the embedded Secure Element 14 and the eUICC 15, at the hardware layer HL is implemented usually through the same hardware device 11 or similar hardware devices, for instance the ST33G1M2 secure microcontroller. In variant embodiments for the embedded Secure Element 14 the hardware protocol used may be I2C or SPI and ISO T=0 or ISO T=1 are simulated over I2C/SPI).
Hsiao- Di Cosmo are analogous as they are in security of integrated circuit modules. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hsiao- Di Cosmo before him or her, to combine, Hsiao teaching of integrated circuit with secure unit and cryptographic module with digital key service and trusted zone unit (Hsiao’s abstract) with Di Cosmo’s teaching of multiple security domain’s in tamper resistant integrated circuit card (Di Cosmo abstract). The suggestion/motivation for doing so would have been to enhance security in IC card with tamper resistant module with multiple security domains (Di Cosmo para 2).
As per claim 2 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, wherein each secure circuit is dedicated to a respective certification authority (Hsiao Fig 1 and 2 element 112 and 1001, para 23-24 teaches IC module security based on signature verification which is interpreted to cover certification authority).
As per claim 3 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, wherein each secure circuit is configured according to a geographical area (Hsiao Fig 1 teaches architecture for Information security IC module para 23-26 teaches architecture of IC module with security circuit unit and trusted zone unit with additional features in distinct location).
As per claim 4 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, further comprising:
a selector having a control terminal coupled to a terminal of the integrated circuit (Hsiao Fig 1 and 2 element 1 and 29 para 23-26 teaches secure circuit unit interpreted as integrated circuit); and
one or more communication buses accessible to the at least two secure circuits via the selector (Hsiao Fig 1 element 101 teaches para 23-26 teaches where the communication channel via secure signal channel covers the claimed limitation).
As per claim 5 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, further comprising wherein the other circuits are shared between the at least two secure circuits (Hsiao Fig 1 element 101 secure signal channel or interface element 1110 para 24-27 teaches secure signal channel to establish functional security public-private key pair in trusted zone unit and secure circuit unit which covers claimed limitation).
As per claim 6 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, further comprising communication and input/output circuits accessible to the at least two secure circuits (Hsiao Fig 1 element 101 secure signal channel, para 24-27 teaches secure circuit in secure communication with trusted zone unit and digital key pairs).
As per claim 7 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, further comprising one or more power management units accessible to the at least two secure circuits (Hsiao para 25 teaches power management with controller set unit element 11 for functions for secure IC circuit).
As per claim 9 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, wherein the integrated circuit is configured to select one of the at least two secure circuits in accordance with a software control originating from an outside of the integrated circuit (Hsiao Fig 1 and 2 where two circuits and circuit 102 updates key information from element 112, para 23-27 teaches where the controller unit in accordance with fast service updates secure policies and key information from secure circuit to via secure channel for updating of policies and raw / private key updates).
As per claim 10 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1, wherein each secure circuit comprises: at least one secure circuit communication bus;
at least one non-volatile memory coupled to the at least one secure circuit communication bus (Hsiao para 23-27 and 34 teaches PCI-Ebus and HSM hardware security module which includes secure communication bus);
at least one volatile memory coupled to the at least one secure circuit communication bus (Hsiao Fig 1 element 10 – secure circuit unit para 22-26 teaches secure channel within two units secure unit and encryption unit with secure bus channel which covers claimed limitation) ;
at least one peripheral circuit, dedicated to features required by a respective certification authority, coupled to the at least one secure circuit communication bus (Hsiao Fig 1 and 2 element 112 and 1001, para 23-24 teaches IC module security based on signature verification which is interpreted to cover certification authority); and
a microprocessor communicatively coupled, via the at least one secure circuit communication bus, to the at least one non-volatile memory, the at least one volatile memory, and the at least one peripheral circuit (Hsiao Fig 3A-3C para 23-27 and 29-30 teaches micro card and other hardware elements with brief descriptions of each HW unit which covers the claimed limitation).
Claim 11,
Claim 11 is rejected in accordance with claim 1.
Claim 12,
Claim 12 is rejected in accordance with claim 2.
Claim 13,
Claim 13 is rejected in accordance with claim 3.
Claim 14,
Claim 14 is rejected in accordance with claim 4.
Claim 15,
Claim 15 is rejected in accordance with claim 5.
Claim 16,
Claim 16 is rejected in accordance with claim 6.
Claim 17,
Claim 17 is rejected in accordance with claim 7.
Claim 19,
Claim 19 is rejected in accordance with claim 9.
Claim 20,
Claim 20 is rejected in accordance with claim 10.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable by U.S. Publication 2022/0353062 to Hsiao et al. (hereinafter known as “Hsiao”) and in view of U.S. Publication 2020/0137034 to Di Cosmo et al. (hereinafter known as “Di Cosmo”) and further in view of U.S. Publication 2019/0174449 to Shan et al. (hereinafter known as “Shan”).
As per claim 8 Combination of Hsiao – Di Cosmo teaches, the integrated circuit according to claim 1.
Hsiao-Di Cosmo does not teach however Shan teaches, further comprising one or more clock generation circuits accessible to the at least two secure circuits (Shan – para 149 teaches real time clock with time counters within secure digital circuit).
Hsiao- Di Cosmo-Shan are analogous as they are in security of integrated circuit modules. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hsiao- Di Cosmo -Shan before him or her, to combine, Hsiao- Di Cosmo’s teaching of integrated circuit with secure unit and cryptographic module with digital key service and trusted zone unit (Hsiao’s abstract) with Shan’s teaching of access and mobility management function with secure unit and clock generation circuit (Shan’s abstract and para 149). The suggestion/motivation for doing so would have been to enhance security and receive authorized services to user equipment with periodic analysis of system (Shan para 3).
Claim 18,
Claim 18 is rejected in accordance with claim 8.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Van et al US Patent 11768968
Benson et al US Patent 10878113
Van et al US Patent 10157281
Chastain et al US Patent 8898769
Conclusion
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/VIRAL S LAKHIA/Primary Examiner, Art Unit 2431