DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 8, 10-18, and 22-25 are pending for examination.
This Office Action is FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 10-17, 22, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PRAGASH et al. (WO 2005072052 A2, as cited in the IDS, hereinafter “PRAGASH”).
Regarding Claim 1, PRAGASH discloses A dual timing circuit configured to reset a processor upon detecting a fault (Fig. 1: watchdog system 100 contains a first boot timer ([0024]: delay component 130) and a second operational timer ([0027]: monitor 180), both of which are configured to trigger a reset of the monitored processor upon detecting a boot initialization fault or periodicity fault, respectively), the dual timing circuit comprising:
a start-up circuit, configured with a first timeout duration, wherein the start-up circuit is operative to assert a reset signal in response to failing to receive a strobe signal from the processor within the first timeout duration after powering on (Fig. 1 and [0024]: delay component 130 provides a specified delay (“boot up period”) for the processor and triggers a reset of the processor after failing to receive an acknowledgement signal from the processor during the boot up period. [0026]: save & reset logic 160 actuates a reset signal to reset the processor. Fig. 2 and [0028]: boot up period refers to boot state 210, in which watchdog system 100 is in the boot state 210 on power up. Therefore, a start-up circuit (control logic 120 + delay component 130 + save & reset logic 160) is configured with a boot up period timeout duration and asserts a reset signal in response to failing to receive an acknowledgement signal (“strobe signal”) from the processor within the boot load period on power up. The strobe signal interpretation is consistent with [0050] of the instant spec: “Processor 110 is configured to send a strobe signal 120 (or keep-alive signal)…”); and
an operations circuit, configured with a second timeout duration, wherein the operations circuit is operative to assert the reset signal in response to failing to receive the strobe signal from the processor within the second timeout duration (Fig. 1 and [0027]-[0028]: monitor 180 supervises the periodicity and order of acknowledgement pulses according to a stored supervision policy. Monitor 180 instructs save & reset logic 160 to reset the processor if all N acknowledgement signals are not received before expiration of the cycle period. [0036]: acknowledgement signals are received from the processor. Therefore, an operations circuit (control logic 120 + monitor 180 + save & reset logic 160) is configured with a cycle period and asserts a reset signal in response to failing to receive all N acknowledgement signals from the processor within the cycle period);
wherein the strobe signal is configured to be operatively provided to both the start-up circuit and the operations circuit (Fig. 1; [0024]; [0029]: acknowledgement signal (e.g., Ack1) configured to be sent to delay component 130 of control logic 120 - delay component 130 - save & reset logic 160 circuit (start-up circuit, see above). Fig. 1; [0027]; [0031]: acknowledgement signals (e.g., including another Ack1) configured to be sent to monitor 180 of control logic 120 – monitor 180 – save & reset logic 160 circuit (operations circuit, see above)) and wherein receiving the strobe signal indicates that the processor is operating normally and not receiving the strobe signal indicates that the processor is not properly functioning ([0024]; [0029]-[0030]: upon receiving an acknowledgement signal 310 during boot up period, normal operational state cycle 230 begins. Not receiving an acknowledgement signal during the boot up period indicates the processor failed to properly initialize. [0031]-[0033]: at the expiration of the forbidden period, another first acknowledgement signal 320 (Ack 1) is expected. Failure to receive the signal before the expiration of the cycle period T and in a specific order triggers a reset of the processor (processor ack transmissions are not functioning properly));
wherein the strobe signal is initiated after the dual timing circuit is fully configured (Fig. 2; [0028]-[0029]: send ack1 to interpreted boot circuit (see above) during boot state 210 and boot period tb begins. Fig. 2; [0028]; [0031]-[0033]: send another ack1 to interpreted operations circuit (see above) during operational state 230, when cycle period T begins, and after forbidden period t0 expires without receiving an acknowledgement signal); and
wherein each of the start-up circuit and the operations circuit are external to the processor (Fig. 1 and [0021]: watchdog system 100 is coupled to one or more processors (not shown) through processor interface 110. All components of watchdog system 100 (including the interpreted start-up circuit and operations circuit described above) are therefore external to the one or more processors).
Regarding Claim 4, PRAGASH discloses the dual timing circuit of claim 1, as referenced above, wherein the dual timing circuit is further configured to assert a single second reset signal to the processor in response to either the start-up circuit or the operations circuit asserting the reset signal (Fig. 1 and [0024]: delay component 130 triggers a reset of the processor. [0026]: save & reset logic 160 is the component that actuates a reset signal 164 to the processor. Therefore, delay component 130 asserts a reset “signal” to save & reset logic 160, which then asserts reset signal 164 to the processor).
Regarding Claim 5, PRAGASH discloses the dual timing circuit of claim 1, as referenced above, further comprising:
a first memory element configured to store a reset indicator signal indicating a source of the reset signal asserted by the start-up circuit ([0026]: save & reset logic 160 additionally asserts to the processor a save signal 168 that stores information to identify data surrounding the cause/source for reset. Interrupt Service Routine (ISR) stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168). [0024] and [0028]: delay component 130 uses save & reset logic 160 to send a reset signal to the processor. Therefore, ISR stores save signal 168 (understood by one of ordinary skill in the art to be stored in a memory element) that indicates a source of the reset signal, in which the reset signal was asserted by delay component 130); and
a second memory element configured to store the reset indicator signal indicating the source of the reset signal asserted by the operations circuit ([0027]: similar reasoning above except with monitor 180 instead of delay component 130 -- monitor 180 also uses save & reset logic 160 to reset the processor, which contains a save signal 168 storing a source of the reset signal, wherein the reset signal was asserted by monitor 180. Save signal 168 is stored by ISR, wherein the storage location is understood by one of ordinary skill in the art to be a memory element).
Regarding Claim 6, PRAGASH discloses the dual timing circuit of claim 1, as referenced above, wherein the processor is configured to disable the start-up circuit after a boot load is completed by the processor and the operations circuit is configured correctly (Fig. 2 and [0028]: if an acknowledgement signal is received during the boot up period ([0024]: by the processor), the watchdog system 100 moves to the operational state 230 immediately. Since watchdog system 100 operates as a state machine, the transition to operation state 230 effectively disables the boot state and boot state related components ([0024], [0026]: control logic 120, delay component 130, and save & reset logic 160, interpreted as the start-up circuit) and the control logic 120, monitor 180, and save & reset logic 160 is configured correctly through the immediate transition (see [0030]-[0031] – operational state 230 starts with various period durations upon receiving the same acknowledgement signal 310 within the boot state. [0025]: periods are predetermined and unable to be modified, thus the interpreted operations circuit is configured correctly prior to the immediate transition).
Regarding Claim 10, PRAGASH discloses a method for resetting a processor upon detecting a fault (Fig. 1), the method comprising:
asserting, by a start-up circuit that is external to the processor and configured with a first timeout duration, a reset signal in response to failing to receive a strobe signal from the processor within the first timeout duration (Fig. 1 and [0024]: delay component 130 provides a specified delay (“boot up period”) for the processor and triggers a reset of the processor failing to receive an acknowledgement signal from the processor during the boot up period. [0026]: save & reset logic 160 actuates a reset signal to reset the processor. Therefore, a start-up circuit (control logic 120 + delay component 130 + save & reset logic 160) is configured with a boot up period timeout duration and asserts a reset signal in response to failing to receive an acknowledgement signal (“strobe signal”) from the processor within the boot up period. The strobe signal interpretation is consistent with [0050] of the instant spec: “Processor 110 is configured to send a strobe signal 120 (or keep-alive signal)…” Fig. 1 and [0021]: watchdog system 100 is coupled to one or more processors (not shown) through processor interface 110. Therefore, all components of watchdog system 100 (including the interpreted start-up circuit) are external to the one or more processors); and
asserting, by an operations circuit that is external to the processor and configured with a second timeout duration, the reset signal in response to failing to receive the strobe signal from the processor within the second timeout duration (Fig. 1 and [0027]-[0028]: monitor 180 supervises the periodicity and order of acknowledgement pulses according to a stored supervision policy. Monitor 180 instructs save & reset logic 160 to reset the processor if all N acknowledgement signals are not received before expiration of the cycle period. [0036]: acknowledgement signals are received from the processor. Therefore, an operations circuit (control logic 120 + monitor 180 + save & reset logic 160) is configured with a cycle period and asserts a reset signal in response to failing to receive all N acknowledgement signals from the processor within the cycle period. Fig. 1 and [0021]: watchdog system 100 is coupled to one or more processors (not shown) through processor interface 110. Therefore, all components of watchdog system 100 (including the interpreted operations circuit) are external to the one or more processors), said strobe signal is operatively provided to both the start-up circuit and the operations circuit (Fig. 1; [0024]; [0029]: acknowledgement signal (e.g., Ack1) configured to be sent to delay component 130 of control logic 120 - delay component 130 - save & reset logic 160 circuit (start-up circuit, see above). Fig. 1; [0027]; [0031]: acknowledgement signals (e.g., including another Ack1) configured to be sent to monitor 180 of control logic 120 – monitor 180 – save & reset logic 160 circuit (operations circuit, see above)), wherein receiving the strobe signal indicates that the processor is operating normally and not receiving the strobe signal indicates that the processor is not properly functioning ([0024]; [0029]-[0030]: upon receiving an acknowledgement signal 310 during boot up period, normal operational state cycle 230 begins. Not receiving an acknowledgement signal during the boot up period indicates the processor failed to properly initialize. [0031]-[0033]: at the expiration of the forbidden period, another first acknowledgement signal 320 (Ack 1) is expected. Failure to receive the signal before the expiration of the cycle period T and in a specific order triggers a reset of the processor (processor ack transmissions are not functioning properly)), and wherein the strobe signal is initiated after a dual timing circuit that includes the stat-up circuit and the operations circuit is fully configured (Fig. 2; [0028]-[0029]: send ack1 to interpreted boot circuit (see above) during boot state 210 and boot period tb begins. Fig. 2; [0028]; [0031]-[0033]: send another ack1 to interpreted operations circuit (see above) during operational state 230, when cycle period T begins, and after forbidden period t0 expires without receiving an acknowledgement signal).
Regarding Claim 11, PRAGASH discloses the method of claim 10, as referenced above, further comprising disabling the start-up circuit in response to a boot load by the processor completing within the first timeout duration (Fig. 2 and [0028]: if an acknowledgement signal is received during the boot up period, the watchdog system 100 moves to the operational state 230 immediately. Since watchdog system 100 operates as a state machine, the transition to operation state 230 effectively disables the boot state and boot state related components ([0024], [0026]: control logic 120, delay component 130, and save & reset logic 160 as the start-up circuit) in response to the boot by the processor completing within the boot up period ([0030])).
Regarding Claim 12, PRAGASH discloses the method of claim 10, as referenced above, further comprising enabling the operations circuit in response to a boot load by the processor completing within the first timeout duration ([0028]: if an acknowledgement signal is received during the boot up period ([0024]: which indicates the processor successfully initializing during boot load), watchdog system 100 moves to operational state 230 immediately. Operational state 230 uses control logic 120, monitor 180, and save & reset logic 160 (see [0027], [0031]-[0033]). Therefore, the transition to operational state 230 encompasses enabling the interpreted operations circuit in response to the processor completing the boot load initialization within the boot up period).
Regarding Claim 13, PRAGASH discloses the method of claim 10, as referenced above, further comprising configuring the operations circuit in response to the boot load by the processor completing ([0028]: if an acknowledgement signal is received during the boot up period ([0024]: which indicates the processor successfully initializing during boot load), watchdog system 100 moves to operational state 230 immediately. Operational state 230 uses control logic 120, monitor 180, and save & reset logic 160 (see [0027], [0031]-[0033]). Therefore, the transition to operational state 230 encompasses configuring the interpreted operations circuit in response to the processor completing the boot load initialization within the boot up period).
Regarding Claim 14, PRAGASH discloses the method of claim 10, as referenced above, further comprising, in response to failing to receive the strobe signal from the processor within the second timeout duration, writing a reset indicator signal indicating a source of the reset signal asserted by the operations circuit to a second memory element ([0027]: if all N acknowledgement signals are not received ([0036]: from the processor) before the expiration of the cycle period, monitor 180 instructs the save & reset logic 160 to reset the processor. [0026]: before sending reset signal 164, save & reset logic 160 asserts (writes) a save signal 168 indicating the cause for reset to the processor and ISR. ISR stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168 triggered by monitor 180). Therefore, in response to failing to receive all N signals from the processor within the cycle period, save signal 168 indicating a cause of the reset signal asserted by monitor 180 is stored by the ISR. One of ordinary skill in the art would understand that the storage location is a memory element).
Regarding Claim 15, PRAGASH discloses The method of claim 10, as referenced above, further comprising, in response to failing to complete a boot load by the processor within the first timeout duration, writing a reset indicator signal indicating a source of the reset signal asserted by the start-up circuit ([0024]: if the processor fails to initialize during the boot up period, delay component 130 triggers a reset of the processor. [0026]: before sending reset signal 164, save & reset logic 160 asserts (writes) a save signal 168 indicating the cause for reset to the processor and ISR. ISR stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168 triggered by monitor 180). Therefore, in response to failing to complete the boot initialization by the processor within the boot up period, save signal 168 indicating a cause of the reset signal asserted by delay component 130 is stored by the ISR).
Regarding Claim 16, PRAGASH discloses the method of claim 10, as referenced above, further comprising:
storing, by a first memory element, an indication of a reset signal asserted by the start-up circuit ([0026]: save & reset logic 160 additionally asserts to the processor a save signal 168 that stores information to identify data surrounding the cause/source for reset. Interrupt Service Routine (ISR) stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168). [0024] and [0028]: delay component 130 uses save & reset logic 160 to send a reset signal to the processor. Therefore, ISR stores save signal 168 (understood by one of ordinary skill in the art to be stored in a memory element) that indicates a source of the reset signal, in which the reset signal was asserted by delay component 130);
and storing, by a second memory element, an indication of a reset signal asserted by the operations circuit ([0027]: similar reasoning above except with monitor 180 instead of delay component 130 -- monitor 180 also uses save & reset logic 160 to reset the processor, which contains a save signal 168 storing a source of the reset signal, wherein the reset signal was asserted by monitor 180. Save signal 168 is stored by ISR, wherein the storage location is understood by one of ordinary skill in the art to be a memory element).
Regarding Claim 17, PRAGASH discloses the method of claim 10, as referenced above, further comprising asserting a single reset signal to the processor in response to either the start-up circuit or the operations circuit asserting reset ([0024]: delay component 130 triggers a reset of the processor. [0026]: save & reset logic 160 is the component that actuates a reset signal to reset the processor. A single reset signal 164 is then asserted to the processor in response to delay component 130 invoking reset to save & reset logic 160).
Regarding Claim 22, PRAGASH discloses the dual timing circuit of claim 1, as referenced above, wherein the dual timing circuit is connected to the processor by the strobe signal (Fig. 1; [0021]: processor generates acknowledgement signals and sends the signals to watchdog system 100 over IO lines 115A-N) and by a serial interface (Fig. 1, [0021]: watchdog system 100 connected to one or more processors (not shown) via a number “N” of unique IO lines 115A-N. Connected to serial interface when N = 1).
Regarding Claim 25, PRAGASH discloses the method of claim 10, as referenced above, further comprising connecting the processor to the dual timing circuit with both the strobe signal (Fig. 1; [0021]: processor generates acknowledgement signals and sends the signals to watchdog system 100 over IO lines 115A-N) and with a serial interface (Fig. 1, [0021]: watchdog system 100 connected to one or more processors (not shown) via a number “N” of unique IO lines 115A-N. Connected to serial interface when N = 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over PRAGASH in view of Majewski et al. (US 20080276132 A1, hereinafter “Majewski”).
Regarding Claim 2, PRAGASH discloses the dual timing circuit of claim 1, as referenced above.
PRAGASH does not disclose:
wherein the start-up circuit is hardware controlled
However, Majewski teaches:
wherein the start-up circuit is hardware controlled (Fig. 1 and [0045]: internal watchdog timer may have a hardware enable input configurated to enable the internal watchdog timer during the operating system startup sequence).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH and Majewski by implementing the hardware enable input taught by Majewski to another start-up circuit such as delay component 130 as taught by PRAGASH. One of ordinary skill in the art would be motivated to make this modification in order to provide a means of enabling the timer (Majewski: [0045]).
Regarding Claim 3, PRAGASH discloses the dual timing circuit of claim 1, as referenced above.
PRAGASH does not disclose:
wherein the operations circuit is software controlled.
However, Majewski teaches:
wherein the operations circuit is software controlled (Fig. 1 and [0009]: external watchdog timer (WDT) 16 is initiated after the OS is fully launched and running. External WDT is interpreted as an operations circuit as it monitors and resets the processor if the OS faults and fails to toggle the external WDT’s strobe input (see [0048]). [0027]: external WDT 16 may be enabled by BIOS, other locally stored program of processor 12, or the COTS OS itself).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH and Majewski by performing a simple substitution of one known element (PRAGASH: control logic 120 + monitor 180 + save & reset logic 160) for another (Majewski: external WDT 16) to obtain predictable results (a watchdog timer configured to monitor the processor during operations/after a startup).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over PRAGASH in view of Texas Instruments (NPL: “Monitor System with External Programmable Watchdog Timer with Low-Cost MSP430 MCU”).
Regarding Claim 8, PRAGASH discloses the dual timing circuit of claim 1, as referenced above.
PRAGASH does not disclose:
further comprising a serial interface, wherein the second timeout duration is configured to be set via the serial interface.
However, Texas Instruments teaches:
further comprising a serial interface (Page 1, left column, last paragraph: uses a UART interface, which is known in the art to be a serial interface), wherein the second timeout duration is configured to be set via the serial interface (Page 2, Table 1 and right column, last paragraph: several UART commands can be sent to the external WDT to specify a timeout interval as opposed to internal WDTs (Page 1, para. 1)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Majewski and Texas Instruments by implementing the UART interface taught by Texas Instruments. One of ordinary skill in the art would be motivated to make this modification in order to provide a low-cost configurable external WDT for system redundancy and robustness (Texas Instruments: Page 1, left column, para. 2).
Regarding Claim 18, PRAGASH discloses the method of claim 10, as referenced above.
PRAGASH does not disclose:
further comprising configuring the second timeout duration over a serial interface.
However, Texas Instruments teaches:
further comprising configuring the second timeout duration over a serial interface (Page 2, Table 1 and right column, last paragraph: lists several UART commands to specify a timeout interval for external WDTs as opposed to internal WDTs (Page 1, para. 1)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Majewski and Texas Instruments by implementing the UART interface taught by Texas Instruments. One of ordinary skill in the art would be motivated to make this modification in order to provide a low-cost configurable external WDT for system redundancy and robustness (Texas Instruments: Page 1, left column, para. 2).
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over PRAGASH in view of Kosut et al. (US 20140201578 A1, hereinafter “Kosut”), in further view of Wikipedia (NPL: “Static random-access memory”).
Regarding Claim 23, PRAGASH discloses the dual timing circuit of claim 1, as referenced above.
PRAGASH does not disclose:
further comprising latches that are coupled to the processor through a reset indicator signal with the reset indicator signal being received at the latches by one or both of the start-up circuit and the operations circuit.
However, Kosut teaches:
further comprising a storage location that are coupled to the processor through a reset indicator signal with the reset indicator signal being received at the storage location by one or both of the start-up circuit and the operations circuit ([0036]: when compare 208 indicates that chip watchdog counter 204 has expired, compare 208 triggers a chip reset. Chip watchdog 120 further stores an indication in storage location 210 that a chip reset has occurred. [0034]-[0035]: chip watchdog counter 204 + compare 208 monitors normal operation of device 100 and resets if device 100 is in an error state. Thus, interpreted as operations circuit. Fig. 2; [0029]: storage location 210 embodied within a processor. [0043]: store data relating to the error to volatile memory (e.g., RAM). Storage location 210 coupled to a processor stores a reset indication asserted by counter 204 + compare 208).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH and Kosut by implementing the storage location taught by Kosut within watchdog system 100 taught by PRAGASH. One of ordinary skill in the art would be motivated to make this modification in order to determine what type of error has occurred (Kosut: [0036]). PRAGASH in view of Kosut does not teach:
…latches…
However, Wikipedia teaches:
…latches… (Page 1: SRAM uses latching circuitry (flip-flop) to store each bit)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH, Kosut, and Wikipedia by performing a simple substitution of one known element (Kosut: [0043]: volatile memory such as RAM) for another (Wikipedia: Page 1: volatile memory SRAM) to obtain predictable results (RAM volatile memory).
Regarding Claim 24, PRAGASH in view of Kosut, in further view of Wikipedia teaches the dual timing circuit of claim 23, as referenced above, wherein the latches are single-bit memory latches (Wikipedia: Page 1: SRAM uses latching circuitry (flip-flop) to store each bit. Hence, each flip-flop stores a single bit).
Response to Arguments
Applicant's arguments filed 01/30/2026 have been fully considered but they are not persuasive.
Regarding 102 of Claim 1, Applicant argues:
“Pragash does not disclose the concepts of a dual timing circuit with two circuits that each receive a strobe signal. Conversely, Pragash discloses a system that monitors receipt and timing of acknowledgement signals to determine the need for a processor reset. For at least these reasons, independent claim 1 and its dependent claims are not anticipated by Pragash.”
“Independent claim 10 has been amended to now include the start-up circuit and the operations circuit asserting a reset signal in response to failing to receive the strobe signal. The claim now also includes that receiving the strobe signal indicates that the processor is operating normally and not receiving the strobe signal indicates that the processor is not properly functioning, and that the strobe signal is initiated after the dual timing circuit that includes the start-up circuit and the operation circuit is fully configured. For at least these reasons, independent claim 10 and its dependent claims are not anticipated by Pragash.”
Examiner respectfully disagrees.
Regarding A, as cited above and in Fig. 1, [0029]-[0031], watchdog system 100 contains two timing circuits, { control logic 120 - delay component 130 - save & reset logic 160 } and { control logic 120 – delay component 130 – save & reset logic 160 } that receives an acknowledgement signal “Ack1” from an unshown processor through IO lines 115A-115N. The acknowledgement signal is consistent with [0050] of the instant specification, where a strobe signal (or keep-alive signal) is received from the processor.
Regarding B, PRAGASH anticipates the amended limitations of Claim 10. Please see above for further details.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CATHERINE MARIE NGUYEN whose telephone number is (571)272-6160. The examiner can normally be reached M-F 7:30 AM - 4:30 PM ET.
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114