DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4-6, 10-18, and 22-28 are pending for examination.
This Office Action is Non-Final.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/11/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 18 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 18 recites “The method of claim 10, further comprising configuring the second timeout duration over a serial interface.” However, Claim 18 does not further limit Claim 10, which recites “…configuring the second timeout duration by the processor through a serial interface that is independent of the strobe signal and the disable signal.”
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 10-18, 22, and 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over PRAGASH et al. (WO 2005072052 A2, as cited in the IDS, hereinafter “PRAGASH”) in view of Majewski et al. (US 20080276132 A1, hereinafter “Majewski”), in view of LAI (TW I805341 B), in further view of Wikipedia (NPL: “General-purpose input/output,” hereinafter “Wikipedia GPIO”).
Regarding Claim 1, PRAGASH discloses a dual timing circuit configured to reset a processor upon detecting a fault (Fig. 1: watchdog system 100 contains a first boot timer ([0024]: delay component 130) and a second operational timer ([0027]: monitor 180), both of which are configured to trigger a reset of the monitored processor upon detecting a boot initialization fault or periodicity fault, respectively), the dual timing circuit comprising:
a start-up circuit , the start-up circuit configured with a first timeout duration, wherein the start-up circuit is operative to assert a reset signal in response to failing to receive a strobe signal from the processor within the first timeout duration after powering on (Fig. 1 and [0024]: delay component 130 provides a specified delay (“boot up period”) for the processor and triggers a reset of the processor after failing to receive an acknowledgement signal from the processor during the boot up period. [0026]: save & reset logic 160 actuates a reset signal to reset the processor. Fig. 2 and [0028]: boot up period refers to boot state 210, in which watchdog system 100 is in the boot state 210 on power up. Therefore, a start-up circuit (control logic 120 + delay component 130 + save & reset logic 160) is configured with a boot up period timeout duration and asserts a reset signal in response to failing to receive an acknowledgement signal (“strobe signal”) from the processor within the boot load period on power up. The strobe signal interpretation is consistent with [0050] of the instant spec: “Processor 110 is configured to send a strobe signal 120 (or keep-alive signal)…”); and
an operations circuit , the operations circuit configured with a second timeout duration, wherein the operations circuit is operative to assert the reset signal in response to failing to receive the strobe signal from the processor within the second timeout duration (Fig. 1 and [0027]-[0028]: monitor 180 supervises the periodicity and order of acknowledgement pulses according to a stored supervision policy. Monitor 180 instructs save & reset logic 160 to reset the processor if all N acknowledgement signals are not received before expiration of the cycle period. [0036]: acknowledgement signals are received from the processor. Therefore, an operations circuit (control logic 120 + monitor 180 + save & reset logic 160) is configured with a cycle period and asserts a reset signal in response to failing to receive all N acknowledgement signals from the processor within the cycle period);
wherein the strobe signal is configured to be operatively provided to both the start-up circuit and the operations circuit (Fig. 1; [0024]; [0029]: acknowledgement signal (e.g., Ack1) configured to be sent to delay component 130 of control logic 120 - delay component 130 - save & reset logic 160 circuit (start-up circuit, see above). Fig. 1; [0027]; [0031]: acknowledgement signals (e.g., including another Ack1) configured to be sent to monitor 180 of control logic 120 – monitor 180 – save & reset logic 160 circuit (operations circuit, see above)) and wherein receiving the strobe signal indicates that the processor is operating normally and not receiving the strobe signal indicates that the processor is not properly functioning ([0024]; [0029]-[0030]: upon receiving an acknowledgement signal 310 during boot up period, normal operational state cycle 230 begins. Not receiving an acknowledgement signal during the boot up period indicates the processor failed to properly initialize. [0031]-[0033]: at the expiration of the forbidden period, another first acknowledgement signal 320 (Ack 1) is expected. Failure to receive the signal before the expiration of the cycle period T and in a specific order triggers a reset of the processor (processor ack transmissions are not functioning properly));
wherein the strobe signal is initiated after the dual timing circuit is fully configured (Fig. 2; [0028]-[0029]: send ack1 to interpreted boot circuit (see above) during boot state 210 and boot period tb begins. Fig. 2; [0028]; [0031]-[0033]: send another ack1 to interpreted operations circuit (see above) during operational state 230, when cycle period T begins, and after forbidden period t0 expires without receiving an acknowledgement signal);
wherein each of the start-up circuit and the operations circuit are external to the processor (Fig. 1 and [0021]: watchdog system 100 is coupled to one or more processors (not shown) through processor interface 110. All components of watchdog system 100 (including the interpreted start-up circuit and operations circuit described above) are therefore external to the one or more processors).
PRAGASH does not disclose:
a start-up circuit that is hardware controlled…
an operations circuit that is software controlled…
wherein the start-up circuit is coupled to the processor through a disable signal that is independent of the strobe signal and the reset signal;
wherein the operations circuit is coupled to the processor through a serial interface that is independent of the strobe signal and the reset signal, wherein the second timeout duration is configured to be set through the serial interface; and
However, Majewski teaches:
a start-up circuit that is hardware controlled (Fig. 1 and [0045]: internal watchdog timer may have a hardware enable input configurated to enable the internal watchdog timer during the operating system startup sequence)…
an operations circuit that is software controlled (Fig. 1 and [0009]: external watchdog timer (WDT) 16 is initiated after the OS is fully launched and running. External WDT is interpreted as an operations circuit as it monitors and resets the processor if the OS faults and fails to toggle the external WDT’s strobe input (see [0048]). [0027]: external WDT 16 may be enabled by BIOS, other locally stored program of processor 12, or the COTS OS itself)…
wherein the operations circuit is coupled to the processor through a interface that is independent of the strobe signal and the reset signal, wherein the second timeout duration is configured to be set through the interface ([0047]-[0048]: external watchdog timer may include an enable input to enable the external watchdog timer, a strobe input, and a reset output. The enable input and strobe input may be coupled to the one or more primary GPIOs 64 of the microprocessor 61, which may enable the external watchdog timer 62 and toggle the strobe input of the external watchdog timer 62 when the microprocessor 61 is operating properly. [0020]: enable refers to enabling or initiating the external watchdog timer. I.e., external watchdog timer coupled to microprocessor through GPIO, independent of (separate from) strobe input and reset output. Enable input sent through GPIO initiates external watchdog timer (encompasses initiating external watchdog timer duration)); and
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH and Majewski by implementing the enablement signals and GPIO communication taught by Majewski. One of ordinary skill in the art would be motivated to make this modification in order to initiate the timers at different times (Majewski: [0020]).
PRAGASH in view of Majewski does not teach:
wherein the start-up circuit is coupled to the processor through a disable signal that is independent of the strobe signal and the reset signal;
…serial interface…
However, PRAGASH in view of Majewski, in view of LAI teaches:
wherein the start-up circuit is coupled to the processor through a disable signal (LAI: Page 6, fifth-sixth paragraphs: “Next, when the OTFDEC circuit 340 is in the normal mode, the CPU 310 executes the encrypted boot code in the boot area of the non-volatile memory 380 (step S403). Wherein, the encrypted boot code includes a disable command for disabling the timer 360… The process of executing the plaintext (that is, the decoded boot code) by CPU 310 will disable the timer 360 and complete the initialization procedure…”) that is independent of the strobe signal and the reset signal (PRAGASH: [0024]: processor initializes and sends an ACK signal. When the ACK signal isn’t received during the boot up period, delay component 130 triggers a reset of the processor. [0026]: resets by sending a reset signal. [0020]: ACK and reset signals are separate structures from processor initialization/boot loader code);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH, Majewski, and LAI by implementing the disable command within the bootup code taught by LAI. One of ordinary skill in the art would be motivated to make this modification in order to complete the initialization procedure and prevent the timer from triggering a warm reset (LAI: Page 6, para. 5-6 and 9-10).
PRAGASH in view of Majewski, in view of LAI does not teach:
…serial interface…
However, Wikipedia GPIO teaches:
…serial interface… (Page 1, “Integrated circuit GPIOs,” first paragraph: GPIO expander ICs interface GPIOs to serial communication buses such as I2C and SMBus. Page 3, “Usage,” fourth paragraph: two GPIOs may be used to implement a serial communication bus such as I2C, and four GPIOs can be used to implement a Serial Peripheral Interface (SPI) bus; these are usually used to facilitate serial communication with ICs and other devices which have compatible serial interfaces)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH, Majewski, LAI, and Wikipedia GPIO by implementing the GPIO/serial communication taught by Wikipedia GPIO as part of the GPIO communication taught by Majewski ([0047]-[0048]). One of ordinary skill in the art would be motivated to make this modification since GPIO is merely a pin/port used to establish communication buses (e.g., serial or parallel). Thus, when ICs and other devices have [existing] compatible serial interfaces, GPIOs are used to facilitate serial communication to said ICs and other devices (Wikipedia GPIO: Page 1, para. 1-2; Page 3, “Usage,” fourth paragraph).
Regarding Claim 4, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above, wherein the dual timing circuit is further configured to assert a second reset signal to the processor in response to either the start-up circuit or the operations circuit asserting the reset signal (PRAGASH: Fig. 1 and [0024]: delay component 130 triggers a reset of the processor. [0026]: save & reset logic 160 is the component that actuates a reset signal 164 to the processor. Therefore, delay component 130 asserts a reset “signal” to save & reset logic 160, which then asserts reset signal 164 to the processor).
Regarding Claim 5, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above, further comprising:
a first memory element configured to store a reset indicator signal indicating a source of the reset signal asserted by the start-up circuit (PRAGASH: [0026]: save & reset logic 160 additionally asserts to the processor a save signal 168 that stores information to identify data surrounding the cause/source for reset. Interrupt Service Routine (ISR) stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168). [0024] and [0028]: delay component 130 uses save & reset logic 160 to send a reset signal to the processor. Therefore, ISR stores save signal 168 (understood by one of ordinary skill in the art to be stored in a memory element) that indicates a source of the reset signal, in which the reset signal was asserted by delay component 130); and
a second memory element configured to store the reset indicator signal indicating the source of the reset signal asserted by the operations circuit (PRAGASH: [0027]: similar reasoning above except with monitor 180 instead of delay component 130 -- monitor 180 also uses save & reset logic 160 to reset the processor, which contains a save signal 168 storing a source of the reset signal, wherein the reset signal was asserted by monitor 180. Save signal 168 is stored by ISR, wherein the storage location is understood by one of ordinary skill in the art to be a memory element).
Regarding Claim 6, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above, wherein the processor is configured to disable the start-up circuit after a boot load is completed by the processor and the operations circuit is configured correctly (PRAGASH: Fig. 2 and [0028]: if an acknowledgement signal is received during the boot up period ([0024]: by the processor), the watchdog system 100 moves to the operational state 230 immediately. Since watchdog system 100 operates as a state machine, the transition to operation state 230 effectively disables the boot state and boot state related components ([0024], [0026]: control logic 120, delay component 130, and save & reset logic 160, interpreted as the start-up circuit) and the control logic 120, monitor 180, and save & reset logic 160 is configured correctly through the immediate transition (see [0030]-[0031] – operational state 230 starts with various period durations upon receiving the same acknowledgement signal 310 within the boot state. [0025]: periods are predetermined and unable to be modified, thus the interpreted operations circuit is configured correctly prior to the immediate transition).
Regarding Claim 10, PRAGASH discloses a method for resetting a processor upon detecting a fault (Fig. 1), the method comprising:
asserting, by a start-up circuit that is external to the processor and configured with a first timeout duration, a reset signal in response to failing to receive a strobe signal from the processor within the first timeout duration (Fig. 1 and [0024]: delay component 130 provides a specified delay (“boot up period”) for the processor and triggers a reset of the processor failing to receive an acknowledgement signal from the processor during the boot up period. [0026]: save & reset logic 160 actuates a reset signal to reset the processor. Therefore, a start-up circuit (control logic 120 + delay component 130 + save & reset logic 160) is configured with a boot up period timeout duration and asserts a reset signal in response to failing to receive an acknowledgement signal (“strobe signal”) from the processor within the boot up period. The strobe signal interpretation is consistent with [0050] of the instant spec: “Processor 110 is configured to send a strobe signal 120 (or keep-alive signal)…” Fig. 1 and [0021]: watchdog system 100 is coupled to one or more processors (not shown) through processor interface 110. Therefore, all components of watchdog system 100 (including the interpreted start-up circuit) are external to the one or more processors);
asserting, by a operations circuit that is external to the processor and configured with a second timeout duration, the reset signal in response to failing to receive the strobe signal from the processor within the second timeout duration (Fig. 1 and [0027]-[0028]: monitor 180 supervises the periodicity and order of acknowledgement pulses according to a stored supervision policy. Monitor 180 instructs save & reset logic 160 to reset the processor if all N acknowledgement signals are not received before expiration of the cycle period. [0036]: acknowledgement signals are received from the processor. Therefore, an operations circuit (control logic 120 + monitor 180 + save & reset logic 160) is configured with a cycle period and asserts a reset signal in response to failing to receive all N acknowledgement signals from the processor within the cycle period. Fig. 1 and [0021]: watchdog system 100 is coupled to one or more processors (not shown) through processor interface 110. Therefore, all components of watchdog system 100 (including the interpreted operations circuit) are external to the one or more processors), said strobe signal is operatively provided to both the start-up circuit and the operations circuit (Fig. 1; [0024]; [0029]: acknowledgement signal (e.g., Ack1) configured to be sent to delay component 130 of control logic 120 - delay component 130 - save & reset logic 160 circuit (start-up circuit, see above). Fig. 1; [0027]; [0031]: acknowledgement signals (e.g., including another Ack1) configured to be sent to monitor 180 of control logic 120 – monitor 180 – save & reset logic 160 circuit (operations circuit, see above)), wherein receiving the strobe signal indicates that the processor is operating normally and not receiving the strobe signal indicates that the processor is not properly functioning ([0024]; [0029]-[0030]: upon receiving an acknowledgement signal 310 during boot up period, normal operational state cycle 230 begins. Not receiving an acknowledgement signal during the boot up period indicates the processor failed to properly initialize. [0031]-[0033]: at the expiration of the forbidden period, another first acknowledgement signal 320 (Ack 1) is expected. Failure to receive the signal before the expiration of the cycle period T and in a specific order triggers a reset of the processor (processor ack transmissions are not functioning properly)), and wherein the strobe signal is initiated after a dual timing circuit that includes the start- up circuit and the operations circuit is fully configured (Fig. 2; [0028]-[0029]: send ack1 to interpreted boot circuit (see above) during boot state 210 and boot period tb begins. Fig. 2; [0028]; [0031]-[0033]: send another ack1 to interpreted operations circuit (see above) during operational state 230, when cycle period T begins, and after forbidden period t0 expires without receiving an acknowledgement signal);
PRAGASH does not disclose:
…a hardware controlled start-up circuit…
…a software controlled operations circuit…
disabling the start-up circuit with a disable signal from the processor that is independent from the strobe signal; and
configuring the second timeout duration by the processor through a serial interface that is independent of the strobe signal and the disable signal.
However, Majewski teaches:
…a hardware controlled start-up circuit… (Fig. 1 and [0045]: internal watchdog timer may have a hardware enable input configurated to enable the internal watchdog timer during the operating system startup sequence)
…a software controlled operations circuit… (Fig. 1 and [0009]: external watchdog timer (WDT) 16 is initiated after the OS is fully launched and running. External WDT is interpreted as an operations circuit as it monitors and resets the processor if the OS faults and fails to toggle the external WDT’s strobe input (see [0048]). [0027]: external WDT 16 may be enabled by BIOS, other locally stored program of processor 12, or the COTS OS itself)
configuring the second timeout duration by the processor through a interface that is independent of the strobe signal ([0047]-[0048]: external watchdog timer may include an enable input to enable the external watchdog timer, a strobe input, and a reset output. The enable input and strobe input may be coupled to the one or more primary GPIOs 64 of the microprocessor 61, which may enable the external watchdog timer 62 and toggle the strobe input of the external watchdog timer 62 when the microprocessor 61 is operating properly. [0020]: enable refers to enabling or initiating the external watchdog timer. I.e., external watchdog timer coupled to microprocessor through GPIO, independent of (separate from) strobe input. Enable input sent through GPIO initiates external watchdog timer (encompasses initiating external watchdog timer duration))
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH and Majewski by implementing the enablement signals and GPIO communication taught by Majewski. One of ordinary skill in the art would be motivated to make this modification in order to initiate the timers at different times (Majewski: [0020]).
PRAGASH in view of Majewski does not teach:
disabling the start-up circuit with a disable signal from the processor that is independent from the strobe signal; and
…serial interface…
…and the disable signal…
However, PRAGASH in view of Majewski, in view of LAI teaches:
disabling the start-up circuit with a disable signal from the processor (LAI: Page 6, fifth-sixth paragraphs: “Next, when the OTFDEC circuit 340 is in the normal mode, the CPU 310 executes the encrypted boot code in the boot area of the non-volatile memory 380 (step S403). Wherein, the encrypted boot code includes a disable command for disabling the timer 360… The process of executing the plaintext (that is, the decoded boot code) by CPU 310 will disable the timer 360 and complete the initialization procedure…”) that is independent from the strobe signal (PRAGASH: [0024]: processor initializes and sends an ACK signal. When the ACK signal isn’t received during the boot up period, delay component 130 triggers a reset of the processor. [0020]: initialization procedure/boot loader code separate from ACK signal); and
configuring the second timeout duration by the processor through a interface that is independent of the strobe signal and the disable signal (LAI: Page 6, fifth-sixth paragraphs: disable command part of initialization procedure/boot code. Majewski: [0020]; [0047]-[0048]: separate enable input, GPIO, and strobe input structure to enable external watchdog timer after OS has launched and is up and running).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH, Majewski, and LAI by implementing the disable command within the bootup code taught by LAI. One of ordinary skill in the art would be motivated to make this modification in order to complete the initialization procedure and prevent the timer from triggering a warm reset (LAI: Page 6, para. 5-6 and 9-10).
PRAGASH in view of Majewski, in view of LAI does not teach:
…serial interface…
However, Wikipedia GPIO teaches:
…serial interface… (Page 1, “Integrated circuit GPIOs,” first paragraph: GPIO expander ICs interface GPIOs to serial communication buses such as I2C and SMBus. Page 3, “Usage,” fourth paragraph: two GPIOs may be used to implement a serial communication bus such as I2C, and four GPIOs can be used to implement a Serial Peripheral Interface (SPI) bus; these are usually used to facilitate serial communication with ICs and other devices which have compatible serial interfaces)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH, Majewski, LAI, and Wikipedia GPIO by implementing the GPIO/serial communication taught by Wikipedia GPIO as part of the GPIO communication taught by Majewski ([0047]-[0048]). One of ordinary skill in the art would be motivated to make this modification since GPIO is merely a pin/port used to establish communication buses (e.g., serial or parallel). Thus, when ICs and other devices have [existing] compatible serial interfaces, GPIOs are used to facilitate serial communication to said ICs and other devices (Wikipedia GPIO: Page 1, para. 1-2; Page 3, “Usage,” fourth paragraph).
Regarding Claim 11, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising disabling the start-up circuit in response to a boot load by the processor completing within the first timeout duration (LAI: Page 6: para. 5-6, 9-10: CPU 310 executes the encrypted boot code… wherein the encrypted boot code includes a disable command for disabling the timer 360. The process of executing the plaintext (that is, the decoded boot code) by CPU 310 will disable the timer 360 and complete the initialization procedure (initialization… [Conversely, since] the central processing unit 310 cannot disable the timer 360, the timer 360 changes the OTFDEC circuit 340 to bypass mode after a certain period of time, and triggers a warm reset to the central processing unit 310. CPU 310 disables timer 360 in response to successfully executing (and thus completing) boot code within the time period. Else, after the time period and if not disabled, timer 360 triggers a warm reset).
Regarding Claim 12, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising enabling the operations circuit in response to a boot load by the processor completing within the first timeout duration (PRAGASH: [0028]: if an acknowledgement signal is received during the boot up period ([0024]: which indicates the processor successfully initializing during boot load), watchdog system 100 moves to operational state 230 immediately. Operational state 230 uses control logic 120, monitor 180, and save & reset logic 160 (see [0027], [0031]-[0033]). Therefore, the transition to operational state 230 encompasses enabling the interpreted operations circuit in response to the processor completing the boot load initialization within the boot up period).
Regarding Claim 13, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising configuring the operations circuit in response to a boot load by the processor completing (PRAGASH: [0028]: if an acknowledgement signal is received during the boot up period ([0024]: which indicates the processor successfully initializing during boot load), watchdog system 100 moves to operational state 230 immediately. Operational state 230 uses control logic 120, monitor 180, and save & reset logic 160 (see [0027], [0031]-[0033]). Therefore, the transition to operational state 230 encompasses configuring the interpreted operations circuit in response to the processor completing the boot load initialization within the boot up period).
Regarding Claim 14, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising, in response to failing to receive the strobe signal from the processor within the second timeout duration, writing a reset indicator signal indicating a source of the reset signal asserted by the operations circuit to a second memory element (PRAGASH: [0027]: if all N acknowledgement signals are not received ([0036]: from the processor) before the expiration of the cycle period, monitor 180 instructs the save & reset logic 160 to reset the processor. [0026]: before sending reset signal 164, save & reset logic 160 asserts (writes) a save signal 168 indicating the cause for reset to the processor and ISR. ISR stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168 triggered by monitor 180). Therefore, in response to failing to receive all N signals from the processor within the cycle period, save signal 168 indicating a cause of the reset signal asserted by monitor 180 is stored by the ISR. One of ordinary skill in the art would understand that the storage location is a memory element).
Regarding Claim 15, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising, in response to failing to complete a boot load by the processor within the first timeout duration, writing a reset indicator signal indicating a source of the reset signal asserted by the start-up circuit (PRAGASH: [0024]: if the processor fails to initialize during the boot up period, delay component 130 triggers a reset of the processor. [0026]: before sending reset signal 164, save & reset logic 160 asserts (writes) a save signal 168 indicating the cause for reset to the processor and ISR. ISR stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168 triggered by monitor 180). Therefore, in response to failing to complete the boot initialization by the processor within the boot up period, save signal 168 indicating a cause of the reset signal asserted by delay component 130 is stored by the ISR).
Regarding Claim 16, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising:
storing, by a first memory element, an indication of a reset signal asserted by the start-up circuit (PRAGASH: [0026]: save & reset logic 160 additionally asserts to the processor a save signal 168 that stores information to identify data surrounding the cause/source for reset. Interrupt Service Routine (ISR) stores the event that triggered this interrupt and information identifying the particular IO line misbehaved (i.e., cause for reset as indicated by save signal 168). [0024] and [0028]: delay component 130 uses save & reset logic 160 to send a reset signal to the processor. Therefore, ISR stores save signal 168 (understood by one of ordinary skill in the art to be stored in a memory element) that indicates a source of the reset signal, in which the reset signal was asserted by delay component 130);
and storing, by a second memory element, an indication of a reset signal asserted by the operations circuit (PRAGASH: [0027]: similar reasoning above except with monitor 180 instead of delay component 130 -- monitor 180 also uses save & reset logic 160 to reset the processor, which contains a save signal 168 storing a source of the reset signal, wherein the reset signal was asserted by monitor 180. Save signal 168 is stored by ISR, wherein the storage location is understood by one of ordinary skill in the art to be a memory element).
Regarding Claim 17, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising asserting a single reset signal to the processor in response to either the start-up circuit or the operations circuit asserting reset (PRAGASH: [0024]: delay component 130 triggers a reset of the processor. [0026]: save & reset logic 160 is the component that actuates a reset signal to reset the processor. A single reset signal 164 is then asserted to the processor in response to delay component 130 invoking reset to save & reset logic 160).
Regarding Claim 18, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising configuring the second timeout duration over a serial interface (Majewski: [0047]-[0048]: external watchdog timer may include an enable input to enable the external watchdog timer, a strobe input, and a reset output. The enable input and strobe input may be coupled to the one or more primary GPIOs 64 of the microprocessor 61, which may enable the external watchdog timer 62 and toggle the strobe input of the external watchdog timer 62 when the microprocessor 61 is operating properly. [0020]: enable refers to enabling or initiating the external watchdog timer (encompasses external watchdog timer duration). Enables external watchdog timer duration over GPIO interface. Wikipedia GPIO: Page 1, “Integrated circuit GPIOs,” first paragraph: GPIO expander ICs interface GPIOs to serial communication buses such as I2C and SMBus. Page 3, “Usage,” fourth paragraph: two GPIOs may be used to implement a serial communication bus such as I2C, and four GPIOs can be used to implement a Serial Peripheral Interface (SPI) bus; these are usually used to facilitate serial communication with ICs and other devices which have compatible serial interfaces. GPIO implements serial interface).
Regarding Claim 22, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above, wherein the dual timing circuit is connected to the processor by the strobe signal (PRAGASH: Fig. 1; [0021]: processor generates acknowledgement signals and sends the signals to watchdog system 100 over IO lines 115A-N) and by the serial interface (Majewski: Fig. 6; [0047]-[0048]: external watchdog timer 62 connected to microprocessor 61 via GPIOs 64. Wikipedia GPIO: Page 1, “Integrated circuit GPIOs,” first paragraph; Page 3, “Usage,” fourth paragraph: GPIO implements serial communication).
Regarding Claim 25, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the method of claim 10, as referenced above, further comprising connecting the processor to the dual timing circuit with both the strobe signal (PRAGASH: Fig. 1; [0021]: processor generates acknowledgement signals and sends the signals to watchdog system 100 over IO lines 115A-N) and with the serial interface (Majewski: Fig. 6; [0047]-[0048]: external watchdog timer 62 connected to microprocessor 61 via GPIOs 64. Wikipedia GPIO: Page 1, “Integrated circuit GPIOs,” first paragraph; Page 3, “Usage,” fourth paragraph: GPIO implements serial communication).
Regarding Claim 26, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above, wherein the start-up circuit is configured to be disabled by software once a start-up process is completed (LAI: Page 6: para. 5-6: CPU 310 executes encrypted boot code… [wherein] the encrypted boot code includes a disable command for disabling the timer 360… The process of executing the plaintext (that is, the decoded boot code) by the CPU 310 will disable the timer 360 and complete the initialization procedure).
Regarding Claim 27, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above, wherein the start-up circuit is configured to provide start-up timeout monitoring without dependency on software (Majewski: Fig. 1; [0023]; [0045]: when enabled, internal watchdog timer monitors the processor during OS startup… Internal watchdog timer may have a hardware enable input configurated to enable the internal watchdog timer during the operating system startup sequence. Consistent with [0049] of instant spec, where start-up circuit is predominantly hardware-controlled; no dependency on software to enable hardware functions).
Regarding Claim 28, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above.
Majewski further teaches:
wherein the operations circuit fulfills a higher resolution timeout requirement than the start-up circuit ([0026]: external watchdog timer 16 may have a timer duration of, for example, tenths of seconds, seconds, tens of seconds, or longer as desired. [0025]: internal watchdog timer 14 may be programmed or otherwise configured to have a relatively longer timer duration [to] allow for complete startup of the processor 12 operating system…. The internal watchdog timer 14 may be about five minutes or more. Seconds are a higher resolution than minutes. Consistent with [0048] of instant spec, where operations timer set to 10 ms compared to 10 sec start-up timer).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to further combine with Majewski by implementing the timer durations taught by Majewski. One of ordinary skill in the art would be motivated to make this modification in order to allow complete startup of the processor under normal startup conditions (Majewski: [0025]).
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over PRAGASH in view of Majewski, in view of LAI, in view of Wikipedia GPIO, in view of Kosut et al. (US 20140201578 A1, hereinafter “Kosut”), in further view of Wikipedia (NPL: “Static random-access memory,” hereinafter “Wikipedia SRAM”).
Regarding Claim 23, PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO teaches the dual timing circuit of claim 1, as referenced above.
PRAGASH in view of Majewski, in view of LAI, in further view of Wikipedia GPIO does not teach:
further comprising latches that are coupled to the processor through a reset indicator signal with the reset indicator signal being received at the latches by one or both of the start-up circuit and the operations circuit.
However, Kosut teaches:
further comprising a storage location that are coupled to the processor through a reset indicator signal with the reset indicator signal being received at the storage location by one or both of the start-up circuit and the operations circuit ([0036]: when compare 208 indicates that chip watchdog counter 204 has expired, compare 208 triggers a chip reset. Chip watchdog 120 further stores an indication in storage location 210 that a chip reset has occurred. [0034]-[0035]: chip watchdog counter 204 + compare 208 monitors normal operation of device 100 and resets if device 100 is in an error state. Thus, interpreted as operations circuit. Fig. 2; [0029]: storage location 210 embodied within a processor. [0043]: store data relating to the error to volatile memory (e.g., RAM). Storage location 210 coupled to a processor stores a reset indication asserted by counter 204 + compare 208).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PRAGASH, Majewski, LAI, Wikipedia GPIO, and Kosut by implementing the storage location taught by Kosut within watchdog system 100 taught by PRAGASH. One of ordinary skill in the art would be motivated to make this modification in order to determine what type of error has occurred (Kosut: [0036]).
PRAGASH in view of Majewski, in view of LAI, in view of Wikipedia GPIO, in view of Kosut does not teach:
…latches…
However, Wikipedia SRAM teaches:
…latches… (Page 1: SRAM uses latching circuitry (flip-flop) to store each bit)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to perform a simple substitution of one known element (Kosut: [0043]: volatile memory such as RAM) for another (Wikipedia SRAM: Page 1: volatile memory SRAM) to obtain predictable results (RAM volatile memory).
Regarding Claim 24, PRAGASH in view of Majewski, in view of LAI, in view of Wikipedia GPIO, in view of Kosut, in further view of Wikipedia SRAM teaches the dual timing circuit of claim 23, as referenced above, wherein the latches are single-bit memory latches (Wikipedia SRAM: Page 1: SRAM uses latching circuitry (flip-flop) to store each bit. Hence, each flip-flop stores a single bit).
Response to Arguments
Applicant’s arguments with respect to 35 U.S.C. 102/103 of claim(s) 1, 4-6, 10-18, and 22-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Emerson et al. (US 20070083719 A1) -- [0070]: if IOP (I/O processor) 302 is operational, it may decline or honor the request to reset embodied by the NMI. For the IOP 302 to decline the reset request, it should disable the failsafe boot timer 610 before its countdown expires and clear the predetermined bit or bits that correspond to the reset request in the failsafe register
Conclusion
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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