DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 10-28 are pending in the application.
Examiner’s Note: The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS."
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/08/2024, 05/30/2024, 12/10/2024 was filed after the mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-17, 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Micheloni U.S. Patent No. 9,899,092 in view of Healy et al. US Pub. No. 2016/0328291 (“Healy”).
Regarding claim 10, Micheloni teaches a computerized logic configured for assessing performance of a characterized memory device [NAND 20], the computerized logic comprising:
first computerized logic [14 – SEE fig. 1] configured to, when executed, make a determination that a performance of a memory apparatus is outside of an expected solution density function [block BER exceeds a block BER threshold], thereby indicating that a fault [high errors rate, data corruption] occurred within an actual solution density function [SEE further Col. 11 lines 14-37]; and
(20) Characteristics module 14 is configured to determine characteristics of NAND devices 20. The characteristics may be stored in data storage 15 on nonvolatile memory controller 10 (e.g., registers or a memory array), or may be stored on one or more NAND device 20. NAND device 20 includes memory cells that are organized into blocks and pages, with each page composed of a main data area and a spare area. In one embodiment the determined usage characteristics are stored in the spare area of one or more page of NAND device 20.
(22) The characteristics stored by characteristics module 14 may include characteristics that indicate the performance of NAND device 20 that may be referred to hereinafter as “performance characteristics.” The stored performance characteristics include test results from tests on each NAND device 20, which may include the number of read errors from the test (e.g., the total number of errors in each test block of memory cells that is read) and/or the number of errors of the page in the block having the highest number of errors, that may be referred to hereinafter as the “maximum number of errors” of the block. In one embodiment, characteristics module 14 includes an online test module configured to perform reads of memory cells of a NAND device during operation of the NAND device to determine the error rate of the NAND device. The error rate can be determined by reading one or more dedicated test block to determine a maximum number of errors in each dedicated test block, the determined maximum number of errors determined to be the Bit Error Rate (BER) of the NAND device. [Col. 4 lines 26-44]
(23) In one exemplary embodiment, characteristics module 14 includes an online test module configured to perform reads of memory cells of a NAND device during operation of the NAND device to determine an error rate for each block of the NAND device, that can be referred to as the “block BER.” When the block BER exceeds a block BER threshold, program step circuit 13 is configured to change the program step voltage for the block to the different program step voltage. [Col. 4 lines 45-57]
second computerized logic [SEE Col. 9 lines 45-54] configured to, based at least on the determination that the performance is outside of the expected solution density function, determine to change the program step voltage - Col. 4 lines 45-57; and SEE steps of fig. 6].
Micheloni does not teach whether the fault is correctable or uncorrectable.
Healy teaches another computerized logic configured for assessing characteristic of a memory device by accessing data from a location within a memory device, determining memory errors in the data, and classifying the memory error (fault). Specifically, Healy teaches determine whether the fault is correctable or uncorrectable.
[0026] The memory controller 202 is a circuit that manages the flow of data to and from a computing device's memory. In some embodiments, the memory controller 202 may include a central processing unit (CPU) or a logic circuit. The CPU or logic circuit may be configured to control the general operation of the memory controller 202 in response to read/write requests by a computing device. The memory controller 202 may also include one or more buffers to temporarily store read/write data between transfers from the memory array 222 and the computing device. The memory controller 202 may support data flow from a computing device to a memory array via system buses (e.g., memory bus 110 of FIG. 1, address/command busses 204A and 204B, and data buses 206A and 206B). The memory controller 202 may also control the writing and reporting of various memory errors, according to embodiments. For example, the memory controller 202 may control the reporting of whether an error is uncorrectable versus correctable, a soft error or hard error, or an existing error or new error, as described further below. In some embodiments, the memory controller includes 202 ECC circuitry to detect and correct memory errors. In some embodiments, the memory controller 202 includes firmware for monitoring memory health and memory management (e.g., determine whether to replace memory, spare or mark memory as faulty, etc.). For example, the firmware may be a reliability, accessibility, and serviceability (RAS) module to assess and monitor memory health.
[0037] In some embodiments, the history bit circuitry module 326 is utilized to update the history bit field 306. History bit values within the history bit field 306 may provide a user additional information concerning potential memory errors in the data words 302. For example, once the ECC decoder 318 detects a memory error, the history bit circuitry module 326 may write a history bit value to specify whether an error is a known error (e.g., value of 1) or new error (e.g., value of 0), whether the error is a soft error (e.g., 1) or hard error (e.g., 0), whether the error is correctable, and whether the correctable error was uncorrectable at a previous time.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the system of Micheloni with a logic to determine whether the fault is correctable or uncorrectable. The motivation for doing so would has been, as suggested by Healy [par. 0015] to inform the user the health of the memory device and whether the user should replace or repair the memory devices causing the hard errors. Thus, would prevent machine crash or applications using corrupted data [SEE par. 0003 of Healy].
Regarding claim 11, Healy teaches third computerized logic configured to, based at least on a determination that the fault is correctable, cause at least one of a refresh or a re-characterization of the memory apparatus [par. 0014 - ECC memory may correct memory errors by matching an original copy of a code word (e.g., 64 bit message plus additional parity bits) with a corresponding code word read from memory; par. 0034, 00038, 0047].
Regarding claim 12, Healy teaches fourth computerized logic configured to, based at least on a determination that the fault is uncorrectable, indicate that at least a portion of the memory apparatus is to be replaced [par. 0015- Alternatively, the user may want to know if an error is a hard error to know whether the user should replace or repair the memory devices causing the hard error; SEE further par. 0026 and 0046].
Regarding claims 13-15, they are directed to the method of steps to implement the computerized logic as set forth in claims 10-12. Therefore, they are rejected on the same basis as set forth hereinabove.
Regarding claim 16, Micheloni teaches performance of the memory apparatus is assessed based on operating of the memory apparatus under a range of conditions [SEE fig. 5 and 16 – steps voltage].
Regarding claim 17, Micheloni teaches performance of the memory apparatus is assessed based on operating of the memory apparatus using a range of operational parameters [SEE fig. 5 and 16].
Regarding claims 21-23, they are directed to the system to implement the computerized logic as set forth in claims 10-12. Therefore, they are rejected on the same basis as set forth hereinabove.
Regarding claim 24, Micheloni teaches performance of the memory apparatus is assessed based on operating of the memory apparatus under a range of conditions [SEE fig. 5 and 16 – steps voltage].
Regarding claim 25, Micheloni teaches performance of the memory apparatus is assessed based on operating of the memory apparatus using a range of operational parameters [SEE fig. 5 and 16].
Allowable Subject Matter
Claims 18-20, 26-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 18-20, 26-28 are considered allowable since, when reading the claims in light of the specification, none of the references of record alone or in combination disclose or suggest the combination of subject matter specified in the dependent claim(s): the solution density function representative of at least of a probability of finding a valid solution for an application within a solution space.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. No. 2015/0074367 to Cher et al. teach a method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.
US Pub. No. 2011/0219285 to Nakamura teaches a semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT HUY TRAN whose telephone number is (571)272-7210. The examiner can normally be reached M-F 7:00-4:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini S Shah can be reached at 571-272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT H TRAN
Primary Examiner
Art Unit 2115
/VINCENT H TRAN/Primary Examiner, Art Unit 2115