DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 8-12, 16, 17, 20 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Williams (US 2004/0030819)
As to claim 1, Williams discloses a system, comprising:
a first subsystem coupled to a second subsystem by a communication circuit (¶0038); and
a debugging network, comprising: an aggregation network including a first leaf node coupled to a first functional circuit in the first subsystem and a first root node coupled to the first leaf node, wherein the first leaf node is configured to collect a first error information about a first error event in the first functional circuit and to transmit the first error information to the first root node (¶0011 & ¶0051); and
a distribution network including a second root node coupled to the first root node and to a second functional circuit in the second subsystem, wherein the second root node is configured to receive the first error information from the first root node and to distribute the first error information to the second functional circuit to perform an action corresponding to the first error information (¶0051, ¶0098 & ¶0138).
As to claim 2, Williams discloses the system of claim 1, further comprising: a third subsystem and a fourth subsystem coupled to the first subsystem and the second subsystem by the communication circuit, wherein the aggregation network further includes a second leaf node coupled to a third functional circuit in the third subsystem, and wherein: the second leaf node is configured to collect a second error information about a second error event in the third functional circuit and to transmit the second error event to the first root node; the first root node is configured to identify an order of occurrence between the first error event and the second error event; and the second root node is configured to receive the second error information and to distribute the second error information to a fourth functional circuit in the fourth subsystem to perform a second action corresponding to the second error information (¶0038-¶0039).
As to claim 4, Williams discloses the system of claim 1, wherein the first error information is stored in a register of the first leaf node (¶0048).
As to claim 8, Williams discloses the system of claim 1, wherein at least one of the first functional circuit or the second functional circuit includes a processor, a controller, a peripheral component, and a storage component in a system-on-chip (SoC) (¶0038 & ¶0046).
As to claim 9, Williams discloses the system of claim 1, wherein the aggregation network further includes a first tree with a first plurality of leaf nodes and a first inner node, and wherein the distribution network further includes a second tree with a second plurality of leaf nodes and a second inner node of the distribution network (Figure 1).
As to claim 10, Williams discloses the system of claim 1, wherein the first leaf node or the first root node is configured to perform event masking for the first error event (¶0096).
As to claim 11, Williams discloses the system of claim 1, wherein the first error event includes at least one of a non-recoverable error, a fabric error in the communication circuit, a security error caused by a security violation, an overflow of an internal hardware resource, a memory allocation error, and an invalid access detected by a memory controller (¶0049).
As to claim 12, Williams discloses a method, comprising:
collecting, by a leaf node of an aggregation network, an error information about an error event in an initiator functional circuit of an initiator subsystem (¶0023);
transmitting the error information from the leaf node to a root node of the aggregation network (¶0025);
receiving, by a root node of a distribution network, the error information from the root node of the aggregation network (¶0021); and
distributing the error information to a responding functional circuit of a responding subsystem, wherein the error information causes the responding functional circuit to perform an action corresponding to the error information (¶0138 & ¶0098).
As to claim 16, Williams discloses the method of claim 12, wherein the aggregation network includes a first tree with a first plurality of leaf nodes and a first plurality of inner nodes, and wherein the distribution network includes a second tree with a second plurality of leaf nodes and a second plurality of inner nodes, and wherein: the transmitting the error information comprises transmitting the error information from the leaf node of the aggregation network through first the plurality of inner nodes to the root node of the aggregation network; and the distributing the error information to the responding subsystem comprises distributing the error information through the second plurality of inner nodes and the second plurality of leaf nodes (Figure 1, ¶0098).
As to claim 17, Williams discloses a debugging system, comprising:
an aggregation network including leaf nodes coupled to functional circuits and a first root node coupled to the leaf nodes, wherein the leaf nodes are configured to collect error information about error events in the functional circuits and to transmit the error information to the first root node, and wherein the first root node is configured to identify an order of occurrence among the error events (¶0011 & ¶0051); and
a distribution network including a second root node coupled to the first root node and to responding functional circuits, wherein the second root node is configured to receive the error information from the first root node and to distribute the error information to the responding functional circuits to perform an action based on the error information and the order of occurrence among the error events (¶0138 & ¶0098).
As to claim 20, Williams discloses the debugging system of claim 17, wherein the functional circuits and the responding functional circuits are coupled by a communication circuit, and the error events include at least one of a non-recoverable error, a fabric error occurred in the communication circuit, a security error caused by a security violation, an overflow of an internal hardware resource, a memory allocation error, and an invalid access detected by a memory controller (¶0049).
As to claim 21, Williams discloses a system, comprising:
a first subsystem coupled to a second subsystem by a communication circuit (¶0038); and
a debugging network, comprising: an aggregation network including a first tree having a first leaf node coupled to a first functional circuit in the first subsystem and a first root node coupled to the first leaf node, wherein the first leaf node is configured to collect an error information about an error event in the first functional circuit, store the error information in a register of the first leaf node, and transmit the error information to the first root node, and wherein the first leaf node or the first root node is configured to perform event masking for the error event (¶0011 & ¶0051); and
a distribution network including a second tree having a second root node coupled to the first root node and to a second functional circuit in the second subsystem, wherein the second root node is configured to receive the error information from the first root node and to distribute the error information to the second functional circuit to perform an action corresponding to the error information (¶0138 & ¶0098).
Allowable Subject Matter
Claims 3, 5-7, 13-15, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art Golash (US 10,169,133) discloses a method for debugging network nodes that may include (1) detecting a computing event that is indicative of a networking malfunction within a network node, (2) determining, based at least in part on the computing event, one or more potential causes of the networking malfunction, (3) identifying one or more debugging templates that each define debugging steps that, when performed by a computing system, enable the computing system to determine whether the networking malfunction resulted from any of the potential causes, (4) performing a set of debugging steps defined by one of the debugging templates that corresponds to one of the potential causes, and then (5) determining, based at least in part on the set of debugging steps defined by the debugging template, that the networking malfunction resulted from the potential cause (Abstract).
Prior art Blumrich (US 8,667,049) discloses a global combining tree network, interconnecting compute nodes in a tree structure and including global signals and external network connections. Included in the tree is an associated I/O processing node that is connected through the Global Combining Tree to a predetermined number of compute nodes. One I/O node is dedicated to providing service and I/O operations for compute nodes. The packaging design enables alternate configurations such that the ratio of computation nodes to service nodes may change depending on requirements of the parallel calculations (column 13, lines 2-16).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES EHNE whose telephone number is (571)272-2471. The examiner can normally be reached 8:00-5:00 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES EHNE/ Primary Examiner, Art Unit 2113