DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo (US 9030244).
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With respect to claim 1, Luo produces a memory system (per column 1 lines 20-25 give the example of the DDR memory interface), comprising: one or more memory devices (configuration memory elements per claim 17 having input coupled to the calibration control circuitry and output coupled to the tuning circuit) (see also col. 3 lines 15-26 “Signals received from external circuitry at input-output elements 110 may be routed from input-output elements 110 to core logic region 115 or other logic blocks (not shown) on IC 100. Core logic region 115 may be populated with logic cells that may include "logic elements" (LEs) 117, among other circuits. In one embodiment, LEs 117 may include look-up table-based logic regions and may be grouped into "Logic Array Blocks" (LABs). LEs 117 and groups of LEs or LABs may be configured to perform specific user functions. Configuration data loaded into configuration memory (not shown) may be used to produce control signals that configure LEs 117 and groups of LEs and LABs to perform the desired user functions. Core logic region 115 may therefore perform logical functions based on the signals received.”); and one or more controllers (calibration control 370/380) coupled with the one or more memory devices and configured to cause the memory system to: determine whether (assert or de-assert) an autonomous duty cycle calibration mode (CAL-EN) of the memory system is enabled by accessing a bit (i.e. R3 or R2) stored to a set feature address register (calibration circuitry, Here logic elements are the specific set feature, see fig. 1. In particular in figure 3, calibration circuitry is the “set feature address register wherein bits R1 and R2 and R3 are stored), the bit comprising an enable bit or a disable bit (bit R3; per Col. 6 lines 5-25 “ In one embodiment, R3 may be a RAM control bit that enables and disables comparator circuit 330 for offset calibration”); and perform, in accordance with determine that the autonomous duty cycle calibration mode is enabled (see Col. 6 lines 5-25 “R3 may store an asserted enable signal when comparator circuit 330 is placed in calibration mode”), one or more duty cycle calibration operations during a boot sequence (here boot sequence is interpreted as an open ended period of the start-up of the machine. Since boot sequence is defined as “the series of steps a computer follows to initialize hardware and load the operating system when powered on or restarted” and calibration is an initialization operation, the calibration mode is interpreted as occurring during the boot sequence) of the memory system, wherein determining that autonomous duty cycle calibration mode is enabled is based on the enable bit (bit R3) being set in the set feature address register. (col. 6, per lines 5-25 “ In one embodiment, R3 may be a RAM control bit that enables and disables comparator circuit 330 for offset calibration”); Col. 5 lines 41-60 “Tuning circuit 310 will calibrate or adjust the clock signals CLK and CLKB incrementally until the duty cycle of the adjusted output clock signals CLK-O and CLKB-O is balanced (or as close as possible to 50%). In one embodiment, the calibration stops when the output INC of comparator circuit 330 switches from a logic high level to a logic low level. As shown in FIG. 3, control logic 380 may be used to monitor the toggling of the output signal INC. Control logic 380 may output an asserted enable signal CAL-EN that enables tuning calibration circuit 350 in calibration control circuitry 370 to update calibration offset RAM bits R1. Accordingly, when INC toggles from the logic high level to the logic low level, indicating that the previous calibration made to the clock signal CLK (and clock signal CLKB) is as close as possible to a 50% duty cycle, control logic 380 may de-assert CAL-EN. When CAL-EN is de-asserted, tuning calibration circuit 350 may "lock" the calibration offset RAM bits R1 so that tuning circuit 310 may apply the appropriate offset value to the clock signals CLK and CLKB to produce the respective adjusted clock signals CLK-O and CLKB-O.”)
With respect to claim 2, Luo produces the memory system of claim 1, wherein the one or more controllers (370) are further configured to cause the memory system to: receive, from a host system (380) a set feature command (INC) for the memory system (col. 5 lines 7-16 “The output of comparator circuit 330, INC, is transmitted to tuning calibration circuit 350 in calibration control circuitry 370. Tuning calibration circuit 350 may accumulate incremental value of INC to generate the calibration RAM bits R1. …. A total of five bits are used to set the calibration RAM bits R1.”), wherein determining whether the autonomous duty cycle calibration mode is enabled is based at least in part on the command (col. 5 lines 7-16 “Tuning circuit 310 in turn calibrates the clock signal CLK and the CLB clock signal based on the tuning bits DC-TUNE[0-4] from calibration RAM bits R1.”).
With respect to claim 3, Luo produces the memory system of claim 2, wherein receiving the command comprises the one or more controllers configured to cause the memory system to: receive, from the one or more controllers associated with the memory system, or from the host system (380), or both, an autonomous duty cycle calibration mode enable command (col. 5 lines 48 -51, “Control logic 380 may output an asserted enable signal CAL-EN that enables tuning calibration circuit 350 in calibration control circuitry 370 to update calibration offset RAM bits R1.”).
With respect to claim 4, Luo produces the memory system of claim 1, wherein determining whether the autonomous duty cycle calibration mode is enabled (see Col. 5 lines 48-51 “Control logic 380 may output an asserted enable signal CAL_EN that enables tuning calibration circuit 350 in calibration control circuitry 370 to update calibration offset RAM bits R1.”) is based at least in part on a power-on sequence for the memory system. (Here, col. 1 lines 14-25, discloses synchronous devices require a clock signal to operate. “Circuits that are designed to operate with a clock signal (commonly referred to as synchronous circuits) are generally activated at the rising or falling edge of the clock signal.” Thus as interpreted here, the rising or falling edge activation of the device by the clock signal is seen as part of the power-on sequence for the memory system and the duty cycle calibration enablement is based on the power-on sequence.)
With respect to claim 5, Luo produces the memory system of claim 1, wherein the one or more controllers (370/380) are further configured to cause the memory system to: adjust, during the boot sequence (Here, boot sequence is interpreted as an open ended period of the start-up of the machine. Since boot sequence is defined as “the series of steps a computer follows to initialize hardware and load the operating system when powered on or restarted” and calibration is an initialization operation, the calibration mode is interpreted as occurring during the boot sequence) and based at least in part on performing the one or more duty cycle calibration operations (from 300), a trim value (tuning bits DC TUNE[0:4]) associated with the one or more duty cycle calibration operations.
With respect to claim 6, Luo produces the memory system of claim 1, wherein the one or more controllers (370/380) are further configured to cause the memory system to: monitor (via feedback and control logic col. 5, lines 45-50 “control logic 380 may be used to monitor the toggling of the output signal INC.”), based at least in part on performing the one or more duty cycle calibration operations, one or more duty cycle calibration parameters (col 4, lines 49-62 “The difference between ERR and ERRB represents the ratio of the duty cycle distortion in the clock signal CLK-O.”) of the memory system; the one or more duty cycle calibration parameters comprising a duration associated with one or more continuous read clocks (system clock signal) or a quantity of clock cycles associated with one or more continuous read clocks; compare (via 330) the one or more duty cycle calibration parameters with a duty cycle calibration condition; and determine, based at least in part on the comparison of the one or more duty cycle calibration parameters with the duty cycle calibration condition, whether to perform one or more second duty cycle calibration operations during a second idle period of the memory system (Col. 4 lines 61-68- col.5 lines 1-7 “Depending on the values of ERR and ERRB, comparator circuit 330 may set its output, INC, to either a logic high level or a logic low level. The respective voltage levels of ERR and ERRB indicate whether the duty cycle of the clock signal CLK is greater or less than 50%. For example, when the duty cycle of the clock signal CLK is above 50%, ERR may be at a higher voltage level than ERRB and when the duty cycle is below 50%, ERR may be at a lower voltage level than ERRB. A clock signal with a balanced duty cycle (50% duty cycle) may produce equal ERR and ERRB value.”).
With respect to claim 7, Luo produces the memory system of claim 6, wherein the one or more controllers (370/380) are further configured to cause the memory system to: perform, based at least in part on the one or more duty cycle calibration parameters (ERR and ERRB) satisfying the duty cycle calibration condition (not balanced or close as possible to 50% duty cycle), the one or more second duty cycle calibration operations during the second idle period of the memory system.
With respect to claim 8, Luo produces the memory system of claim 6, wherein the one or more controllers (370/380) are further configured to cause the memory system to: refrain from performing, based at least in part on the one or more duty cycle calibration parameters failing to satisfy the duty cycle calibration condition (not balanced or close as possible to 50% duty cycle), the one or more second duty cycle calibration operations during the second idle period of the memory system (if the parameter is 50% duty cycle the system does not increment.)
With respect to claim 10, Luo produces the memory system of claim 1, wherein a duty cycle calibration parameter (ERR and ERRB) of the one or more duty cycle calibration parameters (ERR and ERRB) comprises a quantity of cycles (this is inherent with the calculation of the duty cycle distortion for a given number of cycles) associated with one or more continuous read clocks of the memory system.
With respect to claim 11, Luo produces the memory system of claim 1, wherein a duty cycle calibration parameter (ERR and ERRB) of the one or more duty cycle calibration parameters comprises a mode (Calibration enable mode) of the memory system.
With respect to claim 12, Luo discloses a method, comprising: determining whether (CAL-EN) an autonomous duty cycle calibration mode of a memory system is enabled by accessing a bit (R3 or R2) stored to a set feature address register (Here logic elements are the specific set feature, see fig. 1. In particular in figure 3, calibration circuitry is the “set feature address register wherein bits R1 and R2 and R3 are stored); (see Col. 6 lines 5-25 per column 5-25 “ In one embodiment, R3 may be a RAM control bit that enables and disables comparator circuit 330 for offset calibration”); ), the bit comprising an enable bit or a disable bit; and performing, in accordance with determining that the autonomous duty cycle calibration mode is enabled, one or more duty cycle calibration operations during a boot sequence (here boot sequence is interpreted as an open ended period of the start-up of the machine) of the memory system, wherein determining that the autonomous duty cycle calibration mode is enabled based on the enable bit (bit R3) being set in the set feature address register.
With respect to claim 13, Luo discloses the method of claim 12, further comprising: receiving, from a host system (380) a set feature command (i.e. inc) for the memory system (col 3, lines 21-26 “Configuration data loaded into configuration memory (not shown) may be used to produce control signals that configure LEs 117 and groups of LEs and LABs to perform the desired user functions.”). , wherein determining whether the autonomous duty cycle calibration mode is enabled is based at least in part on receiving the command.
With respect to claim 14, Luo discloses the method of claim 13, wherein receiving the command comprises: receiving, from one or more controllers (370/ ) associated with the memory system or from the host system (380) , an autonomous duty cycle calibration mode enable command (CAL-EN). (col. 5 lines 48 -51, “Control logic 380 may output an asserted enable signal CAL-EN that enables tuning calibration circuit 350 in calibration control circuitry 370 to update calibration offset RAM bits R1.”).
With respect to claim 15, Luo discloses the method of claim 12, wherein determining whether the autonomous duty cycle calibration mode is enabled is based at least in part on a power-on sequence for the memory system (Here, col. 1 lines 14-25, discloses synchronous devices require a clock signal to operate. “Circuits that are designed to operate with a clock signal (commonly referred to as synchronous circuits) are generally activated at the rising or falling edge of the clock signal.” Thus as interpreted here, the rising or falling edge activation of the device by the clock signal is seen as part of the power-on sequence for the memory system and the duty cycle calibration enablement is based on the power-on sequence.)
With respect to claim 16, Luo discloses the method of claim 12, further comprising: adjusting, during the boot sequence (here boot sequence is interpreted as an open ended period of the start-up of the machine) and based at least in part on performing the one or more duty cycle calibration operations (from 300), a trim value (tuning bits DC TUNE[0:4]) associated with the one or more duty cycle calibration operations.
With respect to claim 17, Luo discloses the method of claim 12, further comprising: monitoring (via feedback and control logic col. 5, lines 45-50 “control logic 380 may be used to monitor the toggling of the output signal INC.”), based at least in part on performing the one or more duty cycle calibration operations, one or more duty cycle calibration parameters (col 4, lines 49-62 “The difference between ERR and ERRB represents the ratio of the duty cycle distortion in the clock signal CLK-O.”) of the memory system, the one or more duty cycle calibration parameters comprising a duration associated with one or more continuous read clocks (system clock) or a quantity of clock cycles associated with one or more continuous read clocks; comparing (via 330) the one or more duty cycle calibration parameters with the duty cycle calibration condition; and determining, based at least in part on comparing the one or more duty cycle calibration parameters with the duty cycle calibration condition, whether to perform one or more second duty cycle calibration operations during a second idle period of the memory system (Col. 4 lines 61-68- col.5 lines 1-7 “Depending on the values of ERR and ERRB, comparator circuit 330 may set its output, INC, to either a logic high level or a logic low level. The respective voltage levels of ERR and ERRB indicate whether the duty cycle of the clock signal CLK is greater or less than 50%. For example, when the duty cycle of the clock signal CLK is above 50%, ERR may be at a higher voltage level than ERRB and when the duty cycle is below 50%, ERR may be at a lower voltage level than ERRB. A clock signal with a balanced duty cycle (50% duty cycle) may produce equal ERR and ERRB value.”).
With respect to claim 18, Luo discloses the method of claim 17, further comprising: performing, based at least in part on the one or more duty cycle calibration parameters (ERR and ERRB) satisfying the duty cycle calibration condition (not balanced or close as possible to 50% duty cycle),, the one or more second duty cycle calibration operations during the second idle period of the memory system.
With respect to claim 19, Luo discloses the method of claim 17, further comprising: refraining from performing, based at least in part on the one or more duty cycle calibration parameters failing to satisfy the duty cycle calibration condition (not balanced or close as possible to 50% duty cycle), the one or more second duty cycle calibration operations during the second idle period of the memory system (if the parameter is 50% duty cycle the system does not increment.)
With respect to claim 20, Luo discloses a non-transitory computer-readable medium (col 3, lines 21-26 “Configuration data loaded into configuration memory (not shown) may be used to produce control signals that configure LEs 117 and groups of LEs and LABs to perform the desired user functions.”) storing code, the code comprising instructions executable by one or more processors to: determine whether an autonomous duty cycle calibration mode (CAL -EN) of a memory system is enabled by accessing a bit (R3 or R2) stored to a set feature address register (Here logic elements are the specific set feature, see fig. 1. In particular in figure 3, calibration circuitry is the “set feature address register wherein bits R1 and R2 and R3 are stored), the bit comprising an enable bit or a disable bit (Col. 6, lines 5-25 “In one embodiment, R3 may be a RAM control bit that enables and disables comparator circuit 330 for offset calibration”); and perform, in accordance with determining that the autonomous duty cycle calibration mode is enabled (see Col. 5 lines 48-51 “Control logic 380 may output an asserted enable signal CAL_EN that enables tuning calibration circuit 350 in calibration control circuitry 370 to update calibration offset RAM bits R1.”) one or more duty cycle calibration operations during a boot sequence (here boot sequence is interpreted as an open ended period of the start-up of the machine) of the memory system, wherein determining that the autonomous duty cycle calibration mode is enabled is based on the enable bit (bit R3) being set in the set feature address register (Here logic elements are the specific set feature, see fig. 1. In particular in figure 3, calibration circuitry is the “set feature address register wherein bits R1 and R2 and R3 are stored). (Col. 6 lines 5-25 “ In one embodiment, R3 may be a RAM control bit that enables and disables comparator circuit 330 for offset calibration.” Col. 5 lines 41-60 “Tuning circuit 310 will calibrate or adjust the clock signals CLK and CLKB incrementally until the duty cycle of the adjusted output clock signals CLK-O and CLKB-O is balanced (or as close as possible to 50%). In one embodiment, the calibration stops when the output INC of comparator circuit 330 switches from a logic high level to a logic low level. As shown in FIG. 3, control logic 380 may be used to monitor the toggling of the output signal INC. Control logic 380 may output an asserted enable signal CAL-EN that enables tuning calibration circuit 350 in calibration control circuitry 370 to update calibration offset RAM bits R1. Accordingly, when INC toggles from the logic high level to the logic low level, indicating that the previous calibration made to the clock signal CLK (and clock signal CLKB) is as close as possible to a 50% duty cycle, control logic 380 may deassert CAL-EN. When CAL-EN is deasserted, tuning calibration circuit 350 may "lock" the calibration offset RAM bits R1 so that tuning circuit 310 may apply the appropriate offset value to the clock signals CLK and CLKB to produce the respective adjusted clock signals CLK-O and CLKB-O.”)
Response to Arguments
Applicant's arguments filed 6/11/2026 have been fully considered but they are not persuasive.
Initially Applicant argues “by accessing a bit stored to a set feature address register” and “based on the enable bit being set in the set feature address register” are not found in Luo, the Examiner disagrees. (Bits R1, R2 and R3 are stored in set feature address register “i.e. calibration circuitry” and based on the enable bit being set in the set feature address register is found as the output of the calibration circuitry is sent to the command which then sends the signal to enable via calibration control and is interpreted as reading on this feature.
Applicant argues R2 and R3 bits of Luo cannot be relied to teach or suggest the bit “stored to a feature address register”. The Examiner points out the Logic Elements (col. 3 lines 15-21 “Core logic region 115 may be populated with logic cells that may include "logic elements" (LEs) 117, among other circuits. In one embodiment, LEs 117 may include look-up table-based logic regions and may be grouped into "Logic Array Blocks" (LABs). LEs 117 and groups of LEs or LABs may be configured to perform specific user functions.” Applicant argues that R2 and R3 are not bits stored on a set feature address register. The set feature address register would be the calibration circuitry having Logic elements. Depicted in fig. 3 the specific set feature is calibration. As seen in fig. 3, the R3 and R2 are stored on the calibration circuitry which is interpreted as the specific set feature address register. Since R3 and R2 allow for enabling and disabling these are the bits stored to the set feature address register. The feedback going to the control logic sets the basis of the determining that autonomous cycle calibration mode.
With respect to claims 2 and 13, the receiving from a host system, a set feature command, (the host system in interpreted as 380), and thus is interpreted as producing a set feature command from the host system. R1 and R2 and R3, are internally set by the circuit based on 380, wherein 380 is interpreted as the host system that sets the feature command. As such, Luo is interpreted on reading on the alleged discrepancies cited by the Applicant.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2836
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