DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicants' arguments filed 02/26/2026 have been fully considered but they are not persuasive.
With respect to the Rejection under 35 U.S.C 103 based on WAELDE as modified by Heide, the Applicant states that the prior art does not teach or disclose “wherein the first structure size is different from the second structure size, and/or wherein the first semiconductor technology is different from the second semiconductor technology, “as recited by independent claim 1. The Examiner disagrees and maintains the art rejection.
In support of the above argument the Applicant further argues that although Heide describes that some semiconductor technologies may be used, Heide does not disclose a first semiconductor technology (of the first ASIC) being different from a second semiconductor technology (of the second ASIC). The Examiner respectfully disagrees. Heide discloses the use of one or more “individual electronic components” on paragraph [0015]. Paragraphs [0025] and [0027] further disclose that each individual electronic component may be either a microwave chip, a millimeter wave chip or an IC element (IC=Integrated Circuit). As was set forth in the previous action, paragraph [0028] discloses, “active individual components can, for example, be constructed using Si, SiGe, GaAs or InP semiconductor
Technology.” Paragraph [0028] does not disclose that each active individual component must utilize the same semiconductor technology, but simply that each component may be constructed from a semiconductor technology provided by the aforementioned list. Paragraphs [0015], [0025], [0027], and [0028] clearly suggest that each individual electronic component may utilize a separate semiconductor technology. The Examiner maintains the art rejection.
The Applicant further argues that Heide fails to teach, “that the first ASIC has a first structure size and an operating range in the megahertz range and the second ASIC has a second structure size (which is different from the first structure size) and an operating range of at least 6 GHz.” Although the Applicant fails to provide evidence or support for this position, the Examiner points to the previously filled non final rejection and reminds the Applicant that Heide was not relied upon exclusively to teach the subject matter recited in the above limitation. Paragraph [0030] and [0065] of WAELDE disclose the use of two different ASIC’s, one operating at above 6GHz and the other operating in the megahertz range. Figure 4 of Heide clearly depicts the use of multiple integrated circuits of different structure sizes [FIG.4, Parts.OSZ-IC & Mix1]. As the Applicant fails to set forth any argument otherwise the Examiner maintains the art rejection.
The Applicant additionally argues that it would not have been obvious to combine WAELDE and Heide stating that “the Office Action does not address either the required motivation or the required reasonable expectation of success that a person of ordinary skill in the art must have had in order to have considered the asserted combination of references” and that “it would have been necessary for the person of ordinary skill in the art to make highly specific, nonobvious selections of, and adaptations to, features from these references. This is too much to ask of the hypothetical person of ordinary skill in the art.” As with the Applicant’s above argument, these remarks are unsupported by reasoning particular to the instant application or with any relevant evidence. With respect to the Applicant's statement that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). The Examiner acknowledges the Applicant’s statement found on Pages 7 and 8 of the Remarks that preface the above argument stating, “The Examiner’s assertations are a classic example of improper use of hindsight benefit of the Applicant’s claimed invention in the absence of any reasonable motivation from within the cited references [emph.] for the person of ordinary skill in the art to have considered their combination.” Page 4 of the previously filled nonfinal rejection clearly sets forth the Examiner’s “required motivation” of which explicitly relies upon knowledge sourced from Heide(US20060097906A1) published 05/11/2006, preceding the earliest date granted to the instant application. Accordingly, the Examiner does not find support for this argument and points to the OA dated 11/26/2025.
Further, Examiner reminds the Applicant of the explicit claim language evoking the 35 U.S.C. 103 rejection. Of independent claim 1, WAELDE as modified by Heide are relied upon to teach, “wherein the first structure size is different from the second structure size, and/or wherein the first semiconductor technology is different from the second semiconductor technology.” The Applicants specification does not provide a special definition for the claimed “semiconductor technology,” simply leaving the term generally recited. The breadth of “semiconductor technology” may include any technological difference including changes in material, shape, generic semiconductor properties, or manufacturing process. MPEP 2144.04(IV)(A) explicitly demonstrates that that changes in size, shape, or “sequence of adding ingredients” of a component is obvious modifications. As the limitations simply recite two ASICs of different size and different generic semiconductor technology, it would not have been “necessary for the person of ordinary skill in the art to make highly specific, nonobvious selections of, and adaptations to, features from these references.” It is further noted that the test for obviousness is not whether the features of one reference may be bodily incorporated into the other to produce the claimed subject matter but simply what the combination of references makes obvious to one of ordinary skill in the pertinent art. In re Bozek, 163 USPQ 545 (CCPA 1969). The Examiner maintains WAELDE as modified by Heide make obvious to one of ordinary skill in the art two ASICs of different size and different generic semiconductor technology.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-11, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over WAELDE(US20190107427A1) in view of Heide(US20060097906A1).
Regarding claim 1, WAELDE discloses
A radar circuit for a level measuring device (“a radar fill level measurement device” [0052]), comprising: a first application-specific integrated circuit (ASIC) (“The analysis unit may be […] an ASIC” [0116]); and a second ASIC (“a monolithic microwave integrated circuit (MMIC) may be provided” [0005]), wherein the first ASIC has a first structure size and an operating range in the megahertz range(“The HF bandwidth of the transmission signals may be in the range between several hundred megahertz and four (or more) gigahertz” [0065]). and/or is manufactured by a first semiconductor technology (FIG.3, Part.310), wherein the second ASIC has a second structure size and an operating range of at least 6 GHz (“the radar chips are based on HF CMOS technology and comprise high-frequency circuit parts for frequencies of 75 GHz and above.” [0030]) and/or is manufactured by a second semiconductor technology (FIG.3, Part.301),
WAELDE discloses the use of a first and second ASIC, but does not appear to explicitly disclose wherein the ASICs are of a different size or semiconductor technology. Heide discloses, wherein the first structure size is different from the second structure size (FIG.4, Parts.OSZ-IC & Mix1 & “The mixer can be (at least partially) present as an integrated circuit. The circuits of the mixer, the oscillator and the frequency divider can generally be present as single chip, two chip or three chip solutions” [0066]), and/or wherein the first semiconductor technology is different from the second semiconductor technology (“The active individual components can, for example, be constructed using Si, SiGe, GaAs or InP semiconductor technology.” [0028]).
Heide teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify WAELDE with the teachings of Heide to incorporate the features of ASIC’s being of a different size or semiconductor technology so as to gain the advantage of reducing system size ([0008], Heide) . Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 2, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the second ASIC has an operating range of one of 24 GHz, 60 GHz, 80 GHz, 120 GHz, 180 GHz, or 240 GHz, or higher (“the radar chips are based on HF CMOS technology and comprise high-frequency circuit parts for frequencies of 75 GHz and above.” [0030])
Regarding claim 3, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the second ASIC is a monolithic microwave integrated circuit (MMIC) (“a monolithic microwave integrated circuit (MMIC) may be provided” [0005]).
Regarding claim 6, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE
discloses the radar circuit wherein, the first ASIC and the second ASIC are arranged one above the other, stacked, or overlapping each other (fig.5, Parts. FPGA&301b).
Regarding claim 7, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the first ASIC is arranged on a carrier plate (“FIG. 11A is a cross section of a circuit board comprising radar chips” [0048])
WAELDE does not appear to explicitly disclose wherein the second ASIC is arranged on the first ASIC. Heide discloses, wherein the second ASIC is arranged on the first ASIC (fig.2, Parts. CB&IE).
Heide teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify WAELDE with the teachings of Heide to incorporate the features of the second ASIC being arranged on the first ASIC so as to gain the advantage of reducing environmental system effects ([0067], Heide) . Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 8, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit further comprising, a carrier plate (“FIG. 11A is a cross section of a circuit board comprising radar chips” [0048]), wherein the second ASIC is arranged on or in a recess of the carrier plate (“The radar chips are positioned on a face (or plane) 801, 802 of the circuit board 904,” [0089]) and wherein the first ASIC is arranged on the second ASIC (fig.5, Parts. FPGA&301b).
Regarding claim 9, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE does not appear to explicitly disclose wherein the first ASIC has a metallization on an upper side thereof. Heide discloses the radar circuit wherein, the first ASIC has a metallization on an upper side thereof as a reflector configured to reflect the radar measurement signals generated by the second ASIC (“a substrate with at least two dielectric layers located directly on top of each other, in which metallized surfaces are placed on top of, below and between the dielectric layers” [0014], & FIG.2, Part.IE).
Heide teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify WAELDE with the teachings of Heide to incorporate the features of the first ASIC having a metallization on an upper side thereof so as to gain the advantage of reducing improving shielding ([0069], Heide) . Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 10, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the carrier plate has a metallization as a reflector below the first ASIC configured to reflect the radar measurement signals generated by the second ASIC (“The outer layers 801, 809 are metallized layers” [0091] & (fig.5, Parts. FPGA&301b)).
Regarding claim 11, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit further comprising: a carrier plate (“FIG. 11A is a cross section of a circuit board comprising radar chips” [0048]); and a primary radiator (FIG.4, Part.303), arranged to emit the radar measurement signal generated by the second ASIC (FIG.3, Part.301), which is arranged on the second ASIC or on the carrier plate (fig.5, Parts. FPGA&301b).
Regarding claim 13, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the first ASIC is arranged to supply a voltage-controlled oscillator (VCO) of the second ASIC and/or a multiplier of the second ASIC (“the following are integrated: PLL, VCO” [0061]).
Regarding claim 14, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the first ASIC and the second ASIC are separate components (FIG.3, Parts.310 & 301).
Regarding claim 15, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the radar circuit is configured to be used in a radar level meter (“The invention relates to fill level measurement” [0002]).
Regarding claim 16, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses, A radar level meter comprising a radar circuit according to claim 1 (“The invention relates to fill level measurement” [0002] & FIG.1B). (“The invention relates to fill level measurement” [0002])
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over WAELDE(US20190107427A1) as modified by Heide(US20060097906A1) as applied to claim 1 above, and further in view of Giannini (US20170115377A1).
Regarding claim 5, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE as modified by Heide does not appear to explicitly disclose a first structure size being smaller than 50 nm. Giannini discloses the radar circuit wherein, the first structure size is smaller than 50 nm (“A test device was fabricated using a CMOS 45 nm technology” [0029]).
Giannini teaches in the same field of endeavor of radar integrated circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify WAELDE as modified by Heide with the teachings of Giannini to incorporate the features of first structure size being smaller than 50 nm so as to gain the advantage of reducing radar system size. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 12, WAELDE as modified by Heide disclose all the limitations of claim 1. WAELDE discloses the radar circuit wherein, the first ASIC comprises a phase locked loop (PLL), an analog-to-digital converter (ADC) circuit (“the following are integrated: PLL… ADC’s”[0061]), […], and/or a digital interface to a processor of the radar circuit (“a digital interface” [0063]).
WAELDE as modified by Heide does not appear to explicitly disclose a finite state machine. Giannini discloses the radar circuit wherein, the first ASIC comprises […] a finite state machine (FSM) (“A BIST Sub-System Finite-State-Machine (FSM) 147” [0018]).
Giannini teaches in the same field of endeavor of radar integrated circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify WAELDE as modified by Heide with the teachings of Giannini to incorporate the features of a finite state machine so as to gain the advantage of simplifying system design ([0018], Giannini). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Documents Considered but not Relied Upon
The prior art made of record and not relied upon is considered pertinent to the applicant’s Disclosure.
WELLE(US20200333176A1) is considered analogous art to the instant application as it discloses in [0048] “using GaAs MMICs with inherently low inherent noise and high emitted power, even the smallest reflection signals can be reliably processed.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CLAYTON PAUL RIDDER whose telephone number is (571)272-2771. The examiner can normally be reached Monday thru Friday ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Keith can be reached on (571) 272-6878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.P.R./Examiner, Art Unit 3646
/JACK W KEITH/Supervisory Patent Examiner, Art Unit 3646
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