DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species Embodiment 1, with corresponding claims 1-5, 7-14, and 16-17, in the reply filed on 06/05/2026 is acknowledged. Claims 6, 15, and 18-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species Embodiments.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: PEDMOS TRANSISTOR DEVICES COMPRISING P-TYPE SILICON GERMANIUM DRIFT REGION BETWEEN P-TYPE SILICON DRIFT REGION AND P-TYPE SILICON GERMANIUM DRAIN REGION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Zhang et al. (US 2008/0197412 A1; hereinafter “Zhang”) in view of Chakravarthi et al. (US 2008/0242032 A1; hereinafter “Chakravarthi”).
Regarding claim 1, referring to Figs. 5-6, Zhang teaches a P-type extended drain metal-oxide-semiconductor (PEDMOS) field-effect transistor (FET) (a p-type transistor with source/drain extensions 25) including a Si active layer (a semiconductor region 16 formed of silicon) that includes:
(a) a Si channel region (a channel region of 16 between source/drain extensions 25 and 27) having a source-side edge (a left-side of the channel region of 16 facing 25) and a drain-side edge (a right-side of the channel region of 16 facing 27) (paragraphs 4 and 14-15);
(b) a P+ SiGe source region (a high concentration boron-doped SiGe layer 40) adjacent the source-side edge of the channel region (paragraphs 18 and 20);
(c) a first Si drift region (a drain extension 27 by implanting a region of 16 formed of silicon) having a first side (a left-side of 27) adjacent the drain-side edge of the channel region, and having a second side (a right-side of 27) (paragraph 15);
(d) a second P− SiGe drift region (a low level concentration boron-doped SiGe layer 34 and/or a medium level concentration boron-doped SiGe layer 38) having a first side (a left-side of 34/38) adjacent the second side of the first Si drift region, and having a second side (a right-side of 34/38) (paragraphs 16-17); and
(e) a P+ SiGe drain region (a high level concentration boron-doped SiGe layer 42) adjacent the second side of the second P− SiGe drift region (paragraphs 18 and 20).
While Zhang does not further teach that the Si channel region is an N-type and the first Si drift region is a P-type, it is well known in the art that the p-type transistor would include an n-type channel region and a lightly doped p-type drain drift region. This is evidenced by Chakravarthi teaching a p-type extended drain MOS transistor (a PMOS region 60 with extended source/drain extensions 70), including a n-type channel region (a n-type channel region of 120 between source/drain extensions 70) and a p-type drift layer (a lightly doped p-type drain extension 70) (Fig. 1 and paragraphs 5-8). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Zhang with that of Chakravarthi in order to provide the predictable n-type channel region and the lightly doped p-type drift region for the p-type transistor.
Regarding claim 2, Zhang teaches wherein the active layer is formed on a buried-oxide insulator layer (14) (paragraph 15).
Regarding claim 3, Zhang teaches wherein the buried-oxide insulator layer is formed on a substrate (12) (paragraph 15).
Regarding claim 4, Zhang in view of Chakravarthi teaches wherein the P+ SiGe source region and the second P− SiGe drift region are shaped to compress the N-type Si channel region (Zhang, a shape of 40 and 34/38 with a channel region therebetween as shown in Fig. 5 and Chakravarthi for the n-type channel region).
Regarding claim 5, Zhang in view of Chakravarthi teaches wherein the P+ SiGe source region has a rounded shape adjacent the source-side edge of the N-type channel region and the second P− SiGe drift region has a rounded shape adjacent the drain-side edge of the N-type channel region (See Zhang, Fig. 5 for the rounded shape and Chakravarthi for the n-type channel region).
Regarding claim 7, Zhang teaches wherein the Si active layer further includes a doped halo region (paragraph 15 describes “Semiconductor region 16 in this described example is just silicon, as the semiconductor material, that may have background doping and other dopings such as a halo implant”). While Zhang does not explicitly show where the halo implant region is located, it would have been obvious to one of ordinary skill in the art that the halo implant region is located between the P+ SiGe source region and the N-type Si channel region as claimed for improving transistor functionality.
Regarding claim 8, Zhang in view of Chakravarthi teaches wherein the Si active layer further includes a lightly-doped drain region (25) between the P+ SiGe source region (40) and the N-type Si channel region (Zhang, Fig. 5 and paragraph 15 and Chakravarthi for the n-type channel region).
Regarding claim 9, while Zhang does not further teach the Si active layer having a <110> orientation, it would have been obvious to one of ordinary skill in the art that the Si active layer (16) from Zhang would have (110) surface orientation for improving hole mobility for the p-type transistor.
Claims 10-14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Zhang in view of Chakravarthi and Cheng et al. (US 2023/0099156 A1; hereinafter “Cheng”).
Regarding claim 10, referring to Figs. 5-6, Zhang teaches an integrated circuit fabricated on a substrate and including:
(a) a Si active layer (a semiconductor region 16 formed of silicon) (paragraphs 4 and 14-15) and which includes:
(1) a Si channel region (a channel region of 16 between source/drain extensions 25 and 27) having a source-side edge (a left-side of the channel region of 16 facing 25) and a drain-side edge (a right-side of the channel region of 16 facing 27) (paragraphs 4 and 14-15);
(2) a P+ SiGe source region (a high concentration boron-doped SiGe layer 40) adjacent the source-side edge of the channel region (paragraphs 18 and 20);
(3) a first Si drift region (a drain extension 27 by implanting a region of 16 formed of silicon) having a first side (a left-side of 27) adjacent the drain-side edge of the channel region, and having a second side (a right-side of 27) (paragraph 15);
(4) a second P− SiGe drift region (a low level concentration boron-doped SiGe layer 34 and/or a medium level concentration boron-doped SiGe layer 38) having a first side (a left-side of 34/38) adjacent the second side of the first Si drift region , and having a second side (a right-side of 34/38) (paragraphs 16-17);
(5) a P+ SiGe drain region (a high level concentration boron-doped SiGe layer 42) adjacent the second side of the second P− SiGe drift region (paragraphs 18 and 20); and
(b) a gate structure (a gate structure including at least a gate 22 and a gate dielectric 20) overlying the Si channel region (paragraph 15).
Zhang does not further teach that 1) the Si channel region is an N-type and the first Si drift region is a P-type and 2) the Si active layer has a <110> orientation.
Regarding 1) the Si channel region is an N-type and the first Si drift region is a P-type and 2) the Si active layer, it is well known in the art that the p-type transistor would include an n-type channel region and a lightly doped p-type drain drift region. This is evidenced by Chakravarthi teaching a p-type extended drain MOS transistor (a PMOS region 60 with extended source/drain extensions 70), including a n-type channel region (a n-type channel region of 120 between source/drain extensions 70) and a p-type drift layer (a lightly doped p-type drain extension 70) (Fig. 1 and paragraphs 5-8). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Zhang with that of Chakravarthi in order to provide the predictable n-type channel region and the lightly doped p-type drift region for the p-type transistor.
Regarding 2) the Si active layer having a <110> orientation, Cheng teaches a p-type field-effect transistor (PFET) comprising (110) crystalline surface orientation for optimal electrical performance of the PFET (paragraph 24). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Zhang with that of Cheng in order to provide the optimal electrical performance of the PFET.
Regarding claim 11, Zhang teaches wherein the Si active layer is formed on a buried-oxide insulator layer (14) (paragraph 15).
Regarding claim 12, Zhang teaches wherein the buried-oxide insulator layer is formed on a substrate (12) (paragraph 15).
Regarding claim 13, Zhang in view of Chakravarthi teaches wherein the P+ SiGe source region and the second P− SiGe drift region are shaped to compress the N-type Si channel region (Zhang, a shape of 40 and 34/38 with a channel region therebetween as shown in Fig. 5 and Chakravarthi for the n-type channel region).
Regarding claim 14, Zhang in view of Chakravarthi teaches wherein the P+ SiGe source region has a rounded shape adjacent the source-side edge of the N-type channel region and the second P− SiGe drift region has a rounded shape adjacent the drain-side edge of the N-type channel region (See Zhang, Fig. 5 for the rounded shape and Chakravarthi for the n-type channel region).
Regarding claim 16, Zhang teaches wherein the Si active layer further includes a doped halo region (paragraph 15 describes “Semiconductor region 16 in this described example is just silicon, as the semiconductor material, that may have background doping and other dopings such as a halo implant”). While Zhang does not explicitly show where the halo implant region is located, it would have been obvious to one of ordinary skill in the art that the halo implant region is located between the P+ SiGe source region and the N-type Si channel region as claimed for improving transistor functionality.
Regarding claim 17, Zhang in view of Chakravarthi teaches wherein the Si active layer further includes a lightly-doped drain region (25) between the P+ SiGe source region (40) and the N-type Si channel region (Zhang, Fig. 5 and paragraph 15 and Chakravarthi for the n-type channel region).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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