DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
09/23/2025 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 03/05/2026. Claims 1,3-6, 8-11, 13-16, 18 and 20 are pending. Applicant’s arguments for 35 U.S.C. 112(a) rejection is considered and accepted. Rejection of U.S.C. 112(a) is hereby withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,3-4,6,8-11,13-14, 16,18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Paley et al. (US 20100172180 A1) in view of Parthasarathy et al. (US 20210103389 A1) further in view of Li et al. (US 20050237814 A1) and further in view of Rousseau et al. (US 20160098220 A1) hereinafter Paley and Parthasarathy and Li and Rousseau.
Regarding claim 1, Paley teaches A method, comprising: writing data stored in a first block to a second block; (“A second portion forms an optional cache for data in transit to the main memory”) (paragraph [0032] line 5) (i.e. a method is formed to store data in cache in transit to main memory. In other words, data is stored in cache memory in transit to main memory)
determining, based least in part on writing the data stored in the first block to the second block, whether to program the first block into a fully programmed state based at least in part on whether that the first block is storing the data in a partially programmed state; (“With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2)
(“the write is to main memory if the binary cache is in partial page mode only. The binary cache is in partial page mode when the volume of valid data in the cache is near (by a predefined amount) the cache capacity”) (paragraph [0228] line 1-3) (i.e. Fig 20A step 410 and 412 illustrate determination to find if binary cache is near full then write or program proceeds to main memory and it happens only when binary cache is in partial program page mode. In other words, when it is determined after examining cache memory is near full, data is programmed or stored in main memory when cache memory is in partially program mode)
the value of the second data indicates (“See Fig. 15, paragraph [0202], illustrates set of data management page by page in 1st memory 204)
maintaining, based at least in part on determining whether to program the first block, the first block in the fully programmed state until an erase operation is performed for the first block; and performing the erase operation for the first block. (“Cache compaction is enabled when unwritten capacity<=size of current data segment or when the unwritten capacity is less than 128 sectors”) (paragraph [0292] line 1-2)
(“All valid data from the selected block is copied in increasing LBA order to the cache write block, and the selected block is erased (or marked for erasure)”) (paragraph [0295] line 1-2) (i.e. Fig 23 illustrates when binary cache reaches unwritten capacity less than 128 sectors, all valid data from the selected block is copied and the selected block is erased. In other words, when binary cache is fully programmed and have capacity less than 128 sectors, it’s marked for erase)
Paley teaches partial programming management for memory devices. However, Paley does not explicitly teach reading a page of the first block, wherein the page of the first block stores second data
On the other hand, Parthasarathy which also relates to partial programming management for memory devices teaches reading a page of the first block, wherein the page of the first block stores second data (“See Fig. 2, paragraph [0030], illustrates controller 215 can issue read request to memory device 210)
Both Paley and Parthasarathy relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley with Parthasarathy by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Parthasarathy, to enable controller to issue read request to memory device. The combined system of Paley – Parthasarathy allows partially written blocks to reduce uncorrectable bit error rates (UBERs), reduce the number of corrective reads, and also reduce complexity associated with system controller as mentioned in paragraph [0013]. Therefore, the combination of Paley - Parthasarathy improves read performance of partially written blocks. See Parthasarathy, paragraph [0013].
Paley in view of Parthasarathy teaches partial programming management for memory devices. However, Paley - Parthasarathy combination does not explicitly teach and wherein a value of the second data that indicates whether the first block is storing the data in a partially programmed state
On the other hand, Li which also relates to partial programming management for memory devices teaches
and wherein a value of the second data that indicates whether the first block is storing the data in a partially programmed state (See Fig. 11A,11B paragraph [0108], illustrates flag bits are embedded in row of memory cells which are used to determine if page is partially or fully programmed where setting the flag bits are used to determine programming level)
Both Paley, Parthasarathy and Li relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, and see Li, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley - Parthasarathy combination with Li by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Parthasarathy, to enable flag bits are embedded in row of memory cells which are used to determine if page is partially or fully programmed where setting the flag bits are used to determine programming level. The combined system of Paley – Parthasarathy - Li allows improved partial page program capability as mentioned in paragraph [0001]. Therefore, the combination of Paley - Parthasarathy - Li improves read and program performance. See Li, paragraph [0038].
Paley in view of Parthasarathy and in view of Li further teaches partial programming management for memory devices. However, Paley - Parthasarathy combination does not explicitly teach invalidating, based at least in part on writing the data to the second block, the data stored in the first block;
and after the data stored in the first block is invalidated
On the other hand, Rousseau which also relates to partial programming management for memory devices teaches invalidating, based at least in part on writing the data to the second block, the data stored in the first block; (See Fig. 1,2 paragraph [0206], illustrates program VPG moves the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages)
and after the data stored in the first block is invalidated (See Fig. 1,2 paragraph [0206], illustrates after VPG moves valid descriptors to other page, source or first page is invalidated)
Both Paley, Parthasarathy, Li and Rousseau relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, and see Li, abstract, and see Rousseau, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley - Parthasarathy - Li combination with Rousseau by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Rousseau, to enable program VPG to move the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages. The combined system of Paley – Parthasarathy - Li - Rousseau allows as the memory space diminishes the invalid data are erased to free up memory space as mentioned in paragraph [0011]. Therefore, the combination of Paley - Parthasarathy - Li - Rousseau improves data write time and protect the data from tearing. See Rousseau, paragraph [0011].
Regarding claim 3, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 1. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 1, further comprising: determining that the first block is storing the data in the partially programmed state, wherein determining whether to program the first block comprises determining to program the first block into the fully programmed state based at least in part on determining that the first block is storing the data in the partially programmed state.
On the other hand, Paley which also relates to partial programming management for memory devices teaches The method of claim 1, further comprising: determining that the first block is storing the data in the partially programmed state, wherein determining whether to program the first block comprises determining to program the first block into the fully programmed state based at least in part on determining that the first block is storing the data in the partially programmed state. (“If the write is a partial page write, then it is always written to the binary cache”) (paragraph [0241] line 1)
(“FIG. 22B illustrates a second example a write that is sequential to the last sector of the logical group written to the binary cache”) (paragraph [0243] line 1-2)
(“STEP 412: With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2) (i.e. Fig 20A and 22B illustrate If the write is a partial page write then it is written to binary cache or first block that is sequential to the last sector of the logical group until it’s examined in step 412 if it’s nearly full or fully programmed)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 1 is equally applicable to claim 3.
Regarding claim 4, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 3. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 3, further comprising: programming, based at least in part on determining to program the first block in the fully programmed state, the first block to store third data that causes the first block to be in the fully programmed state
On the other hand, Li which also relates to partial programming management for memory devices teaches The method of claim 3, further comprising: programming, based at least in part on determining to program the first block in the fully programmed state, the first block to store third data that causes the first block to be in the fully programmed state. (See Fig. 11A,11B paragraph [0108], illustrates flag bits are embedded in row of memory cells which causes to determine if page is fully programmed where setting the flag bits are used to determine programming level)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 1 is equally applicable to claim 4.
Regarding claim 6, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 1. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 1, further comprising: determining that the first block is storing the data in the fully programmed state, wherein determining whether to program the first block comprises determining to maintain the first block into the fully programmed state
On the other hand, Paley which also relates to partial programming management for memory devices teaches The method of claim 1, further comprising: determining that the first block is storing the data in the fully programmed state, wherein determining whether to program the first block comprises determining to maintain the first block into the fully programmed state. (“If routed to the binary cache ("BC") portion, the data will be managed by a BC management module. new block may need to be allocated or obsolete blocks recycled in cooperation with an erase (free) metablock management module. A set of control data is generated and maintained during the various block manipulations and data storage into the blocks”) (paragraph [0202] line 7-11) (i.e. Binary cache data is managed by a BC management module and it may include new block in cooperation with an erase (free) metablock when a set of control data is generated and maintained during the various block manipulations. In other words, data is maintained in fully programmed state until block management manipulates various blocks)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 1 is equally applicable to claim 6.
Regarding claim 8, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 1. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 1, further comprising: invalidating, based at least in part on writing the data to the second block, the data stored in the first block; and designating the first block as free based at least in part on invalidating the data stored in the first block, wherein whether to program the first block into the fully programmed state is determined after the first block is designated as free
On the other hand, Paley which also relates to partial programming management for memory devices teaches The method of claim 1, further comprising: invalidating, based at least in part on writing the data to the second block, the data stored in the first block; and designating the first block as free based at least in part on invalidating the data stored in the first block, wherein whether to program the first block into the fully programmed state is determined after the first block is designated as free. (“The BC management module will have the data in units of ECC pages written into one or more subpages. In either case, new block may need to be allocated or obsolete blocks recycled in cooperation with an erase (free) metablock management module”) (paragraph [0202] line 7-9) (i.e. BC management module and metablock management module in Fig 17 will have the data where new block may need to be allocated or obsolete blocks recycled in cooperation with an erase to free up the blocks. In other words, data may be reallocated or erased from blocks to make it free for new programming)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 1 is equally applicable to claim 8.
Regarding claim 9, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 1. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 1, wherein, while in the partially programmed state, the first block comprises a first set of pages that have been programmed and a second set of pages that are unprogrammed
On the other hand, Paley which also relates to partial programming management for memory devices teaches The method of claim 1, wherein, while in the partially programmed state, the first block comprises a first set of pages that have been programmed and a second set of pages that are unprogrammed. (“For the first example, since the host write 54-57 is a partial page write and does not have the last sector of a metapage, 54-57 is written to the binary cache”) (paragraph [0227] line 1-2) (i.e. Fig 22A illustrates host write 54-57 is a partial page write and does not write last sector. In other words, here some pages are programmed and some are unprogrammed)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 1 is equally applicable to claim 9.
Regarding claim 10, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 1. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 1, further comprising: determining that the data stored in the first block is to be written to the second block, wherein whether to program the first block into the fully programmed state is determined after determining that the data is to be stored in the second block
On the other hand, Paley which also relates to partial programming management for memory devices teaches The method of claim 1, further comprising: determining that the data stored in the first block is to be written to the second block, wherein whether to program the first block into the fully programmed state is determined after determining that the data is to be stored in the second block. (“The binary cache is of finite capacity and its cached data will need to be flushed and archived periodically to make room.”) (paragraph [0248] line 1-2) (i.e. binary cache or first block has finite capacity and if it’s near capacity or full programmed, data will need to be flushed to main memory or second block periodically)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 1 is equally applicable to claim 10.
Regarding claim 11, Paley teaches An apparatus, comprising: one or more controllers; and one or more memory devices coupled with the one or more controllers, the one or more memory devices storing instructions executable by the one or more controllers to cause the apparatus to: write data stored in a first block to a second block; (“The memory system 90 includes a memory 200 whose operations are controlled by a controller 100. The memory 200 comprises of one or more array of non-volatile memory cells distributed over one or more integrated circuit chip”) (paragraph [0119] line 3-5)
(“the host 80 essentially issues a command to the memory system 90 to read or write a segment containing a string of logical sectors of data with contiguous addresses”) (paragraph [0154] line 5-6)
(“A second portion forms an optional cache for data in transit to the main memory”) (paragraph [0032] line 5) (i.e. Fig 1 illustrates memory system 90 includes a memory 200 whose operations are controlled by a controller 100 and memory 200 comprises of one or more array of non-volatile memory cells where host 80 sends commands or instructions to memory system 90 and a method is formed to store data in cache in transit to main memory. In other words, data is stored in cache memory in transit to main memory)
determine, based least in part on writing the data stored in the first block to the second block, whether to program the first block into a fully programmed state based at least in part on whether the first block is storing the data in a partially programmed state; (“With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2)
(“the write is to main memory if the binary cache is in partial page mode only. The binary cache is in partial page mode when the volume of valid data in the cache is near (by a predefined amount) the cache capacity”) (paragraph [0228] line 1-3) (i.e. Fig 20A step 410 and 412 illustrate determination to find if binary cache is near full then write or program proceeds to main memory and it happens only when binary cache is in partial program page mode. In other words, when it is determined after examining cache memory is near full, data is programmed or stored in main memory when cache memory is in partially program mode)
the value of the second data indicates (“See Fig. 15, paragraph [0202], illustrates set of data management page by page in 1st memory 204)
maintain, based at least in part on determining whether to program the first block, the first block in the fully programmed state until an erase operation is performed for the first block; and perform the erase operation for the first block. (“Cache compaction is enabled when unwritten capacity<=size of current data segment or when the unwritten capacity is less than 128 sectors”) (paragraph [0292] line 1-2)
(“All valid data from the selected block is copied in increasing LBA order to the cache write block, and the selected block is erased (or marked for erasure)”) (paragraph [0295] line 1-2) (i.e. Fig 23 illustrates when binary cache reaches unwritten capacity less than 128 sectors, all valid data from the selected block is copied and the selected block is erased. In other words, when binary cache is fully programmed and have capacity less than 128 sectors, it’s marked for erase)
Paley teaches partial programming management for memory devices. However, Paley does not explicitly teach reading a page of the first block, wherein the page of the first block stores second data
On the other hand, Parthasarathy which also relates to partial programming management for memory devices teaches reading a page of the first block, wherein the page of the first block stores second data (“See Fig. 2, paragraph [0030], illustrates controller 215 can issue read request to memory device 210)
Both Paley and Parthasarathy relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley with Parthasarathy by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Parthasarathy, to enable controller to issue read request to memory device. The combined system of Paley – Parthasarathy allows partially written blocks to reduce uncorrectable bit error rates (UBERs), reduce the number of corrective reads, and also reduce complexity associated with system controller as mentioned in paragraph [0013]. Therefore, the combination of Paley - Parthasarathy improves read performance of partially written blocks. See Parthasarathy, paragraph [0013].
Paley in view of Parthasarathy teaches partial programming management for memory devices. However, Paley - Parthasarathy combination does not explicitly teach and wherein a value of the second data that indicates whether the first block is storing the data in a partially programmed state
On the other hand, Li which also relates to partial programming management for memory devices teaches and wherein a value of the second data that indicates whether the first block is storing the data in a partially programmed state (“See Fig. 11A,11B paragraph [0108], illustrates flag bits are embedded in row of memory cells which are used to determine if page is partially or fully programmed where setting the flag bits are used to determine programming level)
Both Paley, Parthasarathy and Li relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, and see Li, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley - Parthasarathy combination with Li by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Parthasarathy, to enable flag bits are embedded in row of memory cells which are used to determine if page is partially or fully programmed where setting the flag bits are used to determine programming level. The combined system of Paley – Parthasarathy - Li allows improved partial page program capability as mentioned in paragraph [0001]. Therefore, the combination of Paley - Parthasarathy - Li improves read and program performance. See Li, paragraph [0038].
Paley in view of Parthasarathy and in view of Li further teaches partial programming management for memory devices. However, Paley - Parthasarathy combination does not explicitly teach invalidating, based at least in part on writing the data to the second block, the data stored in the first block;
and after the data stored in the first block is invalidated
On the other hand, Rousseau which also relates to partial programming management for memory devices teaches invalidate, based at least in part on writing the data to the second block, the data stored in the first block; (See Fig. 1,2 paragraph [0206], illustrates program VPG moves the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages)
and after the data stored in the first block is invalidated (See Fig. 1,2 paragraph [0206], illustrates after VPG moves valid descriptors to other page, source or first page is invalidated)
Both Paley, Parthasarathy, Li and Rousseau relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, and see Li, abstract, and see Rousseau, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley - Parthasarathy - Li combination with Rousseau by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Rousseau, to enable program VPG to move the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages. The combined system of Paley – Parthasarathy - Li - Rousseau allows as the memory space diminishes the invalid data are erased to free up memory space as mentioned in paragraph [0011]. Therefore, the combination of Paley - Parthasarathy - Li - Rousseau improves data write time and protect the data from tearing. See Rousseau, paragraph [0011].
Regarding claim 13, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 11. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The apparatus of claim 11, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: determine that the first block is storing the data in the partially programmed state, wherein the instructions for determining whether to program the first block are further executable by the one or more controllers to cause the apparatus to determine to program the first block into the fully programmed state based at least in part on determining that the first block is storing the data in the partially programmed state
On the other hand, Paley which also relates to partial programming management for memory devices teaches The apparatus of claim 11, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: determine that the first block is storing the data in the partially programmed state, wherein the instructions for determining whether to program the first block are further executable by the one or more controllers to cause the apparatus to determine to program the first block into the fully programmed state based at least in part on determining that the first block is storing the data in the partially programmed state. (“If the write is a partial page write, then it is always written to the binary cache”) (paragraph [0241] line 1)
(“FIG. 22B illustrates a second example a write that is sequential to the last sector of the logical group written to the binary cache”) (paragraph [0243] line 1-2)
(“STEP 412: With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2) (i.e. Fig 20A and 22B illustrate If the write is a partial page write then it is written to binary cache or first block that is sequential to the last sector of the logical group until it’s examined in step 412 if it’s nearly full or fully programmed)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 11 is equally applicable to claim 13.
Regarding claim 14, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 13. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The apparatus of claim 13, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: program, based at least in part on determining to program the first block in the fully programmed state, the first block to store second data that causes the first block to be in the fully programmed state
On the other hand, Paley which also relates to partial programming management for memory devices teaches The apparatus of claim 13, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: program, based at least in part on determining to program the first block in the fully programmed state, the first block to store second data that causes the first block to be in the fully programmed state. (“Data stored in the BC is aligned to Banks similarly to the alignment in the regular MLC blocks, Data within each Bank (within each meta-page) is not aligned--data can be stored into each 2 KB entry starting with any LBA and with any length. No pre/post padding is needed. If the data to be stored is not a multiple of 2 KB, then the last 2 KB will be partially written (padded with zeros)”) (paragraph [0227] line 1-5) (i.e. Fig 24 illustrates Data stored in the BC is aligned to Banks where data can be stored into each 2 KB entry starting with any LBA and with any length and if the data to be stored is not a multiple of 2 KB, then the last 2 KB will be partially written for fully programmed state)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 11 is equally applicable to claim 14.
Regarding claim 16, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 11. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The apparatus of claim 11, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: determine that the first block is storing the data in the fully programmed state, wherein the instructions for determining whether to program the first block are further executable by the one or more controllers to cause the apparatus to determine to maintain the first block into the fully programmed state
On the other hand, Paley which also relates to partial programming management for memory devices teaches The apparatus of claim 11, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: determine that the first block is storing the data in the fully programmed state, wherein the instructions for determining whether to program the first block are further executable by the one or more controllers to cause the apparatus to determine to maintain the first block into the fully programmed state. (“If routed to the binary cache ("BC") portion, the data will be managed by a BC management module. new block may need to be allocated or obsolete blocks recycled in cooperation with an erase (free) metablock management module. A set of control data is generated and maintained during the various block manipulations and data storage into the blocks”) (paragraph [0202] line 7-11) (i.e. Binary cache data is managed by a BC management module and it may include new block in cooperation with an erase (free) metablock when a set of control data is generated and maintained during the various block manipulations. In other words, data is maintained in fully programmed state until block management manipulates various blocks)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 11 is equally applicable to claim 14.
Regarding claim 17, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 11. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The apparatus of claim 11, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: invalidate, based at least in part on writing the data to the second block, the data stored in the first block, wherein whether to program the first block into the fully programmed state is determined after the data stored in the first block is invalidated
On the other hand, Paley which also relates to partial programming management for memory devices teaches The apparatus of claim 11, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: invalidate, based at least in part on writing the data to the second block, the data stored in the first block, wherein whether to program the first block into the fully programmed state is determined after the data stored in the first block is invalidated. (“STEP 412: With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2) (i.e. Fig 20A step 412 illustrates when binary cache is examined and if it’s full, then essentially it’s access is invalidated and data is moved to main memory or other block)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 11 is equally applicable to claim 17.
Regarding claim 18, Paley teaches A non-transitory, computer-readable medium storing code comprising instructions executable by one or more processors of an electronic device to cause the electronic device to: write data stored in a first block to a second block; (“the host 80 essentially issues a command to the memory system 90 to read or write a segment containing a string of logical sectors of data with contiguous addresses”) (paragraph [0154] line 5-6)
(“A second portion forms an optional cache for data in transit to the main memory”) (paragraph [0032] line 5) (i.e. Fig 1 illustrates memory system 90 includes a memory 200 whose operations are controlled by a controller 100 and memory 200 comprises of one or more array of non-volatile memory cells where host 80 sends commands or instructions to memory system 90 and a method is formed to store data in cache in transit to main memory. In other words, data is stored in cache memory in transit to main memory)
determine, based least in part on writing the data stored in the first block to the second block, whether to program the first block into a fully programmed state based at least in part on whether the first block is storing the data in a partially programmed state; (“With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2)
(“the write is to main memory if the binary cache is in partial page mode only. The binary cache is in partial page mode when the volume of valid data in the cache is near (by a predefined amount) the cache capacity”) (paragraph [0228] line 1-3) (i.e. Fig 20A step 410 and 412 illustrate determination to find if binary cache is near full then write or program proceeds to main memory and it happens only when binary cache is in partial program page mode. In other words, when it is determined after examining cache memory is near full, data is programmed or stored in main memory when cache memory is in partially program mode)
the value of the second data indicates (See Fig. 15, paragraph [0202], illustrates set of data management page by page in 1st memory 204)
maintain, based at least in part on determining whether to program the first block, the first block in the fully programmed state until an erase operation is performed for the first block; and perform the erase operation for the first block. (“Cache compaction is enabled when unwritten capacity<=size of current data segment or when the unwritten capacity is less than 128 sectors”) (paragraph [0292] line 1-2)
(“All valid data from the selected block is copied in increasing LBA order to the cache write block, and the selected block is erased (or marked for erasure)”) (paragraph [0295] line 1-2) (i.e. Fig 23 illustrates when binary cache reaches unwritten capacity less than 128 sectors, all valid data from the selected block is copied and the selected block is erased. In other words, when binary cache is fully programmed and have capacity less than 128 sectors, it’s marked for erase)
Paley teaches partial programming management for memory devices. However, Paley does not explicitly teach reading a page of the first block, wherein the page of the first block stores second data
On the other hand, Parthasarathy which also relates to partial programming management for memory devices teaches reading a page of the first block, wherein the page of the first block stores second data (“See Fig. 2, paragraph [0030], illustrates controller 215 can issue read request to memory device 210)
Both Paley and Parthasarathy relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley with Parthasarathy by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Parthasarathy, to enable controller to issue read request to memory device. The combined system of Paley – Parthasarathy allows partially written blocks to reduce uncorrectable bit error rates (UBERs), reduce the number of corrective reads, and also reduce complexity associated with system controller as mentioned in paragraph [0013]. Therefore, the combination of Paley - Parthasarathy improves read performance of partially written blocks. See Parthasarathy, paragraph [0013].
Paley in view of Parthasarathy teaches partial programming management for memory devices. However, Paley - Parthasarathy combination does not explicitly teach and wherein a value of the second data that indicates whether the first block is storing the data in a partially programmed state
On the other hand, Li which also relates to partial programming management for memory devices teaches and wherein a value of the second data that indicates whether the first block is storing the data in a partially programmed state (“See Fig. 11A,11B paragraph [0108], illustrates flag bits are embedded in row of memory cells which are used to determine if page is partially or fully programmed where setting the flag bits are used to determine programming level)
Both Paley, Parthasarathy and Li relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, and see Li, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley - Parthasarathy combination with Li by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Parthasarathy, to enable flag bits are embedded in row of memory cells which are used to determine if page is partially or fully programmed where setting the flag bits are used to determine programming level. The combined system of Paley – Parthasarathy - Li allows improved partial page program capability as mentioned in paragraph [0001]. Therefore, the combination of Paley - Parthasarathy - Li improves read and program performance. See Li, paragraph [0038].
Paley in view of Parthasarathy and in view of Li further teaches partial programming management for memory devices. However, Paley - Parthasarathy combination does not explicitly teach invalidating, based at least in part on writing the data to the second block, the data stored in the first block;
and after the data stored in the first block is invalidated
On the other hand, Rousseau which also relates to partial programming management for memory devices teaches invalidate, based at least in part on writing the data to the second block, the data stored in the first block; (See Fig. 1,2 paragraph [0206], illustrates program VPG moves the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages)
and after the data stored in the first block is invalidated (See Fig. 1,2 paragraph [0206], illustrates after VPG moves valid descriptors to other page, source or first page is invalidated)
Both Paley, Parthasarathy, Li and Rousseau relate to partial programming management for memory devices (see Paley, abstract, and see Parthasarathy, abstract, and see Li, abstract, and see Rousseau, abstract, regarding partial programming management).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Paley - Parthasarathy - Li combination with Rousseau by incorporating partial programming management for memory devices by making determination of partial program of a block, as taught by Rousseau, to enable program VPG to move the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages. The combined system of Paley – Parthasarathy - Li - Rousseau allows as the memory space diminishes the invalid data are erased to free up memory space as mentioned in paragraph [0011]. Therefore, the combination of Paley - Parthasarathy - Li - Rousseau improves data write time and protect the data from tearing. See Rousseau, paragraph [0011].
Regarding claim 20, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 18. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The non-transitory, computer-readable medium of claim 18, wherein the instructions are further executable by the one or more processors to cause the electronic device to: determine that the first block is storing the data in the partially programmed state, wherein the instructions for determining whether to program the first block are further executable by the one or more processors to cause the electronic device to determine to program the first block into the fully programmed state based at least in part on determining that the first block is storing the data in the partially programmed state
On the other hand, Paley which also relates to partial programming management for memory devices teaches The non-transitory, computer-readable medium of claim 18, wherein the instructions are further executable by the one or more processors to cause the electronic device to: determine that the first block is storing the data in the partially programmed state, wherein the instructions for determining whether to program the first block are further executable by the one or more processors to cause the electronic device to determine to program the first block into the fully programmed state based at least in part on determining that the first block is storing the data in the partially programmed state. (“If the write is a partial page write, then it is always written to the binary cache”) (paragraph [0241] line 1)
(“FIG. 22B illustrates a second example a write that is sequential to the last sector of the logical group written to the binary cache”) (paragraph [0243] line 1-2)
(“STEP 412: With at least a page to be written, the binary cache is examined if its capacity is nearly full. If so write to the main memory instead by proceed along line 431 to write to main memory in STEP 430”) (paragraph [0227] line 1-2) (i.e. Fig 20A and 22B illustrate If the write is a partial page write then it is written to binary cache or first block that is sequential to the last sector of the logical group until it’s examined in step 412 if it’s nearly full or fully programmed)
The same motivation that was utilized for combining Paley - Parthasarathy - Li combination with Rousseau as set forth in claim 18 is equally applicable to claim 20.
Claim(s) 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau and further in view of Inbar et al. (US 20210389879 A1) hereinafter Inbar.
Regarding claim 5, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 3. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The method of claim 3, further comprising: programming, based at least in part on determining to program the first block in the fully programmed state, the first block to have a threshold voltage distribution within a threshold voltage window that corresponds to the fully programmed state
On the other hand, Inbar which also relates to partial programming management for memory devices The method of claim 3, further comprising: programming, based at least in part on determining to program the first block in the fully programmed state, the first block to have a threshold voltage distribution within a threshold voltage window that corresponds to the fully programmed state. (“In step 1048, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 1052. If, in 1050, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 1054”) (paragraph [0093] line 1-5) (i.e. Fig 10 step 1048 illustrates if all memory cells have reached their target threshold voltages then programming process is complete and successful because all selected memory cells were programmed and verified to their target states. In other words, programming all cells of any block corresponds to threshold voltages to determine if they are in fully programmed state)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Paley - Parthasarathy - Rousseau combination with Li for the reasons set forth in claim 3 above. In addition, Paley, Parthasarathy, Li, Rousseau and Inbar are considered analogous arts, because they all relate to partial programming management for memory devices. Paley – Parthasarathy - Li - Rousseau combination teaches partial programming management for memory devices. Paley – Parthasarathy - Li combination does not teach threshold voltages to determine if they are in fully programmed state. On the other hand, Inbar teaches partial programming for memory devices and threshold voltages to determine if they are in fully programmed state. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Paley – Parthasarathy - Li - Rousseau combination with Inbar partial programming for memory devices and threshold voltages to determine if they are in fully programmed state providing better programming data management so that the host device (or other client) does not have to wait very long for the memory system to finish the programming as mentioned in paragraph [0002].
Regarding claim 15, Paley in view of Parthasarathy and further in view of Li and further in view of Rousseau teaches partial programming management for memory devices in claim 13. However, Paley – Parthasarathy - Li - Rousseau combination does not explicitly teach The apparatus of claim 13, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: program, based at least in part on determining to program the first block in the fully programmed state, the first block to have a threshold voltage distribution within a threshold voltage window that corresponds to the fully programmed state
On the other hand, Inbar which also relates to partial programming management for memory devices The apparatus of claim 13, wherein the instructions are further executable by the one or more controllers to cause the apparatus to: program, based at least in part on determining to program the first block in the fully programmed state, the first block to have a threshold voltage distribution within a threshold voltage window that corresponds to the fully programmed state. (“In step 1048, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 1052. If, in 1050, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 1054”) (paragraph [0093] line 1-5) (i.e. Fig 10 step 1048 illustrates if all memory cells have reached their target threshold voltages then programming process is complete and successful because all selected memory cells were programmed and verified to their target states. In other words, programming all cells of any block corresponds to threshold voltages to determine if they are in fully programmed state)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Paley - Parthasarathy - Rousseau combination with Li for the reasons set forth in claim 13 above. In addition, Paley, Parthasarathy, Li, Rousseau and Inbar are considered analogous arts, because they all relate to partial programming management for memory devices. Paley – Parthasarathy - Li combination teaches partial programming management for memory devices. Paley – Parthasarathy - Li - Rousseau combination does not teach threshold voltages to determine if they are in fully programmed state. On the other hand, Inbar teaches partial programming for memory devices and threshold voltages to determine if they are in fully programmed state. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Paley – Parthasarathy - Li - Rousseau combination with Inbar partial programming for memory devices and threshold voltages to determine if they are in fully programmed state providing better programming data management so that the host device (or other client) does not have to wait very long for the memory system to finish the programming as mentioned in paragraph [0002].
Response to Arguments
Applicant’s arguments filed on 03/05/2025 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1, 11 and 18 amendments mapping by references Paley, Parthasarathy and Li in page 10 - 13 of the response: Paley, does not teach or suggest "invalidating, based at least in part on writing the data to the second block, the data stored in the first block," as recited in amended independent claim 1.
First, the binary cache of Paley is different from, and cannot be properly interpreted to teach or suggest a "first block," as recited in amended independent claim 1. Second, Paley does not contemplate any invalidation of data, much less "invalidating" any "data stored in [a] first block," as claimed. Instead, as described above, Paley describes determining, during a host write process, whether a binary cache is almost at capacity and writing data to either the intermediate binary cache or main memory of a flash memory system based on the determination. Thus, regardless of whether the binary cache is full or not, the data in Paley is written and used as valid data. Thus, it follows that determining whether a binary cache is full or not-as in Paley-cannot be relied on to teach or suggest "invalidating ...data stored in [a] first block," as claimed.
Third, Paley also fails to teach or suggest "determining, based least in part on writing the data stored in the first block to the second block and after the data stored in the first block is invalidated, whether to program the first block into a fully programmed state," as recited in amended independent claim 1. Rather, as discussed above, Paley merely contemplates whether a cache is full or not, and then writes data to the cache or to main memory accordingly. However, even if writing the data to the cache or to the main memory, as in Paley, could be considered relevant to "determining ...whether to program the first block into a fully programmed state," as claimed-which Applicant expressly does not concede to be true-Paley still fails to teach orPage 11 of 13
suggest any "invalidating ... [of] the data stored in the first block," much less the determination of where to write the data being "after the data stored in the first block is invalidated," as claimed.
Thus, Paley does not teach or suggest all of the features recited in amended independent claim 1. Parthasarathy, Li, and Inbar do not overcome the deficiencies of Paley, nor does the Office Action suggest otherwise
In summary, applicant argued that primary and secondary references Paley, Parthasarathy and Li do not teach amended claim invalidating the data stored in the first block after writing the data to the second block. The amendment necessitates adding secondary reference Rousseau in this regard. For further clarification examiner cites portion from Rousseau. Also, for applicant’s understanding examiner would like to explain the teachings of Rousseau and examiner’s interpretation in more detail here. See Fig. 1,2 paragraph [0206], Rousseau teaches program VPG moves the valid descriptors to the other or second page, then invalidates the source or first page by writing all the bits of the field MID of the page and first page is erased ensuring invalid pages. Also See Fig. 1,2 paragraph [0206], Rousseau teaches after VPG moves valid descriptors to other page, source or first page is invalidated. In the cited portions Rousseau clearly teaches program VPG moves valid descriptors to other or second page, source or first page is invalidated and first page is erased ensuring invalid pages. Thus, the rejection of amended claims 1, 11 and 18 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights