Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filled 02/25/2026 have been considered but are moot because the new ground of rejection does not rely solely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4 and 6-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 and similarly claim 11 recites, “wherein the ASIC has a finite state machine (FSM), which is configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip.” The phrase "configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip" was not present in the claims originally filled. Review of the specification reveals on page 4 lines 9-12, “Furthermore, it may be provided that the ASIC is set up to control a deactivation sequence of the connected radar chip, for example by deactivating individual or several of the supply voltages of the radar chip;” however, the examiner can find no disclosure clarifying that is explicitly the finite state machine that activates and deactivates individual or several supply voltages of the radar chip. Figures 2-4 disclose that the finite state machine(FSM) is part of the RC-ASIC, but do not further demonstrate that it is the finite state machine that activates and deactivates supply voltages.
Claims 2-4, and 6-10 are also rejected based on their dependency of the defected parent claim(s).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 and similarly claim 1 recites, “An application-specific integrated circuit (ASIC) configured for a level radar measuring device, which comprises a radar chip, the ASIC and the radar chip being separate components.” It is unclear how the claimed ASIC can both comprise a radar chip and be separate from the radar chip simultaneously. The limitation is excessively broad in nature and the meets and bounds of the limitation cannot be ascertained by one skilled in the art. Review of the specification reveals at Page 2 lines 15-17, “The ASIC and the radar chip are separate components and are interconnected via corresponding control and supply lines.” It suggested applicant amend the claims to be consistent with the disclosed ASIC and radar chip. For examination purposes the above limitations will be interpreted to mean that ASIC and radar chip are separate components.
Claim 7 recites, “wherein the ASIC is a radar companion ASIC.” It is unclear what is explicitly meant by redefining the ASIC to a “radar companion ASIC” as the definition of a “radar companion ASIC” is unclear and both ASICs have the same function. The limitation is excessively broad in nature and the meets and bounds of the limitation cannot be ascertained by one skilled in the art. Review of the specification reveals at Page 7 lines 26-26, “The ASIC 102 can supply the VCO 107 and the multiplier 108 of the MMIC 101 with energy and perform or trigger a self-test of the MMIC 101 (see Fig. 3). In particular, the RC-ASIC 102 can be used to check the function of the MMIC 101.” Although the Specification discloses the use of an “RC-ASIC” the examiner can not find further clarification on how the “ASIC” and “RC-ASIC” differ or an explicit definition of the claimed “RC-ASIC.” It suggested applicant amend the claims to be consistent with the disclosed ASIC. For examination purposes the above limitations will be interpreted to refer to an ASIC use in a radar application.
Claims 2-4 and 6-10 are also rejected based on their dependency of the defected parent claim(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-4, 6-8, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Straub(US9075144B1) in view of Cappello(US20210119582A1)
Regarding claim 1, Straub discloses
A radar circuit for a measuring device, comprising: […]; an application-specific integrated circuit (ASIC) (“The controller 34 may also include … application-specific integrated circuits (ASICs)” [Col.8, ll.27-30]); and a processor, configured to determine a measured value (“The processor may determine the frequency of the difference signal and compute the altitude” [Col.3, ll.25-26]).
Straub does not explicitly disclose nor limit wherein the radar circuit comprises a radar chip or wherein a finite state machine is configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip. Cappello discloses, a radar chip configured to generate a radar measurement signal (“a single-stage MMIC PA 210 “ [0041])[…] wherein the ASIC and the radar chip are separate components (FIG.3A, part210) and wherein the ASIC has a finite state machine (FSM), (“This control is implemented in the finite-state machine (FSM) shown in FIG. 4” [0036]) which is configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip (“The FSM generates commands to charge the capacitors to VDC/2 through the bias current at VDS of the PA. During the start-up, no RF signal is amplified by the PA (only quiescent current present)” [0044]).
Straub teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Straub with the teachings of Cappello to incorporate the features of a radar chip and a finite state machine configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip so as to gain the advantage of improving efficiency ([0004], Cappello). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 2, Straub as modified by Cappello discloses all the limitations of claim 1. Straub discloses wherein, the ASIC comprises a phase locked loop (PLL) (“The first upconverter 14 may include frequency shifting, converting, or generating circuitry such as phase-locked loops (PLLs)” [Col.4, ll.32-35]).
Regarding claim 3, Straub as modified by Cappello discloses all the limitations of claim 1. Straub discloses wherein, the ASIC comprises an analog-to-digital converter (ADC) circuit (“The baseband signal 76 from the fifth amplifier 80 may be converted to a digital form by an analog-to-digital converter (ADC) 82” [Col.8, ll.19-21]).
Regarding claim 4, Straub as modified by Cappello discloses all the limitations of claim 1. Straub discloses wherein, the ASIC has a digital interface to the processor (“The communications port 36 may act as an interface between the digital radar altimeter system 10 and other systems” [Col.8, ll.41-43]).
Regarding claim 6, Straub as modified by Cappello discloses all the limitations of claim 1. Straub does not explicitly disclose nor limit wherein the radar chip is a radar monolithic microwave integrated circuit (MMIC). Cappello discloses wherein, the radar chip is a radar monolithic microwave integrated circuit (MMIC) (“a single-stage MMIC PA 210 “ [0041])
Cappello teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Straub with the teachings of Cappello to incorporate the features of the radar chip being a radar monolithic microwave integrated circuit (MMIC) so as to gain the advantage of improving back off efficiency ([0042], Cappello). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 7, Straub as modified by Cappello discloses all the limitations of claim 1. Straub discloses wherein, the ASIC is a radar companion ASIC, which is configured to perform control tasks and/or measured value acquisition tasks in the radar circuit (“The controller 34 may time sample the baseband signal 76” [Col.11, ll.12-13]).
Regarding claim 8, Straub as modified by Cappello discloses all the limitations of claim 1. Straub discloses wherein, the radar circuit is a level radar circuit for a level radar measuring device (“A radar or radio altimeter measures the distance between an aircraft and the ground” [Col.1, ll.6-7] & FIG.8, Parts.88 & 10).
Regarding claim 10, Straub as modified by Cappello discloses all the limitations of claim 1. Straub discloses wherein, the ASIC is configured to supply a voltage-controlled oscillator (VCO) of the radar chip and/or a multiplier of the radar chip (“The first upconverter 14 may include frequency shifting, converting, or generating circuitry such as … voltage-controlled oscillators (VCOs)” [Col.4, ll.32-35]).
Regarding claim 11, Straub discloses
An application-specific integrated circuit (ASIC) (“The controller 34 may also include … application-specific integrated circuits (ASICs)” [Col.8, ll.27-30]) configured for a level radar measuring device (“A radar or radio altimeter measures the distance between an aircraft and the ground” [Col.1, ll.6-7] & FIG.8, Parts.88 & 10)
Straub does not explicitly disclose nor limit wherein the radar circuit comprises a radar chip or wherein a finite state machine is configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip. Cappello discloses, which comprises a radar chip (“a single-stage MMIC PA 210 “ [0041]), the ASIC and the radar chip being separate components (“This control is implemented in the finite-state machine (FSM) shown in FIG. 4” [0036]) wherein the ASIC has a finite state machine (FSM), which is configured to control the radar chip by deactivating individual or several supply voltages of the radar chip. (“The FSM generates commands to charge the capacitors to VDC/2 through the bias current at VDS of the PA. During the start-up, no RF signal is amplified by the PA (only quiescent current present)” [0044]).
Straub teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Straub with the teachings of Cappello to incorporate the features of a radar chip and a finite state machine configured to control the radar chip by activating and deactivating individual or several supply voltages of the radar chip so as to gain the advantage of improving efficiency ([0004], Cappello). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Straub(US9075144B1) as modified by Cappello(US20210119582A1) as applied to claims 1-4, 6-8, and 10-11 above, and further in view of WELLE(EP3467450A1).
Regarding claim 9, Straub as modified by Cappello discloses all the limitations of claim 1. Straub as modified by Cappello does not explicitly disclose nor limit wherein the radar system includes a sleep mode. WELLE discloses wherein, the ASIC is configured to wake the processor from a sleep mode (“if the energy budget decreases and/or an upper limit temperature is reached, the device can automatically switch to a second operating mode in which only a reduced number of RSOCs are used for the measurement” [0050]) and thereupon transmit measurement data to the processor (“During all transmission phases, the receiving stages of the radar chips 102, 103 connected to the receiving elements 113 to 119 are activated and transmit the captured data to the evaluation unit” [0055]).
WELLE teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Straub as modified by Cappello with the teachings of WELLE to incorporate the features of a sleep mode so as to gain the advantage of reducing energy consumption ([0051], Welle). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Documents Considered but not Relied Upon
The prior art made of record and not relied upon is considered pertinent to the applicant’s Disclosure.
Jungmaier (US11360185B2) is considered analogous art to the instant application as it discloses in [Col.3, ll.64-65] “processor 104 may be implemented as a custom application specific integrated circuit (ASIC).”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CLAYTON PAUL RIDDER whose telephone number is (571)272-2771. The examiner can normally be reached Monday thru Friday ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Keith can be reached on (571) 272-6878. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.R./Examiner, Art Unit 3646
/JACK W KEITH/Supervisory Patent Examiner, Art Unit 3646
Prosecution Insights