DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114 2.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/28/2026 has been entered.
Response to Arguments
Applicant's arguments filled 08/28/2026 have been considered but are moot because the new ground of rejection does not rely solely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 3, 4, 7, 8, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Mata (US 12239456 B1) in view of Costello(US 20190019140 A1) and WELLE (US 20200252867 A1)
Regarding claim 1, Mata discloses
A radar circuit for a measuring device (“The received mmwave RF signals are processed to generate radar data “ [Col.2, ll.8-9]), comprising: a radar chip, configured to generate a radar measurement signal (“a mmwave radar chip “ [col.2, ll.42]); an application-specific integrated circuit (ASIC) (“The processor board 166 may include one or more processors and circuit elements, such as application-specific integrated circuits” [Col.7, ll.37-39]); and a processor (“the instructions represent modules that include circuitry or code executable by processor(s)” [Col/22, ll.18-20]) configured to determine a measured value (“The radar data generated by the mmwave radar chip can indicate macro-level motion detection and micro-level motion detection” [Col.15, ll.49-51]), configured to determine a measured value, […] wherein the ASIC and the radar chip are separate components (FIG.10, Parts.1010 & 1020), wherein the ASIC has a finite state machine (FSM), which is configured to control the radar chip (“The processing chip 1100 is an embodiment of the processing chip 1010 of FIG. 10. The application modules can include, for instance, a controller application 1110, a radar application 1120, a sensor application 1130” [Col.18, ll.19-23] & “ the radar application 1120 can maintain a state machine, where the current state indicated by the state machine can control the operational state of the mmwave radar chip” [Col.18, ll.59-62]), wherein the ASIC is configured to control an activation sequence (FIG.8, Step.802) and a deactivation sequence of the radar chip (FIG.8, Step.814)
Mata does not explicitly disclose nor limit activating and deactivating individual or several supply voltages of the radar chip. Costello discloses, activating and deactivating individual or several supply voltages of the radar chip (“The controller 155, in response, activates the sensor 150 by sending a signal to the power management circuit 148” [0088])
Costello teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata with the teachings of Cappello to incorporate the features activating and deactivating individual or several supply voltages of the radar chip so as to gain the advantage of reducing energy consumption. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Mata as modified by Cappello does not explicitly disclose nor limit a sleep mode for a processor. WELLE discloses, wherein the ASIC is further configured to wake the processor from a sleep mode (“The time module could also send a signal to a processor that is in power save or sleep mode, which is fully powered back on by a wake-up signal or command.” [0010]) and thereupon transmit measurement data to the processor (“As soon as the processor has collected enough data or after a certain time interval, it prepares the sensor data for transmission” [0010]).
WELLE teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello with the teachings of WELLE to incorporate the features a sleep mode for a processor so as to gain the advantage of reducing energy consumption. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 3, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata does not explicitly disclose nor limit analog-to-digital converter. Cappello discloses wherein, the ASIC comprises an analog-to-digital converter (ADC) circuit (“As one skilled in the art will realize, an analog-to-digital converter may be utilized to transform the analog signal to a digital signal for use by a controller or processing device.” [0200]).
Costello teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata with the teachings of Cappello to incorporate the features of an analog-to-digital converter (ADC) circuit so as to gain the advantage of improving signal processing capabilities. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 4, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata as modified by Cappello does not explicitly disclose nor limit wherein the ASIC has a digital interface to the processor. WELLE discloses wherein, the ASIC has a digital interface to the processor (“ the gateway is integrated into a sensor data source. […] the sensor data may be transmitted to the processor via a wired or hard-wired connection” [0023] & “The interfaces 204, 205, 206 are usually at the same time communication lines via which the measured values of the sensors are transmitted back to the Gateway 207 in analogue and/or digital form” [0049]))
Regarding claim 7, Mata as modified by Cappello and WELLE disclose
The radar circuit according to claim 1, wherein the ASIC is further configured to perform control tasks and/or measured value acquisition tasks in the radar circuit (“the one or more processors, for example as embodied in the processing chip can activate the mmwave radar chip” [Col.3, ll.17-19]).
Regarding claim 8, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata as modified by Cappello does not explicitly disclose nor limit wherein the radar circuit is a level radar circuit for a level radar measuring device. WELLE discloses wherein, the radar circuit is a level radar circuit for a level radar measuring device (“ a sensor, in particular in a level sensor” [0038]).
WELLE teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello with the teachings of WELLE to incorporate the features a level radar measuring device so as to gain the advantage of improving groundwater management [0038, WELLE]). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 11, Mata discloses
An application-specific integrated circuit (ASIC) (“The received mmwave RF signals are processed to generate radar data “ [Col.2, ll.8-9])[…], which comprises a radar chip (“a mmwave radar chip “ [col.2, ll.42]) and a processor (“the instructions represent modules that include circuitry or code executable by processor(s)” [Col/22, ll.18-20]), the ASIC and the radar chip being separate components (FIG.10, Parts.1010 & 1020), wherein the ASIC has a finite state machine (FSM), which is configured to control the radar chip (“The processing chip 1100 is an embodiment of the processing chip 1010 of FIG. 10. The application modules can include, for instance, a controller application 1110, a radar application 1120, a sensor application 1130” [Col.18, ll.19-23] & “ the radar application 1120 can maintain a state machine, where the current state indicated by the state machine can control the operational state of the mmwave radar chip” [Col.18, ll.59-62]), wherein the ASIC is configured to control a deactivation sequence of the radar chip (FIG.8, Step.802)
Mata does not explicitly disclose nor limit deactivating individual or several supply voltages of the radar chip. Costello discloses, deactivating individual or several supply voltages of the radar chip (“The controller 155, in response, activates the sensor 150 by sending a signal to the power management circuit 148” [0088])
Costello teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata with the teachings of Cappello to incorporate the features activating and deactivating individual or several supply voltages of the radar chip so as to gain the advantage of reducing energy consumption. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Mata as modified by Cappello does not explicitly disclose nor limit a sleep mode for a processor. WELLE discloses, configured for use in a level radar measuring device (“ a sensor, in particular in a level sensor” [0038]) […] wherein the ASIC is further configured to wake the processor from a sleep mode (“The time module could also send a signal to a processor that is in power save or sleep mode, which is fully powered back on by a wake-up signal or command.” [0010]) and thereupon transmit measurement data to the processor (“As soon as the processor has collected enough data or after a certain time interval, it prepares the sensor data for transmission” [0010]).
WELLE teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello with the teachings of WELLE to incorporate the features a sleep mode for a processor so as to gain the advantage of reducing energy consumption. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 12, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata as modified by Cappello does not explicitly disclose nor limit a sleep mode. WELLE discloses wherein, the ASIC is further configured, while the processor is in the sleep mode (“The time module could also send a signal to a processor that is in power save or sleep mode, which is fully powered back on by a wake-up signal or command.” [0010]), to digitize signals detected by the radar chip and internally store digitized samples of the signals (“the data transmitted by the sensors 401, 402, 403 are received and temporarily stored” [0052])
WELLE teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello with the teachings of WELLE to incorporate the features of while the processor is in the sleep mode, digitizing signals detected by the radar chip and internally store the samples so as to gain the advantage of reducing data loss. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Mata (US 12239456 B1) as modified by Costello(US 20190019140 A1) and WELLE (US 20200252867 A1) as applied to claim 1 above, and further in view of Straub(US9075144B1) .
Regarding claim 2, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata as modified by Cappello and WELLE does not explicitly disclose nor limit a phase locked loop. Straub discloses wherein, the ASIC comprises a phase locked loop (PLL) (“The first upconverter 14 may include frequency shifting, converting, or generating circuitry such as phase-locked loops (PLLs)” [Col.4, ll.32-35]).
Straub teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello and WELLE with the teachings of Straub to incorporate the features a phase locked loop (PLL) so as to gain the advantage of improving frequency stability. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Regarding claim 10, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata as modified by Cappello and WELLE does not explicitly disclose nor limit a voltage controlled oscillator. Straub discloses wherein, the ASIC is configured to supply a voltage-controlled oscillator (VCO) of the radar chip and/or a multiplier of the radar chip (“The first upconverter 14 may include frequency shifting, converting, or generating circuitry such as … voltage-controlled oscillators (VCOs)” [Col.4, ll.32-35]).
Straub teaches in the same field of endeavor of radar system design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello and WELLE with the teachings of Straub to incorporate the features of a voltage-controlled oscillator (VCO) so as to gain the advantage of improving frequency tuning. Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mata (US 12239456 B1) as modified by Costello(US 20190019140 A1) and WELLE (US 20200252867 A1) as applied to claim 1 above, and further in view of Cappello(US20210119582A1).
Regarding claim 6, Mata as modified by Cappello and WELLE disclose all the limitations of claim 1.
Mata as modified by Costello and WELLE and does not explicitly disclose nor limit a monolythic microwave integrated circuit. Cappello discloses wherein, the radar chip is a radar monolythic microwave integrated circuit (MMIC) (“a single-stage MMIC PA 210 “ [0041])
Cappello teaches in the same field of endeavor of radar circuit design. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Mata as modified by Cappello and WELLE with the teachings of Cappello to incorporate the features of the radar chip being a radar monolithic microwave integrated circuit (MMIC) so as to gain the advantage of improving back off efficiency ([0042], Cappello). Also, since it has been held that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill (MPEP 2143).
Documents Considered but not Relied Upon
The prior art made of record and not relied upon is considered pertinent to the applicant’s Disclosure.
Jungmaier (US11360185B2) is considered analogous art to the instant application as it discloses in [Col.3, ll.64-65] “processor 104 may be implemented as a custom application specific integrated circuit (ASIC).”
Conclusion
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/C.P.R./Examiner, Art Unit 3646
/JACK W KEITH/Supervisory Patent Examiner, Art Unit 3646
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