DETAILED ACTION
Statement of claims
The present application includes:
Claims 1-20 are pending in the application. Claims 1-20 are being considered on the merits.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Under Step 2A, Prong 1, Claim 1, recites judicial exception including certain groupings of abstract idea . Claim 1 recites “for a quantum circuit, determining a graphics processing unit (GPU) service-level-objective (SLO) metric for the quantum circuit when executed using a GPU”, “ for the same quantum circuit, determining a central processing unit (CPU) SLO metric for the quantum circuit when executed using a CPU” , are a process that, under their broadest reasonable interpretation, covers performance of the limitation in the mind, but for the recitation of generic computer components. That is, other than reciting “for a quantum circuit”, “graphics processing unit (GPU)”, “for the quantum circuit when executed using a GPU”, “a central processing unit (CPU)”, “or the quantum circuit when executed using a CPU”, “the CPU SLO metric and the GPU SLO metric” nothing in the claim element precludes the step from practically being performed in a human mind or with the aid of pen and paper. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind, then it falls within the “Mental Processes” grouping of abstract ideas (concepts performed in the human mind including an observation, evaluation, judgment, and opinion).
Further, claim 1 recites “ determining a ratio factor between the CPU SLO metric and the GPU SLO metric” , “for a new quantum circuit, estimating a new GPU SLO metric for the new quantum circuit” , “ for the same new quantum circuit, deriving a new CPU SLO metric by applying the ratio factor to the estimated new GPU SLO metric”, which recite judicial exception including certain groupings of abstract idea (i.e. mathematical concepts). Claim 1 recites “determining a ratio…”, “estimating…” , “deriving …“ step which are mathematical concepts. Therefore, the limitations fall under mathematical concepts.
Under Prong 2,
The judicial exception is not integrated into a practical application.
The additional elements “applying the ratio factor to the estimated new GPU SLO metric”, “based at least on the estimated new GPU SLO metric and the new CPU SLO metric selecting either one of the GPU or the CPU to execute the new quantum circuit.” which “applying… “ and “selecting …” are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)).
The additional element of “GPU” , “GPU or the CPU to execute the new quantum circuit.”, “PU SLO metric” are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). The claim is directed to an abstract idea.
Under Step 2B,
The claim does not include additional elements that are sufficient to amount significantly more than the judicial exception. The limitations “applying” and “selecting …” is recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component.
Therefore, claim 1 as a whole does not amount to significantly more than the judicial exception. Consequently, claim 1 is not eligible.
As to claim 2, recites the additional element “wherein the CPU SLO metric is a CPU execution time, wherein the GPU SLO metric is a GPU execution time, wherein the new CPU SLO metric is a new CPU execution time, and wherein the estimated new GPU SLO metric is a new GPU execution time”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 3, recites the additional element “wherein determining the GPU execution time for the quantum circuit is performed by executing the quantum circuit using a simulation engine executing on the GPU, and wherein determining the CPU execution time for the quantum circuit is performed using the same simulation engine now executing on the CPU”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 4, recites the additional element “ wherein the quantum circuit is one quantum circuit included in a defined group of quantum circuits, the defined group being defined based on a determination that all of the quantum circuits in the group share a same selected characteristic”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 5, recites the additional element “wherein the quantum circuit is selected from the group as a result of the GPU execution time for the quantum circuit being longest as compared to GPU execution times for other quantum circuits in said group” , which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 6, recites the additional element “ wherein the ratio factor associated with the quantum circuit is selected to derive the new CPU execution time for the new quantum circuit based on a determination that the new quantum circuit and said quantum circuit share a same selected characteristic”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 7, recites the additional element “ wherein the estimated new GPU execution time is shorter than the new CPU execution time”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
.
As to claim 8, recites the additional element “wherein, despite the new CPU execution time being longer than the estimated new GPU execution time, the CPU is selected to execute the new quantum circuit, and the CPU is selected based on consideration of at least one additional parameter”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 9, recites the additional element “wherein estimating the new GPU execution time for the new quantum circuit is performed using a trained model that is trained to predict GPU execution times”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 10, recites the additional element “wherein the GPU execution time is one of multiple GPU execution times that were generated using a simulation engine executing on the GPU, and wherein said GPU execution time is an upper bound GPU execution time as a result of said GPU execution time being longest as compared to other GPU execution times included in said multiple GPU execution times”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
.
Claims 11-17:
• Similar analysis as claims 1-2 applies to claims 11-12.
Further claim 11 recites the additional element “One or more hardware storage devices that store instructions that are executable by one or more processors of a computer system to cause the computer system to”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. The “hardware storage devices” , “instructions that are executable by one or more processors of a computer system to cause the computer system “ are all mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f). This does not integrate into a practical application, NOR does it provide significantly more.
As to claim 13, recites the additional element “wherein the same selected characteristic is a characteristic relating to a number of qubits that are associated with the quantum circuit”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 14, recites the additional element “wherein the ratio factor is stored in a lookup table along with an indication of a selected characteristic that the quantum circuit is determined to have”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 15, recites the additional element “wherein the selected characteristic is a number of qubits that the quantum circuit has such that the ratio factor is stored in the lookup table along with an indication regarding the determined number of qubits”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 16, recites the additional element “ wherein the new quantum circuit is determined to have a same number of qubits as said quantum circuit”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 17., “recites the additional element” wherein a same simulation engine executes the quantum circuit on the GPU and executes the quantum circuit on the CPU”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
Claims 18-20:
• Similar analysis as claim 1 applies to claims 18.
Further claim 18 recites the additional element “A computer system comprising: one or more processors; and one or more hardware storage devices that store instructions that are executable by the one or more processors to cause the computer system to”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. The “computer system” , “processors; and one or more hardware storage devices that store instructions that are executable by the one or more processors to cause the computer system “ are all mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f). This does not integrate into a practical application, NOR does it provide significantly more.
As to claim 19, recites the additional element “wherein a lookup table stores the ratio factor”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
As to claim 20, recites the additional element “ wherein selection of either the GPU or the CPU to execute the new quantum circuit is further based on a workload constraint”, which are merely recitations of generic computing components (see MPEP §2106.05(f)) which does not integrate a judicial exception into practical application. These elements represent no more than mere instructions to apply the judicial exception on a computer. Further, the claim does not contain any additional elements that comprise significantly more than the judicial exception. In particular, the additional elements identified above are merely recitations of generic computing components (see MPEP 2106.05(f)) which do not amount to significantly more. The claim is therefore not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Durazzo et al. (US 2021/0406151, Durazzo hereinafter) in view of Negishi et al. (US 2020/0065214, Negishi hereinafter).
As to claim 1, Durazzo teaches a method (see FIG. 1) comprising:
for a quantum circuit, determining a graphics processing unit (GPU) service-level-objective (SLO) metric for the quantum circuit when executed using a GPU (e.g., para 41, “ runtime statistics for a quantum circuit, such as execution time “, “quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes”
para [0032] estimate one or more runtime statistics for one or more quantum computing services, that is, the services provided as a result of execution of one or more quantum circuits. Such runtime statistics may include, but are not limited to, the execution time”, “ for “runtime statistics estimator to predict resource consumption of quantum circuits on different hardware, and then efficiently allocate clusters either in one datacenter or cross-datacenter”, “The service execution behavior obtained by the user may be based on the service, or group of services, chosen by the user for their computing tasks that need to be performed.” , “the real hardware group 200, to decide whether to use QPU, GPU, CPU” in para 9 and 27);
for the same quantum circuit, determining a central processing unit (CPU) SLO metric for the quantum circuit when executed using a CPU ( e.g., para 41, “ runtime statistics for a quantum circuit, such as execution time “, “quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes”
para 34, “ possible choices of processing resources may include, but are not limited to, QPUs, GPUs, and CPUs” and “ GPU may be an accelerated option, at least as compared to a CPU which may not run as quickly as a GPU. If GPU is not available, then a CPU may be employed as a fallback option. Thus, for quantum computing simulations, a hierarchy for the user of processors may be defined and employed.” In para 37) ;
for a new quantum circuit, estimating a new GPU SLO metric for the new quantum circuit (e.g., para 41, wherein “an estimator that may be operable to predict runtime statistics for a quantum circuit, such as execution time and memory space required” , “dynamic resource allocation in quantum simulation by way of a cluster orchestration engine that may employ execution data, such as entanglement from quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes.) ;
for the same new quantum circuit, deriving a new CPU SLO metric (e.g., para 41, wherein “ an estimator that may be operable to predict runtime statistics “, “ as execution time” for “ CPU and GPU resources for quantum simulation processes”. Thus, for the same new quantum circuit, deriving a new CPU SLO metric) ; and
based at least on the estimated new GPU SLO metric and the new CPU SLO metric, selecting either one of the GPU or the CPU to execute the new quantum circuit (e.g., para 41, wherein “an estimator that may be operable to predict runtime statistics for a quantum circuit, such as execution time and memory space required” , “dynamic resource allocation in quantum simulation by way of a cluster orchestration engine that may employ execution data, such as entanglement from quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes. “. Thus, based at least on the estimated new GPU SLO metric and the new CPU SLO metric, selecting either one of the GPU or the CPU to execute the new quantum circuit), [0027]. Some services may be relatively more dynamic and may allow the system, which may comprise the quantum simulation cluster 175 and the real hardware group 200, to decide whether to use QPU, GPU, CPU, or any combination of these”,.) .
However, Durazzo does not teach determining a ratio factor between the CPU SLO metric and the GPU SLO metric, applying the ratio factor to the estimated new GPU SLO metric.
Negishi teaches determining a ratio factor between the CPU SLO metric and the GPU SLO metric, deriving a new CPU SLO metric by applying the ratio factor to the estimated new GPU SLO metric (e.g., see FIG. 1, para 16, “ The application performance simulator 120 can include system ratio engine 122 and a system adjustor 124. The system ratio engine 122 can calculate the ratios of components in systems. The system adjustor 124 can adjust the system components to get a certain performance. The execution environment 110 can include a CPU 112 and a GPU 114 where clocks of the CPU 112 and clocks of the GPU 114 can be changed.” and [0017] The ratios of the system performance metrics can be determined by the system ratio engine 122. The ratios of the system performance metrics can include CPU execution speed on the target environment/CPU execution speed on the execution environment, GPU execution speed on the target environment/GPU execution speed on the execution environment, CPU-GPU communication speed on the target environment/CPU-GPU communication speed on the execution environment, GPU-GPU communication speed on the target environment/GPU-GPU communication speed on the execution environment).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Durazzo with those of Negishi because both references are directed to related systems addressing similar technical problems within the same field and seek to improve system performance, reliability, and efficiency.
Durazzo et al. disclose a for a quantum circuit, determining a graphics processing unit (GPU) service-level-objective (SLO) metric for the quantum circuit when executed using a GPU; for the same quantum circuit, determining a central processing unit (CPU) SLO metric for the quantum circuit when executed using a CPU. while Negishi et al. teaches determining a ratio factor between the CPU SLO metric and the GPU SLO metric.
Incorporating the teachings of Negishi et al. into the system of Durazzo et al. would have been a predictable and logical modification, yielding improved operational robustness and efficiency without requiring undue experimentation.
Such a combination would merely involve the substitution or integration of known elements performing their established functions, as taught by Negishi et al., into the system of Durazzo et al., consistent with design incentives and market demands for improved performance and scalability. Moreover, Negishi et al. explicitly recognize benefits to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17) . —that would naturally be desirable in the system of Durazzo et al.
Accordingly, to one of ordinary skill in the art would have had a reasonable expectation of success in combining Durazzo et al. with Negishi et al., and the combination represents no more than the predictable use of prior art elements according to their known functions.
As to claim 2, Durazzo teaches wherein the CPU SLO metric is a CPU execution time, wherein the GPU SLO metric is a GPU execution time, wherein the new CPU SLO metric is a new CPU execution time, and wherein the estimated new GPU SLO metric is a new GPU execution time. (e.g., abstract, estimating one or more runtime statistics concerning the code, generating a recommendation based on the one or more runtime statistics, and the recommendation identifies one or more resources recommended to be used to execute the quantum circuit, checking availability of the resources for executing the quantum circuit, allocating resources, when available, sufficient to execute the quantum circuit, and using the allocated resources to execute the quantum circuit.” and “an estimator may be provided that may predict runtime statistics of quantum algorithms, including the execution time” for “a pool of processing resources, such as RAM, CPUs, and GPUs, “ in para 10 and 39) .
As to claim 3, Durazzo teaches wherein determining the GPU execution time for the quantum circuit is performed by executing the quantum circuit using a simulation engine executing on the GPU (e.g., “, quantum simulation 179”, FIG. 1, para 16, “ GPUs may be used as accelerators in simulations”) , and wherein determining the CPU execution time for the quantum circuit is performed using the same simulation engine now executing on the CPU (e.g., para 27, “ the quantum simulation cluster 175 and the real hardware group 200, to decide whether to use QPU, GPU, CPU, or any combination of these” and para 37, “one or more QPUs may reside at a datacenter. As another example, one or more CPUs may reside on a laptop. It may be the case, in some circumstances at least, that the QPU is the most expensive processing resource, and may not always be available. Thus, when a real QPU is unavailable to support execution of a quantum algorithm, quantum computing simulation may be possible, depending upon the requirements of the quantum circuit to be executed. In such a case, a GPU may be an accelerated option, at least as compared to a CPU which may not run as quickly as a GPU. If GPU is not available, then a CPU may be employed as a fallback option. Thus, for quantum computing simulations, a hierarchy for the user of processors may be defined and employed”) .
As to claim 4, Durazzo teaches wherein the quantum circuit is one quantum circuit included in a defined group of quantum circuits, the defined group being defined based on a determination that all of the quantum circuits in the group share a same selected characteristic (e.g., para 27 “a quantum runtime group such as the quantum runtime group 125, “ , [0032] estimate one or more runtime statistics for one or more quantum computing services, that is, the services provided as a result of execution of one or more quantum circuits. Such runtime statistics may include, but are not limited to, the execution time and memory space consumption for the quantum computing services. Such estimates may be based on historical information for the same, or similar, quantum computing services.”, for “more QPUs may reside at a datacenter” in para 37. Thus, wherein the quantum circuit is one quantum circuit included in a defined group of quantum circuits, the defined group being defined based on a determination that all of the quantum circuits in the group share a same selected characteristic ) .
As to claim 5, Durazzo teaches further wherein the quantum circuit is selected from the group as a result of the GPU execution time for the quantumby one or more quantum circuits”, “the estimator may predict the time cost of that instruction, that is, the amount of time it will take to execute the instruction. The instruction costs may be summed to predict, for example, the time and/or memory space required by each quantum algorithm, that is, the code in the container 135. In cases where the quantum circuit will be run with quantum simulation, entanglement may be explicitly predicted from historical data”. Thus, the “ time cost” include “the quantum circuit being longest as compared to GPU execution times for other quantum circuits in said group”. Therefore wherein the quantum circuit is selected from the group as a result of the GPU execution time for the quantum circuit being longest as compared to GPU execution times for other quantum circuits in said group) .
As to claim 6, Durazzo teaches wherein a ‘quantum circuit’ embraces an executable computational routine that may include one or more quantum operations which may be performed on quantum data such as qubits.” . Thus, the “qubits.” Include the characteristic , therefore wherein the quantum circuit is selected to derive the new CPU execution time for the new quantum circuit based on a determination that the new quantum circuit and said quantum circuit share a same selected characteristic). However, Durazzo teaches the ratio factor . Negishi teaches the ratio factor ( see rejection of claim 1 above).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Durazzo by adopting the teachings of Negishi to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17).
As to claim 7, Durazzo teaches wherein the estimated new GPU execution time is shorter than the new CPU execution time (e.g., para 41, wherein “ dynamic resource allocation in quantum simulation by way of a cluster orchestration engine that may employ execution data, such as entanglement from quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes.”, “provide for fast error prediction on quantum circuits. Particularly, an embodiment may error out if a determination is made that there will not be sufficient resources to execute a quantum circuit, thus saving time for both the author of that circuit and for other users waiting for available resources”. Thus wherein the estimated new GPU execution time is shorter than the new CPU execution time.
As to claim 8, Durazzo teaches wherein, despite the new CPU execution time being longer than the estimated new GPU execution time, the CPU is selected to execute the new quantum circuit, and the CPU is selected based on consideration of at least one additional parameter (e.g., para 41, wherein “to predict runtime statistics for a quantum circuit, such as execution time “, “a cluster orchestration engine that may be operable to dynamically allocate, and release, resources based on estimated resources required for quantum circuits”, “dynamic resource allocation in quantum simulation by way of a cluster orchestration engine that may employ execution data, such as entanglement from quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes” . Thus, wherein, despite the new CPU execution time being longer than the estimated new GPU execution time, the CPU is selected to execute the new quantum circuit, and the CPU is selected based on consideration of at least one additional parameter).
As to claim 9, Durazzo does not teach wherein estimating the new GPU execution time for the new quantum circuit is performed using a trained model that is trained to predict GPU execution times (e.g., para 41, “ execution time “, “dynamic resource allocation in quantum simulation by way of a cluster orchestration engine that may employ execution data, such as entanglement from quantum simulation, to dynamically allocate, and release, CPU and GPU resources for quantum simulation processes” [0036] In another example implementation, an estimator may alternatively employ a top-down approach which may involve the use of machine learning (ML). In one embodiment of the top-down approach, the estimator may make one or more predictions based on previously defined ML models. These ML models may be trained by historical data from experimentations. Any embodiment of an estimator, including the aforementioned examples, may provide the quantum simulation cluster 175 with at least two predictions or inputs, namely, execution time for the quantum code, and memory space requirements for execution of the quantum code. Another input that may be generated by an estimator is processing requirements for execution of the quantum code. As noted earlier, the estimator may reside in the runtime cluster 125, although that is not necessarily required. Thus, the runtime cluster 125 may communicate directly with the quantum simulation cluster 175, and/or indirectly with the quantum simulation cluster 175, such as by way of the marketplace 150. Thus, wherein estimating the new GPU execution time for the new quantum circuit is performed using a trained model that is trained to predict GPU execution times).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Durazzo by adopting the teachings of Negishi to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17).
As to claim 10, Durazzo does not teach wherein the GPU execution time is one of multiple GPU execution times that were generated using a simulation engine executing on the GPU, and wherein said GPU execution time is an upper bound GPU execution time as a result of said GPU execution time being longest as compared to other GPU execution times included in said multiple GPU execution times.
However, Negishi teaches wherein the GPU execution time is one of multiple GPU execution times that were generated using a simulation engine executing on the GPU (e.g., see FIG. 3) , and wherein said GPU execution time is an upper bound GPU execution time as a result of said GPU execution time being longest as compared to other GPU execution times included in said multiple GPU execution times (e.g., see FIG. 3, para 26, “The performance of running the application can be an execution time of running the application (e.g., 243 milliseconds (ms))” , [0027] The target system simulator 300 can include the target system 310. The target system 310 can include the CPU 112, the GPU 114,) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Durazzo by adopting the teachings of Negishi to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17).
As to claim 11, as to claim 11, see rejection of claim 1 above . Durazzo teaches further One or more hardware storage devices that store instructions that are executable by one or more processors of a computer system to cause the computer system to ( see FIG. 3, [0072] In the example of FIG. 3, the physical computing device 400 includes a memory 402 which may include one, some, or all, of random access memory (RAM), non-volatile random access memory (NVRAM) 404, read-only memory (ROM), and persistent memory, one or more hardware processors 406, non-transitory storage media 408, UI device 410, and data storage 412. One or more of the memory components 402 of the physical computing device 400 may take the form of solid state device (SSD) storage. As well, one or more applications 414 may be provided that comprise instructions executable by one or more hardware processors 406 to perform any of the operations, or portions thereof, disclosed herein.)
As to claim 12, see rejection of claim 2 above.
As to claim 13, Durazzo teaches wherein the same selected characteristic is a characteristic relating to a number of qubits that are associated with the quantum circuit (e.g., see para 16, “n qubits by simulation” , “simulation of certain quantum circuits”, “ parallel processing, so GPUs may be used as accelerators in simulations” and “Quantum Circuit A collection of Qubits and Quantum Gates in a particular order”, [0038] In some embodiments, a quantum circuit may require more qubits for execution”, 0065] Embodiments of the invention may also employ various quantum components, examples of which are disclosed herein. Such quantum components comprise, for example, qubits, and QPUs. Quantum components may comprise hardware and/or software”
[0039] Suppose that there is a pool of processing resources, such as RAM, CPUs, and GPUs, available for different types of use cases, one of which is a quantum computing simulation”. Thus, wherein the same selected characteristic is a characteristic relating to a number of qubits that are associated with the quantum circuit ).
As to claim 14, Durazzo teaches further a lookup table along with an indication of a selected characteristic that the quantum circuit is determined to have (e.g., [0029] Note that the quantum binary 131 comprises quantum code, rather than any hardware, although a quantum binary may also be referred to herein as a quantum circuit. Thus, as used herein, a ‘quantum circuit’ embraces an executable computational routine that may include one or more quantum operations which may be performed on quantum data such as qubits., para 38, “a quantum circuit may require more qubits for execution than are available”. Thus, the “quantum data such as qubits” include an indication of a selected characteristic ). However, Durazzo does not teach the ratio factor. Negishi teaches wherein the ratio factor (see rejection of claim 1 above.) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Durazzo by adopting the teachings of Negishi to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17).
As to claim 15, Durazzo teaches wherein the selected characteristic is a number of qubits that the quantum circuit has , is stored in the lookup table along with an indication regarding the determined number of qubits (e.g., para 16 and 18, “to store the data of n qubits by simulation, roughly 2.sup.n bits would be needed”, “hardware resource allocation for quantum computing simulations “, “each iteration of quantum algorithm development may impact the number of qubits required for execution of the updated algorithm” para [0022], , TABLE-US-00001 Term Definition Qubit A qubit is a two-dimensional complex vector with norm 1”, “Quantum Circuit A collection of Qubits and Quantum Gates in a particular order”) . However, Negishi teaches wherein the ratio factor (see rejection of claim 1 above.) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Durazzo by adopting the teachings of Negishi to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17).
As to claim 16, Durazzo teaches wherein the new quantum circuit is determined to have a same number of qubits as said quantum circuit. (e.g., para 18, “quantum circuits may require different amount of resources based on the number of qubits consumed by the quantum circuits”, “hardware resource allocation for quantum computing simulations “, “each iteration of quantum algorithm development may impact the number of qubits required for execution of the updated algorithm” para 22, “ Qubit A qubit is a two-dimensional complex vector with norm 1”, “When qubits are read, superposition and entanglement data is collapsed to a 0 or 1 in a probabilistic way”, “Quantum Circuit A collection of Qubits and Quantum Gates in a particular order” and “a ‘quantum circuit’ embraces an executable computational routine that may include one or more quantum operations which may be performed on quantum data such as qubits” in para 29. Thus, herein the new quantum circuit is determined to have a same number of qubits as said quantum circuit).
As to claim 17, Durazzo teaches wherein a same simulation engine executes the quantum circuit on the GPU and executes the quantum circuit on the CPU (e.g., para 27, “services may be relatively more dynamic and may allow the system, which may comprise the quantum simulation cluster 175 and the real hardware group 200, to decide whether to use QPU, GPU, CPU, or any combination of these.”) .
As to claim 18, Durazzo teaches further a computer system comprising: one or more processors; and one or more hardware storage devices that store instructions that are executable by the one or more processors to cause the computer system to ( see FIG. 3, [0072] In the example of FIG. 3, the physical computing device 400 includes a memory 402 which may include one, some, or all, of random access memory (RAM), non-volatile random access memory (NVRAM) 404, read-only memory (ROM), and persistent memory, one or more hardware processors 406, non-transitory storage media 408, UI device 410, and data storage 412. One or more of the memory components 402 of the physical computing device 400 may take the form of solid state device (SSD) storage. As well, one or more applications 414 may be provided that comprise instructions executable by one or more hardware processors 406 to perform any of the operations, or portions thereof, disclosed herein.).
As to claim 19, Durazzo does not teach the lookup table stores the ratio factor . Negishi teaches wherein a lookup table stores the ratio factor (e.g., see claim 10, wherein “ The non-transitory computer-readable storage medium “, “generating a maximum ratio from the system performance metrics for the target system and the execution system for the ratio of estimation” . Thus, wherein a lookup table stores the ratio factor . Negishi teaches wherein a lookup table stores the ratio factor must be included ) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Durazzo by adopting the teachings of Negishi to enable “an estimate of the execution time on the target environment can be more accurately measured.” (see Negishi, in para 17).
As to claim 20. , Durazzo teaches wherein selection of either the GPU or the CPU to execute the new quantum circuit is further based on a workload constraint (e.g., para 42, “when private datacenters are running out of resources to service quantum computing workloads, those workloads may burst out into public clouds and other private datacenters”. Thus, wherein selection of either the GPU or the CPU to execute the new quantum circuit is further based on a workload constraint) .
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mozafari Ghoraba et al. (US 2025/0061360) discloses systems and methods for decomposition of quantum oracles for simulating quantum circuits are provided. A simulation platform may receive as input a representation of a quantum circuit that comprises decomposable Boolean functions that define a quantum oracle and convert a Boolean representation of the quantum oracle to a set of Boolean functions. The Boolean functions may be used to create an oracle tensor network (e.g., a MPO sub-tensor network) comprising an exact representation of the Boolean representation of the quantum oracle. The oracle tensor network representation may be incorporated into a tensor network representation of the quantum circuit and passed to the simulation platform in order to simulate the quantum circuit.
Jones et al. (US 2024/0311667) discloses systems and methods for simulating quantum circuits using sparse state partitioning are provided. The quantum state of a quantum circuit may be partitioned into one or more state vector partition candidates that may form sparse state partitions that avoid memory operations for one or more state elements of the quantum circuit's state vector. Gate grouping, gate complexity, and/or qubit ordering optimization algorithms may be applied and the state vector partition candidate evaluated against a computing platform topology profile using a cost evaluation function. The cost evaluation function may estimate an efficiency associated with executing that state vector partition candidate given the processing resources of the currently available simulation platform for running the simulation. A state vector partition candidate optimized for the simulation platform may be passed to the simulation platform as a set of state vector partitions in order to simulate the quantum circuit..
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/ABDOU K SEYE/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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