DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 01/23/2024 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 11-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KOPPASSERY et al. (U.S. 2023/0129287).
Regarding claim 1, KOPPASSERY et al. (hereinafter, Ref~287) discloses (please see Fig. 3 and related text for details) a bias voltage generating circuit (310 of Fig. 3), comprising:
a first circuit subunit (centered by M1/326 of Fig. 3), arranged to generate a first bias voltage (disposed at gate of transistor 346 of Fig. 3) at a first node (349 of Fig. 3) in response to a first current (e.g., drain current of M1/326 of Fig. 3) and a first input voltage (e.g., see voltage Vref at node 325 applied at the drain of M1/326 of Fig. 3);
a second circuit subunit (centered by M2/346 of Fig. 3), coupled to the first circuit subunit, and arranged to receive the first bias voltage and generate a second current (drain current of M2/346 of Fig. 3) flowing through a second node (Vref at node 345 of Fig. 3), wherein the second current is mirrored from the first current (please note that M1/M2 received the same bias voltage at the gate thus supporting the broadly claimed mirrored); and
a third circuit subunit (centered by M3/342 of Fig. 3), coupled to the second node (345 of Fig. 3), and arranged to generate a second bias voltage (voltage disposed the gate 372 of Fig. 3) at a third node (common node of 364/365 of Fig. 3) in response to the second current and a second input voltage (Vref of Fig. 3), meeting claim 1.
Regarding claim 2, Ref~287 discloses the bias voltage generating circuit of claim 1, wherein the first input voltage and the second input voltage are the same voltage as seen from Fig. 3, meeting claim 2.
Regarding claim 11, Ref~287 discloses (please see Fig. 3) a bias voltage generating circuit (310 of Fig. 3), comprising:
a first circuit subunit (centered by M1 of Fig. 3), arranged to generate a first bias voltage (voltage disposed at gate of M2 of Fig. 3) at a first node (349 of Fig. 3) in response to a first current (drain current of M1 of Fig. 3) and a first input voltage (e.g., Vref of Fig. 3);
a second circuit subunit (centered by M2 of Fig. 3), coupled to the first circuit subunit, and arranged to receive the first bias voltage, and generate a second current (drain current of M2 of Fig. 3) flowing through a second node (node 345 of Fig. 3), wherein the second current is mirrored from the first current (please note that M1/M2 received the same bias voltage at the gate thus supporting the broadly claimed mirrored); and
a third circuit subunit (centered by M3 of Fig. 3), coupled to the second node, and arranged to generate a second bias voltage (voltage disposed at gate of 372 of Fig. 3) at a third node (common node of 364/365 of Fig. 3) in response to the second current and a second input voltage (Vref of Fig. 3);
wherein the first node is further coupled to a first bias voltage input terminal of a power amplifier circuit (centered by transistor 374 of Fig. 3), and is arranged to provide the first bias voltage to the power amplifier circuit, and the third node is further coupled to a second bias voltage input terminal (gate of cascode transistor 372 of Fig. 3) of the power amplifier circuit, and is arranged to provide the second bias voltage to the power amplifier circuit as seen, meeting claim 11.
Regarding claim 12, Ref~287 discloses the bias voltage generating circuit of claim 11, wherein the first input voltage and the second input voltage are the same voltage (Vref of Fig. 3) as seen from Fig. 3, meeting claim 12.
Allowable Subject Matter
Claims 3-10 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
Prosecution Insights