Prosecution Insights
Last updated: July 17, 2026
Application No. 18/420,844

INFORMATION PROCESSING APPARATUS AND QUANTUM CIRCUIT GENERATION METHOD

Non-Final OA §101§103
Filed
Jan 24, 2024
Priority
Aug 19, 2021 — continuation of PCTJP2130458 +1 more
Examiner
LEE, CLAY C
Art Unit
Tech Center
Assignee
Fujitsu Limited
OA Round
1 (Non-Final)
55%
Grant Probability
Moderate
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 55% of resolved cases
55%
Career Allowance Rate
125 granted / 229 resolved
-5.4% vs TC avg
Strong +58% interview lift
Without
With
+57.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
36 currently pending
Career history
278
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
92.3%
+52.3% vs TC avg
§102
4.2%
-35.8% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 229 resolved cases

Office Action

§101 §103
DETAILED ACTION Claim Status This is first office action on the merits in response to the application filed on 1/24/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-6 are currently pending and have been examined. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 1/24/2024, 9/10/2024, and 12/11/2025 is(are) in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-6 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Under the Step 1 of the Section 101 analysis, Claims 1-4 are drawn to an apparatus which is within the four statutory categories (i.e. a machine), Claim 5 is drawn to a method which is within the four statutory categories (i.e., a process), and Claim 6 is drawn to a non-transitory computer-readable medium which is within the four statutory categories (i.e., a manufacture). Since the claims are directed toward statutory categories, it must be determined if the claims are directed towards a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea). Based on consideration of all of the relevant factors with respect to the claim as a whole, claims 1-6 are determined to be directed to an abstract idea. The rationale for this determination is explained below: Regarding Claims 1 and 5-6: Claims 1 and 5-6 are drawn to an abstract idea without significantly more. The claims recite “generate a matrix including a plurality of rows corresponding to the plurality of qubits and a plurality of columns corresponding to the plurality of projection operators based on the plurality of projection operators indicated by the operator information; execute diagonalization that converts the matrix into a diagonal matrix through a row operation, the row operation selecting two rows out of the plurality of rows based on the connection relationships indicated by the layout information and using one of the two rows to update the other row; and generate a quantum circuit indicating gate operations for the quantum device based on the row operation performed during the diagonalization.” Under the Step 2A Prong One, the limitations, as underlined above, are processes that, under its broadest reasonable interpretation, cover Mathematical Concepts such as mathematical relationships, mathematical formulas or equations, or mathematical calculations. For example, but for the “qubits” and “generate a quantum circuit indicating gate operations for the quantum device based on the row operation performed during the diagonalization” language, the underlined limitations in the context of this claim encompass the human activity or mental processes. The series of steps belong to a typical mathematical calculations. Under the Step 2A Prong Two, this judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements – “An information processing apparatus comprising: a memory configured to store operator information, which indicates a plurality of projection operators, each of which is indicated by a combination of a plurality of Pauli operators, and layout information, which indicates connection relationships between a plurality of qubits included in a quantum device; and a processor coupled to the memory and the processor configured to:”, “A quantum circuit generation method comprising: … by a processor”, “A non-transitory computer-readable recording medium storing therein a computer program that causes a computer to execute a process comprising:”, “qubits”, and “generate a quantum circuit indicating gate operations for the quantum device based on the row operation performed during the diagonalization”. The additional elements are recited at a high-level of generality (i.e., performing generic functions of an interaction) such that it amounts no more than mere instructions to apply the exception using a generic computer component, merely implementing an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea. Additionally, regarding the specification and claims, there is no improvement in the functioning of a computer or an improvement to other technology or technical field present, there is no applying or using the judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition present, there is no implementing the judicial exception with or using the judicial exception in conjunction with a particular machine or manufacture that is integral to the claim present, there is no effecting a transformation or reduction of a particular article to a different state or thing present, and there is no applying or using the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment present such that the claim as a whole is more than a drafting effort designed to monopolize the exception. Accordingly, these additional elements, individually or in combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea. Under the Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements in the process amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible. Regarding Claims 2-4: Dependent claims 2-4 include additional limitations, for example, “qubits” and “quantum device” (Claim 2); “qubits” (Claim 3); and “qubits” (Claim 4);, but none of these limitations are deemed significantly more than the abstract idea because, as stated above, they require no more than generic computer structures or signals to be executed, and do not recite any Improvements to the functioning of a computer, or Improvements to any other technology or technical field. Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Furthermore, looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology, and their collective functions merely provide conventional computer implementation or implementing the judicial exception on a generic computer. Therefore, whether taken individually or as an ordered combination, claims 2-4 are nonetheless rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over McClean (US 11894860 B2) in view of Hamamura (US20200242290A1; already of record in IDS), in further view of Kliuchnikov (US 20190378032 A1). Regarding Claims 1 and 5-6, McClean teaches An information processing apparatus comprising (McClean: Abstract): a memory configured to store operator information, which indicates a plurality of projection operators, each of which is indicated by a combination of a plurality of Pauli operators, and layout information, which indicates connection relationships between a plurality of qubits included in a quantum device (McClean: Col. 17, lines 28-45; 19/48-58; 2/39-42; 18/32-49; 1/15-30; 7/1-13); and a processor coupled to the memory and the processor configured to (McClean: 7/56-67): A quantum circuit generation method comprising (McClean: Abstract): A non-transitory computer-readable recording medium storing therein a computer program that causes a computer to execute a process comprising (McClean: 17/28-45; 19/48-58): generate a matrix including a plurality of rows corresponding to the plurality of qubits and a plurality of columns corresponding to the plurality of projection operators based on the plurality of projection operators indicated by the operator information (McClean: 3/26-39; 1/37-56; 14/25-50; 17/5-14); execute [diagonalization] that converts the matrix into a diagonal matrix through a [row] operation, the [row] operation selecting two rows out of the plurality of rows based on the connection relationships indicated by the layout information and using one of the two rows to update the other row (McClean: 14/25-50); and generate a quantum circuit indicating gate operations for the quantum device based on the [row] operation performed during the diagonalization (McClean: 4/50-63; 17/5-45). However, McClean does not explicitly teach diagonalization. Hamamura from same or similar field of endeavor teaches diagonalization (Hamamura: Paragraph(s) 0086-0095, 0102). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of McClean to incorporate the teachings of Hamamura for diagonalization. There is motivation to combine Hamamura into McClean because Hamamura’s teachings of diagonalization would facilitate processing of Pauli strings (Hamamura: Paragraph(s) 0086-0095, 0102). However, the combination of McClean and Hamamura does not explicitly teach row operation. Kliuchnikov from same or similar field of endeavor teaches row operation (Kliuchnikov: Paragraph(s) 0109-0110, 0160). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of McClean and Hamamura to incorporate the teachings of Kliuchnikov for row operation. There is motivation to combine Kliuchnikov into the combination of McClean and Hamamura because Kliuchnikov’s teachings of row operation would facilitate processing qubits (Kliuchnikov: Paragraph(s) 0109-0110, 0160). Regarding Claim 2, the combination of McClean, Hamamura, and Kliuchnikov teaches all the limitations of claim 1 above; however the combination does not explicitly teach wherein the two rows selected by the row operation correspond to two qubits that are interconnected in the quantum device, out of the plurality of qubits. Kliuchnikov further teaches wherein the two rows selected by the row operation correspond to two qubits that are interconnected in the quantum device, out of the plurality of qubits (Kliuchnikov: Paragraph(s) 0108-0115, 0160). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of McClean, Hamamura, and Kliuchnikov to incorporate the teachings of Kliuchnikov for row operation. There is motivation to combine Kliuchnikov into the combination of McClean, Hamamura, and Kliuchnikov because Kliuchnikov’s teachings of processing of connectivity of qubits through row operation would facilitate processing qubits (Kliuchnikov: Paragraph(s) 0108-0115, 0160). Regarding Claim 3, the combination of McClean, Hamamura, and Kliuchnikov teaches all the limitations of claim 1 and diagonalization above; and McClean further teaches wherein the plurality of qubits include a first qubit, a second qubit that is connected to the first qubit, and a third qubit that is connected to the second qubit but is not connected to the first qubit (McClean: 7/1-67). However, the combination of McClean, Hamamura, and Kliuchnikov does not explicitly teach the [diagonalization] includes deleting, upon determining that a first row corresponding to the first qubit and a third row corresponding to the third qubit out of the plurality of rows include non-zero elements in the same column, non-zero elements in the third row by performing a first row operation on the first row and a second row corresponding to the second qubit and a second row operation on the second row and the third row. Kliuchnikov further teaches deleting, upon determining that a first row corresponding to the first qubit and a third row corresponding to the third qubit out of the plurality of rows include non-zero elements in the same column, non-zero elements in the third row by performing a first row operation on the first row and a second row corresponding to the second qubit and a second row operation on the second row and the third row (Kliuchnikov: Paragraph(s) 0136-0139, 0110, 0160). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of McClean, Hamamura, and Kliuchnikov to incorporate the teachings of Kliuchnikov for deleting, upon determining that a first row corresponding to the first qubit and a third row corresponding to the third qubit out of the plurality of rows include non-zero elements in the same column, non-zero elements in the third row by performing a first row operation on the first row and a second row corresponding to the second qubit and a second row operation on the second row and the third row. There is motivation to combine Kliuchnikov into the combination of McClean, Hamamura, and Kliuchnikov because Kliuchnikov’s teachings of processing of connectivity of qubits through row operation would facilitate processing qubits (Kliuchnikov: Paragraph(s) 0108-0115, 0160). Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over McClean (US 11894860 B2) in view of Hamamura (US20200242290A1; already of record in IDS) in further view of Kliuchnikov (US 20190378032 A1), and in still further view of Jiang (WO 2020131798 A1). Regarding Claim 4, the combination of McClean, Hamamura, and Kliuchnikov teaches all the limitations of claim 1 and diagonalization above; and McClean further teaches wherein the plurality of qubits include a first qubit and at least two second qubits located at respectively different numbers of hops from the first qubit (McClean: 7/1-67). However, the combination of McClean, Hamamura, and Kliuchnikov does not explicitly teach determining that out of the plurality of rows, a first row corresponding to the first qubit and at least two second rows corresponding to the at least two second qubits include a non-zero element in a same column, a row operation for deleting the non-zero elements preferentially from the second row corresponding to the second qubit with the highest number of hops out of the at least two second rows. Jiang from same or similar field of endeavor teaches executing, upon determining that out of the plurality of rows, a first row corresponding to the first qubit and at least two second rows corresponding to the at least two second qubits include a non-zero element in a same column, a row operation for deleting the non-zero elements preferentially from the second row corresponding to the second qubit with the highest number of hops out of the at least two second rows (Jiang: Paragraph(s) 00029, 00046, 00061, 00072). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of McClean, Hamamura, and Kliuchnikov to incorporate the teachings of Jiang for determining that out of the plurality of rows, a first row corresponding to the first qubit and at least two second rows corresponding to the at least two second qubits include a non-zero element in a same column, a row operation for deleting the non-zero elements preferentially from the second row corresponding to the second qubit with the highest number of hops out of the at least two second rows. There is motivation to combine Jiang into the combination of McClean, Hamamura, and Kliuchnikov because Jiang’s teachings of hopping graph would facilitate processing qubits (Jiang: Paragraph(s) 00029, 00046, 00061, 00072) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CLAY LEE whose telephone number is (571)272-3309. The examiner can normally be reached Monday-Friday 8-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Neha Patel can be reached at (571)270-1492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CLAY C LEE/Primary Examiner, Art Unit 3699
Read full office action

Prosecution Timeline

Jan 24, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §101, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12651255
TRANSACTION MESSAGING
1y 11m to grant Granted Jun 09, 2026
Patent 12647352
VERIFICATION OF DATA PROCESSES IN A NETWORK OF COMPUTING RESOURCES
2y 7m to grant Granted Jun 02, 2026
Patent 12639734
System, Device, and Method of Protected Electronic Commerce and Electronic Financial Transactions
6y 0m to grant Granted May 26, 2026
Patent 12632853
PAYMENT AUTHENTICATION SYSTEM FOR ELECTRONIC COMMERCE TRANSACTIONS
2y 1m to grant Granted May 19, 2026
Patent 12626245
SYSTEMS AND METHODS FOR DISTRIBUTED LEDGER-BASED IDENTITY MANAGEMENT
1y 5m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
55%
Grant Probability
99%
With Interview (+57.8%)
3y 4m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 229 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month