Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed 01/24/2024. Claims 1-13 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior filed application EP23 15 5568.1, filed 02/08/2023, is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted 01/24/2024, have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The following claims lack antecedent basis:
Claim 2, line 3, the phrase “the output value”.
The following claims are indefinite:
Regarding claim 1,
The preamble of Claim 1 recites “a hardware metric predictor configured to predict a hardware metric”, “the hardware metric predictor being configured to receive as input a query description of a neural network architecture and a ground truth set”, and “the hardware metric predictor being configured to produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware” (Lines 1, 4-10). The subsequent recitation in the claim body of “the hardware metric predictor” creates ambiguity as to the precise structural scope being modified. It is unclear to a person of ordinary skill in the art whether “the hardware metric predictor” is restricted exclusively to a hardware metric predictor configured to predict a hardware metric, receive as input a query description of a neural network architecture and a ground truth set, and produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware, as detailed in the preamble, or if it generically encompasses any hardware metric predictor. Because the metes and bounds of the claimed element cannot be reasonably ascertained, the claim is indefinite. For the purposes of examination, examiner will interpret the “hardware metric predictor” as configured to predict a hardware metric, receive as input a query description of a neural network architecture and a ground truth set, and produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware.
The preamble of Claim 1 also recites “a hardware metric, the hardware metric representing a cost of running a particular neural network architecture on target hardware” and “a predicted hardware metric” (Lines 2-4 & 7-8). The subsequent recitation in the claim body of “the hardware metric” creates ambiguity as to the precise structural scope being modified. It is unclear to a person of ordinary skill in the art whether “the hardware metric” is restricted exclusively to a hardware metric representing a cost of running a particular neural network architecture on target hardware, as detailed in the preamble, or if it generically encompasses any hardware metric. Because the metes and bounds of the claimed element cannot be reasonably ascertained, the claim is indefinite. For the purposes of examination, examiner will interpret the “hardware metric” as a hardware metric representing a cost of running a particular neural network architecture on target hardware.
Regarding claim 12,
The preamble of Claim 12 recites “a hardware metric predictor configured to predict a hardware metric”, “the hardware metric predictor being configured to receive as input a query description of a neural network architecture and a ground truth set”, and “the hardware metric predictor being configured to produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware” (Lines 3-12). The subsequent recitation in the claim body of “the hardware metric predictor” creates ambiguity as to the precise structural scope being modified. It is unclear to a person of ordinary skill in the art whether “the hardware metric predictor” is restricted exclusively to a hardware metric predictor configured to predict a hardware metric, receive as input a query description of a neural network architecture and a ground truth set, and produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware, as detailed in the preamble, or if it generically encompasses any hardware metric predictor. Because the metes and bounds of the claimed element cannot be reasonably ascertained, the claim is indefinite. For the purposes of examination, examiner will interpret the “hardware metric predictor” as configured to predict a hardware metric, receive as input a query description of a neural network architecture and a ground truth set, and produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware.
The preamble of Claim 12 also recites “a hardware metric, the hardware metric representing a cost of running a particular neural network architecture on target hardware” and “a predicted hardware metric” (Lines 4-6 & 10). The subsequent recitation in the claim body of “the hardware metric” creates ambiguity as to the precise structural scope being modified. It is unclear to a person of ordinary skill in the art whether “the hardware metric” is restricted exclusively to a hardware metric representing a cost of running a particular neural network architecture on target hardware, as detailed in the preamble, or if it generically encompasses any hardware metric. Because the metes and bounds of the claimed element cannot be reasonably ascertained, the claim is indefinite. For the purposes of examination, examiner will interpret the “hardware metric” as a hardware metric representing a cost of running a particular neural network architecture on target hardware.
Regarding claim 13,
The preamble of Claim 13 recites “a hardware metric predictor configured to predict a hardware metric”, “the hardware metric predictor being configured to receive as input a query description of a neural network architecture and a ground truth set”, and “the hardware metric predictor being configured to produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware” (Lines 6-16). The subsequent recitation in the claim body of “the hardware metric predictor” creates ambiguity as to the precise structural scope being modified. It is unclear to a person of ordinary skill in the art whether “the hardware metric predictor” is restricted exclusively to a hardware metric predictor configured to predict a hardware metric, receive as input a query description of a neural network architecture and a ground truth set, and produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware, as detailed in the preamble, or if it generically encompasses any hardware metric predictor. Because the metes and bounds of the claimed element cannot be reasonably ascertained, the claim is indefinite. For the purposes of examination, examiner will interpret the “hardware metric predictor” as configured to predict a hardware metric, receive as input a query description of a neural network architecture and a ground truth set, and produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware.
The preamble of Claim 13 also recites “a hardware metric, the hardware metric representing a cost of running a particular neural network architecture on target hardware” and “a predicted hardware metric” (Lines 6-9 & 13-14). The subsequent recitation in the claim body of “the hardware metric” creates ambiguity as to the precise structural scope being modified. It is unclear to a person of ordinary skill in the art whether “the hardware metric” is restricted exclusively to a hardware metric representing a cost of running a particular neural network architecture on target hardware, as detailed in the preamble, or if it generically encompasses any hardware metric. Because the metes and bounds of the claimed element cannot be reasonably ascertained, the claim is indefinite. For the purposes of examination, examiner will interpret the “hardware metric” as a hardware metric representing a cost of running a particular neural network architecture on target hardware.
Regarding claims 2-11,
Claims 2-11 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ),
second paragraph, as being indefinite for depending on an indefinite parent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-9, & 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. ("HELP: Hardware-Adaptive Efficient Latency Prediction for NAS via Meta-Learning", 35th Conference on Neural Information Processing Systems, arXiv) (Year: 2021), hereafter Lee, in view of Müller et al. ("TRANSFORMERS CAN DO BAYESIAN INFERENCE", ICLR 2022, OpenReview) (Year: 2022), hereafter Müller.
Regarding independent claim 1, Lee teaches a method using a hardware metric predictor configured to predict a hardware metric, the hardware metric representing a cost of running a particular neural network architecture on target hardware ([Abstract] discusses a hardware-adaptive efficient latency predictor which predicts a hardware cost metric of running a neural network architecture on a given target device), the hardware metric predictor being configured to receive as input a query description of a neural network architecture and a ground truth set ([Sec. 3 & Fig. 2] discusses the predictor taking an encoded query architecture and a hardware embedding built from a number of architecture-latency pairs which constitutes a ground truth set), the hardware metric predictor being configured to produce as output a predicted hardware metric predicted to be incurred by a neural network corresponding to the query description when run on the target hardware ([Abstract & Sec. 3] discusses outputting a predicted estimated latency for the query architecture on an “unseen” target device), the ground truth set including a number of pairs, each of the pairs including a ground truth description of a ground truth neural network architecture and a ground truth hardware metric incurred by a neural network corresponding to the ground truth description when run on the target hardware ([Sec. 3] discusses a ground truth set in which the hardware device is specified, and ground truth pairs comprising a set of neural architectures and a set of latencies, a hardware metric, measured on the hardware device), comprising:
training the hardware metric predictor, including: obtaining multiple different training functions, each training function receiving as input a training description of a neural network architecture and generating as output a value dependent upon the input ([Sec. 3.2-3.3] discusses a meta-training “source device pool” in which during training, the different training functions are randomly obtained with each comprising a training description of the neural architecture as input and generates an output corresponding to the input);
iterating over the multiple different training functions, including: given a training function of the multiple different training functions for training the hardware metric predictor, training the hardware metric predictor to, given as training input a number of input/output pairs of the given training function and a further input, produce output for the further input, the further input including a further description of a neural network architecture ([Sec. 3.2-3.3] discusses iterating over each targeted device taking a training set as input comprising neural architecture and its ground truth pair, which includes a number of input/output pairs, to output an output corresponding to the input);
and neural network designing, including: sampling multiple candidate neural network architectures, predicting the hardware metric of the multiple candidate neural network architectures with the trained hardware metric predictor, selecting a neural network architecture from the multiple candidate neural network architecture using the predicted hardware metrics ([Sec. 4.2-5 & Fig. 1] discusses sampling multiple candidate architectures and their latencies are predicted using the trained hardware metric predictor; further, the “obtained” architecture is selected from the candidates using the latency or hardware metrics).
Lee does not explicitly teach produce as output a prediction of the given training function output for the further input.
However, in the same field of endeavor, Müller teaches a method of metric prediction using PFNs, wherein during training, output is produced as a prediction of the input ([Abstract & Sec. 1-2] discusses iteratively looping through training; for each function a set of (x, y) pairs is sampled, one label is masked, and the network is trained to output a prediction of the training function output for the further input).
Because Lee teaches obtaining multiple different training functions, each training function receiving as input a training description of a neural network architecture and generating as output a value dependent upon the input, training the hardware metric predictor to, given as training input a number of input/output pairs of the given training function and a further input, produce output for the further input, the further input including a further description of a neural network architecture, and sampling multiple candidate neural network architectures, predicting the hardware metric of the multiple candidate neural network architectures with the trained hardware metric predictor, selecting a neural network architecture from the multiple candidate neural network architecture using the predicted hardware metrics; and Müller teaches a method of metric prediction using PFNs, wherein during training, output is produced as a prediction of the input, accordingly, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate during training, output is produced as a prediction of the input as taught by Müller into Lee’s hardware-implemented method, with a reasonable expectation of success, to teach training the hardware metric predictor, including: obtaining multiple different training functions, each training function receiving as input a training description of a neural network architecture and generating as output a value dependent upon the input, iterating over the multiple different training functions, including: given a training function of the multiple different training functions for training the hardware metric predictor, training the hardware metric predictor to, given as training input a number of input/output pairs of the given training function and a further input, produce as output a prediction of the given training function output for the further input, the further input including a further description of a neural network architecture; and neural network designing, including: sampling multiple candidate neural network architectures, predicting the hardware metric of the multiple candidate neural network architectures with the trained hardware metric predictor, selecting a neural network architecture from the multiple candidate neural network architecture using the predicted hardware metrics. This combination would have been motivated by the desire to allow for accurate capture of uncertainty, make use of simple prior modeling, and reduce computational burden by leveraging specifications of prior knowledge due to training predictions on the input (Müller [Abstract & Sec. 2]).
Regarding dependent claim 2, the combination of Lee and Müller teaches the invention as claimed in claim 1, including:
wherein training the hardware metric predictor further includes: computing the output value of the given training function applied to multiple training descriptions of a neural network architecture (Müller [Abstract & Sec. 1-2] discusses a training loop in which a function the prior is drawn and evaluated for a batch of sampled inputs; thus, the loop computes training function outputs for multiple sampled inputs of a neural architecture);
constructing the training input for the hardware metric predictor, the training input including a sequence of pairs of a training description of a neural network architecture, and a corresponding computed output value, and a further input including a description of a neural network architecture (Lee [Sec. 3 & Fig. 2] discusses the predictor taking an encoded query architecture and a hardware embedding built from a training description of the neural architecture and a number of architecture-latency pairs which constitutes a ground truth set; the ground truth set in which the hardware device is specified, and ground truth pairs comprising a set of neural architectures and a set of latencies, a hardware metric, measured on the hardware device; Müller [Abstract & Sec. 1-2] discusses a given prior, which is a previously computed output, being used as an input, and the network inputs are constructed as the full set of samples);
constructing a training output for the hardware metric predictor, the training output including the corresponding computed output value for the at least one further training description of a neural network architecture (Müller [Abstract & Sec. 1-2] discusses training the network to predict the masked label; thus, the training output includes the computed output value for the further query input of the neural architecture);
and training the hardware metric predictor on the training input and the training output (Müller [Abstract & Sec. 1-2] discusses training the transformer neural network, which acts as the hardware metric predictor, end-to-end via a loss between the predicted and true masked label; thus, the input and output pair).
Regarding dependent claim 3, the combination of Lee and Müller teaches the invention as claimed in claim 1, including:
obtaining a target accuracy metric (Lee [Sec. 2, Table 4 & Fig. 6] discusses the use of a target accuracy metric to measure the trade-off between accuracy and latency);
predicting an accuracy metric of each of the multiple candidate neural network architectures with an accuracy metric predictor (Lee [Table 4 & Fig. 6] discusses predicting the accuracy for each multiple candidate neural architectures with the predictor);
and selecting the neural network architecture further using the predicted accuracy metrics and the target accuracy metric (Lee [Sec. 4.2] discusses accuracy-latency trade-off results and a “predictor-guided evolutionary” are used to select architectures balancing predicted accuracy with the targeted metrics).
Regarding dependent claim 4, the combination of Lee and Müller teaches the invention as claimed in claim 1, including wherein the hardware metric predictor includes a neural network (Lee [Sec. 3] discusses the HELP latency predictor is a learned neural network; Müller [Sec. 3] discusses initializing the neural network and specifically, it is a variant of a transformer architecture).
Regarding dependent claim 5, the combination of Lee and Müller teaches the invention as claimed in claim 1, including wherein the hardware metric predictor includes a transformer neural network (Müller [Sec. 3] discusses initializing the neural network and specifically, it is a variant of a transformer architecture).
Regarding dependent claim 6, the combination of Lee and Müller teaches the invention as claimed in claim 1, including wherein the hardware metric includes any of the following: memory usage, energy consumption, latency (Lee [Abstract & Sec. 3] discusses HELP is specifically designed for latency estimation but generally can also be used for energy consumption and memory).
Regarding dependent claim 8, the combination of Lee and Müller teaches the invention as claimed in claim 1, including wherein at least a part of the multiple different training functions are functions according to a same parametrized class of functions, wherein the obtaining of the multiple different training functions includes sampling a parametrization, and the obtaining a training function from a parametrized class of functions according to the sampled parametrization (Müller [Sec. 1-2, 5, & 6] discusses each training class is built off a function class such as Gaussian processes (RBF Kernel) or Bayesian Neural Networks, which constitutes sampling a parameterization; further, the training procedure samples member functions of this parameterized class and draws data from these samples; thus, at least a part of the training functions are functions according to a same parameterized class of functions and the obtaining of these functions are based on the sampled parameterization).
Regarding dependent claim 9, the combination of Lee and Müller teaches the invention as claimed in claim 8, including wherein the parametrized class of functions includes: a parametrized class of polynomials, and/or a parametrized class of neural networks, and/or a parametrized class of graph neural networks (Müller [Sec. 1-2, 5, & 6] discusses sampling a prior for the parameterized class of functions that is built off Gaussian processes or Bayesian Neural Networks; thus, the parameterized class of functions includes a parameterized class of neural networks).
Regarding dependent claim 11, the combination of Lee and Müller teaches the invention as claimed in claim 1, including wherein the output values of at least a part of the multiple different training functions are obtained: (i) from hardware simulation software configured to run a neural network according to the training description of a neural network architecture, and/or (ii) from running the neural network according to the training description of a neural network architecture on physical hardware (Lee [Fig. 2 & Sec. 3] discusses the Meta-Training Source Pool, in which the output values of the multiple training functions are acquired from, comprises physical hardware devices in which the neural network has run on according to the description of the neural architecture).
Regarding claim 12, claim 12 is a non-transitory computer-readable storage medium claim that
is substantially the same as the method of claim 1. Therefore, claim 12 is rejected for the same reasons
as claim 1.
Regarding claim 13, claim 13 is a system claim that is substantially the same as the method of
claim 1. Therefore, claim 13 is rejected for the same reasons as claim 1.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Müller, as applied in claim 1, and further in view of Abdelfattah et al. ("ZERO-COST PROXIES FOR LIGHTWEIGHT NAS", ICLR 2021, arXiv) (Year: 2021), hereafter Abdelfattah.
Regarding dependent claim 7, the combination of Lee and Müller teaches the invention as claimed in claim 1, including obtaining multiple different training functions, ([Sec. 3.2-3.3] discusses a meta-training “source device pool” in which during training, the different training functions are randomly obtained).
The combination of Lee and Müller does not explicitly teach at least one of the training functions is a parameter-free model applied to the training description of the neural network architecture, and/or at least one of the training functions is a least one of the following: a number of parameters of the neural network architecture, a number of layers of the neural network architecture, a number of layers of the neural network architecture of a particular type, a number of activations in the neural network architecture, a number of multiply-accumulate operations, and/or at least part of the training functions are correlated with the hardware metric.
However, in a similar field of endeavor, Abdelfattah teaches zero-cost proxies for lightweight NAS which are applied to predictor-based and evolutionary searches, wherein functions are parameter free ([Abstract & Sec. 1 & 3] discusses applying an individual parameter-free model function, or a function using at most a single minibatch of data at initialization, to a neural architecture search; thus, a training function that is a parameter-free model is applied to the training description of the neural network architecture).
Because the combination of Lee and Müller teaches obtaining multiple different training functions; and Abdelfattah teaches at least one of the training functions is a parameter-free model applied to the training description of the neural network architecture, accordingly, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate at least one of the training functions being a parameter-free model applied to the training description of the neural network architecture as taught by Abdelfattah into the combination of Lee and Müller’s computer-implemented method, with a reasonable expectation of success, to teach at least one of the training functions is a parameter-free model applied to the training description of the neural network architecture, and/or at least one of the training functions is a least one of the following: a number of parameters of the neural network architecture, a number of layers of the neural network architecture, a number of layers of the neural network architecture of a particular type, a number of activations in the neural network architecture, a number of multiply-accumulate operations, and/or at least part of the training functions are correlated with the hardware metric. This combination would have been motivated by the desire to reduce the computational power and time needed (Abdelfattah [Abstract]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Müller, as applied in claim 1, and further in view of Wu et al. ("FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search", 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition, IEEE) (Year: 2019), hereafter Wu.
Regarding dependent claim 10, the combination of Lee and Müller teaches the invention as claimed in claim 1, including obtaining multiple different training functions, ([Sec. 3.2-3.3] discusses a meta-training “source device pool” in which during training, the different training functions are randomly obtained).
The combination of Lee and Müller does not explicitly teach wherein at least a part of the multiple different training functions are discontinuous in at least part of the training description of the neural network architecture.
However, in a similar field of endeavor, Wu teaches a differentiable NAS design in which part of the training functions are discontinuous ([Sec. 3] discusses functions include the use of latency look-up tables to determine the estimate of the latency of a network based on the runtime of each operator; this per-layer lookup is inherently a piecewise, or step, function over the variables in the architecture description, because swapping operators at a layer produces a jump in summed latency and therefore, a discontinuous function of the architecture description for at least a part of the multiple different training functions).
Because the combination of Lee and Müller teaches obtaining multiple different training functions; and Wu teaches at least a part of the multiple different training functions are discontinuous in at least part of the training description of the neural network architecture, accordingly, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate at least a part of the multiple different training functions are discontinuous in at least part of the training description of the neural network architecture as taught by Wu into the combination of Lee and Müller’s computer-implemented method, with a reasonable expectation of success, to teach wherein at least a part of the multiple different training functions are discontinuous in at least part of the training description of the neural network architecture. This combination would have been motivated by the desire to reduce computational cost while consistently reflecting accurate and actual latency (Wu [Abstract]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dudziak et al. ("BRP-NAS: Prediction-based NAS using GCNs", 34th Conference on Neural Information Processing Systems, NeurIPS) (Year: 2020) ([Abstract] Neural architecture search (NAS) enables researchers to automatically explore broad design spaces in order to improve efficiency of neural networks. This efficiency is especially important in the case of on-device deployment, where improvements in accuracy should be balanced out with computational demands of a model. In practice, performance metrics of model are computationally expensive to obtain. Previous work uses a proxy (e.g., number of operations) or a layer-wise measurement of neural network layers to estimate end-to-end hardware performance but the imprecise prediction diminishes the quality of NAS. To address this problem, we propose BRP-NAS, an efficient hardware-aware NAS enabled by an accurate performance predictor-based on graph convolutional network (GCN))
Mayer et al. (US 20230004796 A1, published 01/05/2023) ([0100] Further, when combined with an adaptive training schedule, as described herein, binning and/or one-hot encoding can allow neural networks to converge to functions that describe discontinuous (e.g., piece-wise) target functions or target functions having discontinuities. Traditional or previous neural networks have been limited to learning continuous functions and have had little or no success learning discontinuous functions. The pre-processing techniques described can make it possible for neural networks to be used efficiently and accurately for discontinuous targets or target functions).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RILEY S ACOSTA whose telephone number is (571)272-8714. The examiner can normally be reached Monday-Thursday 6am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer N Welch can be reached at (571)272-7212. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RILEY S ACOSTA/Examiner, Art Unit 2143
/JENNIFER N WELCH/Supervisory Patent Examiner, Art Unit 2143
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