DETAILED ACTION
Claims 1-10 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2-7 and 9-10 are objected to because they are dependent on rejected claims. Appropriate correction is required.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Rathi, et al., Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware, ACM Computing Surveys, Vol. 55, No. 12, Article 243, 02 March 2023, pp. 1-49, in its entirety. Specifically:
Claim 1
Clam 1’s “an axon configured to generate a spike input” is anticipated by Rathi, et al., page 26, Fig. 13, where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 1’s “a synapse configured to perform a weight calculation in response to the spike input and to generate a membrane signal based on the weight calculation; and” is anticipated by Rathi, et al., page 26, last partial paragraph, where it recites:
RESPARC further extends the tiled architecture by leveraging the high storage density of hlmemristive crossbars to enable large number of on-chip tiles. However, expensive crossbar writes limit the applicability of a time-multiplexed architecture, where the crossbars are reused across layers by re-programming weight matrices and executing the corresponding dot-product operations. Consequently, a spatial architecture where the weight data of an entire SNN are pinned to crossbars located across multiple tiles is more efficient, as it leverages the benefits of high storage density while alleviating the costly writes.
Clam 1’s “a neuron configured to accumulate the membrane signal to generate a spike output, and” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated (i.e., “accumulate”) into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 1’s “a firing unit configured to compare a potential of a membrane node where the membrane signal is accumulated with a reference potential, and to fire based on the comparison result; ” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated (i.e., “accumulated”) into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 1’s “a plurality of membrane capacitors connected to the membrane node;” is anticipated by Rathi, et al., page 29, first full paragraph, where it recites:
Leaky IF neurons have been also implemented using switched capacitor circuits where the switches are used to implement leak behavior between the membrane potential and resting potential [64].
Clam 1’s “a switch controller configured to output a plurality of switching signals based on the firing of the firing unit;” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 1’s “a plurality of switches configured to connect each of the plurality of membrane capacitors to one of a power supply voltage and a ground voltage in response to the switching signals; and” is anticipated by Rathi, et al., page 29, first full paragraph, where it recites:
Leaky IF neurons have been also implemented using switched capacitor circuits where the switches are used to implement leak behavior between the membrane potential and resting potential [64].
Clam 1’s “a spike output generator configured to generate the spike output based on the plurality of switching signals and the firing of the firing unit.” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to the target neurons over the network.
Claim 8
Clam 8’s “receiving, by a synapse, a spike input from an axon to generate a membrane signal based on a weight;” is anticipated by Rathi, et al., page 26, Fig. 13, where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 8’s “accumulating the membrane signal on a membrane node of a neuron to lower a potential of the membrane node;” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated (i.e., “accumulate”) into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 8’s “when the potential of the membrane node becomes lower than a reference potential, generating, by a firing unit of the neuron, a firing signal by firing;” is anticipated by Rathi, et al., page 4, third full paragraph, where it recites:
The equation represents the behavior of the neuron when the membrane potential (u) is below the threshold potential (v). The membrane potential integrates the input current over time and the neuron fires when the potential crosses the threshold voltage.
Clam 8’s “generating, by a switch controller, switching signals for deactivating the membrane capacitors in response to the firing signal; and” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to the target neurons over the network.
Clam 8’s “generating, by a spike output generator, a spike output based on the switching signals and the firing signal.” is anticipated by Rathi, et al., page 26, Fig. 13 (b), where the caption recites:
Fig. 13. (a) RESPARC as a pool of NeuroCells (b) Macro Processing Engine - The mPE receives input spikes over the bus and the switch network, which is processed by the crossbars to produce output currents: C1, C2, C3, C4. The crossbar currents get integrated into the neurons to produce output spikes that are then sent to the target neurons over the network.
Reasons for Not Rejecting the Clams Under Art
Claims 2-7 and 9-10 are not rejected since when reading the claims in light of the Specification, as per MPEP § 2111.01, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claims 2-7. Specifically, the closest prior art of Rathi, et al., Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware, ACM Computing Surveys, Vol. 55, No. 12, Article 243, 02 March 2023, pp. 1-49 fails to expressly teach:
Claims 2-7's "...second inverter configured to invert an output of the first inverter..."
Further, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claim 9. Specifically, the closest prior art of Rathi, et al. fails to expressly teach:
Claims 9’s "...same electric capacity..."
Further, none of the references of record, whether taken alone or in combination, discloses or suggests the combination of limitations specified in independent Claim 10. Specifically, the closest prior art of Rathi, et al. fails to expressly teach:
Claims 10’s "...dividing the multiplied result by a value one less than the number of membrane capacitors..."
Only to the extent that these limitations (specifically as defined above) are not found in the prior art of record is the present case not rejected over the prior art.
Conclusion
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/WILBERT L STARKS/
Primary Examiner, Art Unit 2122
WLS
24 JUN 2026
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