DETAILED ACTION
1. This office action is in response to communication filed on 02/11/2026. Claims 1, 8, 13-14 and 20 have been amended. Claims 1 – 20 are pending on this application.
Response to Arguments
2. Applicant’s arguments, under remarks with respect to claims 1 and 20 have been fully considered and are persuasive. The rejections have been withdrawn.
Applicant’s arguments with respect to amended independent claim 14 has been considered but are moot because the new ground of rejection (Bodnar et al. U.S Pub. No. 2019/0280706) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bodnar et al. U.S. Pub. No. 2019/0280706.
Regarding claim 14. Fig. 7 of Bodnar et al discloses a method of operating an analog-to-digital converter (ADC) including a first input unit (200) and a second input unit (200) , each of which (each of 200 or 220) is configured to receive an input signal (VIN), which is a continuous analog signal (An analog signal is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) without being sampled without sampling switch of VIN), the method (Fig. 7) comprising: performing, by the first input unit (200) , a quantization operation (quantize operation of 200) on the input signal (VIN) in a successive approximation scheme (SAR Logic) ; generating, by the second input unit (220) , a residue signal (Residue DAC signal) , throughout the quantization operation (quantize operation of 200) on the input signal (Vin) by the first input unit (200) , based on the input signal (VIN) and a previous digital value (digital value from SAR 214) output during a previous analog-to-digital conversion cycle (cycle of Sliced ADC); integrating the residue signal (integration of 230 for residue DAC signal) in response to receiving the residue signal (residue DAC signal) from the second input unit (220) throughout the quantization operation (quantize operation of 200) on the input signal (VIN) by the first input unit (200); and outputting a digital value (output digital value of ADC 240) corresponding to the input signal (VIN) based on an input signal (VIN) quantized through the quantization operation (quantize operation of 200) and the integrated residue signal ((output of residue amplifier 230) .
Regarding claim 15. (Previously Presented) The method of claim 14, Fig. 7 further discloses wherein the performing the quantization operation (quantize operation of 200) comprises performing the quantization operation (quantize operation of 200) based on the input signal (VIN) applied through the first input unit (200) , and the integrating the residue signal (output of 230) comprises generating the residue signal (Residue DAC signal) based on the input signal (VIN) applied through the second input unit (220), and integrating the residue signal (output of residue amplifier 230).
Regarding claim 16. The method of claim 15, Fig. 7 further discloses wherein the input signal (VIN) is applied to each of the first (200) and second input units (220) without an additional sampling operation (no addition of sampling switch).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bodnar et al. applied to claim 16 above, in view of Thomas U.S. patent No. 5581252.
Regarding claim 17. Fig. 7 of Bodnar et al. U.S. applied to claim 16 above further discloses wherein the first input unit (200) comprises the input signal (VIN) is applied, a first capacitor digital-to-analog converter (see Fig. 11 {210.1}) connected to the input signal (VIN), and a plurality of first switches (switches of 210 in Fig. 11) configured to control an operation of the first CDAC (operation of 210. 1 in Fig. 11)), and the second input unit (220) comprises which the input signal is applied (VIN), a second CDAC (see Fig. 11 {220}) connected to the input (VIN), and a plurality of second switches (switches of 2220 in Fig. 11) configured to control an operation of the second CDAC (operation of 220 in Fig. 11).
However, Bodnar et al. do not disclose the first input unit (200) comprises a first input capacitor to which the input signal is applied and the second input unit (220) comprises a second input capacitor.
Fig. 5 of Thomas discloses an SAR ADC comprising: a first input unit (MSB CDAC) comprises a first input capacitor (528) to which the input signal (Analog Input) is applied and a second input unit (LSB DAC) comprises a second input capacitor (548).
Bodnar et al. and Thomas are common subject matter of SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Thomas into Bodnar et al. for the purpose of improved high- resolution analog-to-digital converter circuit using CDACs which avoids the effects of parasitic capacitance on scaling capacitors, reduce the CMV to be within the CMR of the voltage comparator (Col. 1 lines 50-64 of Thomas).
Regarding claim 18. Bodnar et al. and Thomas applied to claim 17 above, Fig. 7 and Fig. 11 of Bodnar et al. further discloses wherein the outputting the digital value (digital output value of slice ADC 200 and ADC 240) comprises outputting a digital value ((digital output value of slice ADC 200 and ADC 240) corresponding to the input signal (VIN) in units of bits (paragraphs 0069…0075), the performing the quantization operation (quantize operation of 200) comprises controlling operations of the plurality of first switches (switches of 210.1 in Fig. 11) based on the digital value (digital values of SAR Logic 214 in Fig. 11) output in units of bits to quantize (bits output of SAR Logic) the input signal (VIN) in the successive approximation scheme (SAR 214 in Fig. 11) , and the generating the residue signal (Residue DAC signal) comprises applying the previous digital value (digital value of SAR 214) to the plurality of second switches (switches of 220 in Fig. 11) to generate the residue signal (Residue DAC) while the quantization operation is performed (performed of quantize operation of 200).
Regarding claim 19. Bodnar et al. and Thomas applied to claim 18 above, Fig. 7 and Fig. 11 of Bodnar et al. further comprising: resetting the plurality of first switches (resetting top switches of 210 in Fig. 11 to VREF1 or VREF2) and applying the digital value (digital value of SAR 14 in Fig. 11) corresponding to the input signal (VIN) to the plurality of second switches (switches of 220 in Fig. 11) when the digital value (digital value of SAR 214) corresponding to the input signal (VIN) is output in units of bits (bits output of SAR Logic 214).
Allowable Subject Matter
7. Claims 1- 13 and 20 are allowed.
With respect to claim 1 in addition to other elements in the claim; prior arts considered individual or combination does/do not teach: a comparator configured to output a digital value corresponding to the input signal in units of bits in response to receiving the quantized input signal from the first input unit and receiving the integrated residue signal from the loop filter
With respect to claim 20 in addition to other elements in the claim; prior arts considered individual or combination does/do not teach: a comparator configured to output a digital value corresponding to the input signal in units of bits in response to receiving the quantized input signal from the first capacitively-coupled input unit and receiving the integrated residue signal from the loop filter.
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
03/26/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845