DETAILED ACTION
1. This office action is in response to communication filed on 06/22/2026. Claim 14 has been amended. Claims 1 – 20 are pending on this application.
Response to Arguments
2. Under remarks with respect to claims 1 and 20, Applicant’s arguments “Examiner for the indication the allowing intendent claims 1 and 20. Applicants have herein amended independent claim 14 to recite: outputting, by the comparator, a digital value corresponding to the input signal in units of bits in response to receiving the quantized input signal from the first input unit and receiving and the integrated residue signal from the loop filter”. However, upon further searched, the allowing subject matter of claims 1 and 20 have been withdrawn in this non-final office action due to new ground of rejection Huang Pub. No. 2020/0228132 in view of Obata U.S. Pub. No. 2019/0280706.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 8, 14-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang Pub. No. 2020/0228132 in view of Obata U.S. Pub. No. 2023/0370083.
Regarding claim 1. Fig. 1A of Huang disclose an analog-to-digital converter (100) comprising: a first input unit (CT1) configured to receive an input signal (Vin), which is a continuous analog signal (an analog signal Vin is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) being sampled (120), and to quantize (quantization of CT1) the input signal (Vin) to generate a quantized input signal (signal of N1) ; a second input unit (CT2) configured to receive the input signal (Vin) and to generate a residue signal (residue voltage at N2) throughout the quantization of the input signal (quantization of CT2 of Vin) by the first input unit (CT1), based on the input signal (Vin) and a previous digital value output (previous digital output 1of 44) during a previous analog- to-digital conversion cycle (cycle of CT1); a loop filter (120 noise shaping) configured to generate an integrated residue signal (Vres1(k); in response to receiving the residue signal (residual signal of ant N2) from the second input unit (CT2) throughout the quantization of the input signal by the first input unit (quantization of CT1 of Vin) ; a comparator (142) configured to output a digital value (Dout) corresponding to the input signal (Vin) in units of bits (bits of Dout) in response to receiving the quantized input signal (signal N1) from the first input unit (CT1) and receiving the integrated residue signal (Vres2) from the loop filter (noise shaping 120) ; and a controller (146) configured to apply the previous digital value (previous digital value of 146) to the second input unit (CT2) such that the residue signal (residue of N2) is generated in parallel with the quantization of the input signal (N1) and to control (144) the first input unit (CT1) such that the input signal (Vin) is quantized in a successive approximation scheme (paragraph 0019) based on an output of the comparator (Dout).
However, Huang does not disclose the analog signal (Vin) is a continuous signal without being sampled.
Fig. 1 of Obata discloses an SAR analog-to-digital converter (3; paragraph 0007) comprising: a first input unit (top switching capacitors unit C1, C2) configured to receive an input signal (analog input signal V3), which is a continuous analog signal (An analog signal is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) without being sampled (without addition sampling operation of V3), and to quantize (quantize top switching capacitors unit) the input signal (V3) to generate a quantized input signal (V4); a second input unit (bottom switching capacitors unit C1, C2) configured to receive the input signal V3) and to generate a residue signal (paragraph 0003 discloses “noise-shape SAR ADC feeds back the integrated value of the residual voltages”) corresponding to a difference between the input signal (V3) and a previous digital value output (previous digital value output D11).
Huang and Obata are common subject matter of noise shaping SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Obata into Huang for the purpose of providing the conversion error may be reduced by using an integrated value of the conversion error involved with the A/D conversion as the comparison reference voltage for the next A/D conversion (paragraph 0020 of Obata).
Regarding claim 8. Huang and Obata applied to claim 1 above, Fig. 1 and Fig. 2 of Obata further discloses an SAR ADC (3) comprising: a loop filter (6) comprises at least one of a GM-C integrator (61; see Fig. 2 for discloses transconductance of each amplifier OP1, OP2, OP3), a capacitively-coupled instrumentation amplifier (Fig. 2 for disclose a capacitively-coupled instrumentation amplifier), or a circuit in which a GM-C integrator (61; Fig. 2 for discloses GM-C of 61) and a CCIA (capacitive coupling with amplifier in Fig. 2 of integrator 61) are combined with each other (61 in Fig. 2).
Regarding claim 14. Fig. 1A of Huang discloses a method of operating an analog-to-digital converter (100) including a first input unit (CT1), and a second input unit (CT2) , a loop filter (noise shaping 120), and a comparator (142), each of which is the first input unit (CT1) and the second input unit (CT2) being configured to receive an input signal (Vin) , which is a continuous analog signal ((An analog signal Vin is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) being sampled, the method comprising: performing, by the first input unit (CT1), a quantization operation (quantization of CT1) on the input signal (Vin) in a successive approximation scheme (paragraph 0019) to generate a quantized input signal (Signal N1) generating, by the second input unit (CT2), a residue signal (signal N2) , throughout the quantization operation (quantization of CT1) on the input signal (Vin) by the first input unit (CT1), based on the input signal (Vin) and a previous digital value output (previous output of 146) during a previous analog-to-digital conversion cycle (previous cycle of 100) ; integrating the residue signal (N2 signal) , by the loop filter (noise shaping 120) , in response to receiving the residue signal (N2 signal) from the second input unit (CT2) throughout the quantization operation (quantization of CT1) on the input signal (Vin) by the first input unit (CT2), to generate an integrated residue signal (Vres2); and outputting, by the comparator (142) , a digital value (Dout) corresponding to the input signal (Vin) in units of bits (bits of Dout) in response to receiving the quantized input signal (N1 signal) from the first input unit (CT1) and receiving and the integrated residue signal (Vres2) from the loop filter (noise shaping 120).
However, Huang does not disclose the analog signal (Vin) is a continuous signal without being sampled.
Fig. 1 of Obata discloses an SAR analog-to-digital converter (3; paragraph 0007) comprising: a first input unit (top switching capacitors unit C1, C2) configured to receive an input signal (analog input signal V3), which is a continuous analog signal (An analog signal is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) without being sampled (without addition sampling operation of V3), and to quantize (quantize top switching capacitors unit) the input signal (V3) to generate a quantized input signal (V4); a second input unit (bottom switching capacitors unit C1, C2) configured to receive the input signal V3) and to generate a residue signal (paragraph 0003 discloses “noise-shape SAR ADC feeds back the integrated value of the residual voltages”) corresponding to a difference between the input signal (V3) and a previous digital value output (previous digital value output D11).
Huang and Obata are common subject matter of noise shaping SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Obata into Huang for the purpose of providing the conversion error may be reduced by using an integrated value of the conversion error involved with the A/D conversion as the comparison reference voltage for the next A/D conversion (paragraph 0020 of Obata).
Regarding claim 15. Huang and Obata applied to claim 14 above, Fig. 1A of Huang further discloses wherein performing the quantization operation (quantization operation CT1) based on the input signal (V1) applied through the first input unit (CT1), and the integrating the residue signal (Vres2) comprises generating the residue signal (N2 signal) based on the input signal (Vin) applied through the second input unit (CT2), and integrating (Vres2) the residue signal (N2 signal).
Regarding claim 16. Huang and Obata applied to claim 15 above, Fig. 1A of Huang further discloses wherein the input signal (1) is applied to each of the first (CT1) and second input units (CT2) without an additional sampling operation (without additional sampling operation of analog V3 in Fig. 1 of Obata as applied to claim 14 above).
Regarding claim 20. Fig. 1A of Huang discloses a successive approximation analog-to-digital converter (100; paragraph 0019) comprising: a first capacitively-coupled input unit (CT1) configured to receive an input signal (Vin) that is a continuously changed analog signal (an analog signal Vin is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) being sampled and to quantize the input signal (Vin) in a binary search scheme (paragraph 0020) based on a control signal (control switching signal of CT1) to generate a quantized input signal (Signal of N1) ; a second capacitively-coupled input unit (CT2) configured to receive the input signal (Vin) and to generate a residue signal (signal of N2) , throughout the quantization (Quantization of CT1) of the input signal (Vin) by the first capacitively-coupled input unit (CT1) , based on the input signal (Vin) and a previous digital value (previous digital value output of 146) output during a previous analog-digital conversion cycle (previous cycle of 100) ; a loop filter (noise shaping 120) configured to integrate the residue signal (signal of N2) to generate an integrated residue signal (Vres2) in response to receiving the residue signal (N2 signal) from the second capacitively- coupled input unit (CT2) throughout the quantization (Quantization of CT1) of the input signal (Vin) by the first capacitively-coupled input unit (CT1); a comparator (142) configured to output a digital value (value of Dout) corresponding to the input signal (Vin) in units of bits (bits of Dout) in response to receiving the quantized input signal (Vin) from the first capacitively-coupled input unit (CT1) and receiving the integrated residue signal (Vres2) from the loop filter (noise shaping 120); and a successive approximation register logic (144, 146; paragraph 0016) configured to apply the control signal (control switches signal of CT1) to the first capacitively-coupled input unit (CT1) based on an output of the comparator (Dout) , and to apply the previous digital value (previous digital value Dout), output from the comparator (142), to the second capacitively-coupled input unit (CT2).
However, Huang does not disclose the analog signal (Vin) is a continuous signal without being sampled.
Fig. 1 of Obata discloses an SAR analog-to-digital converter (3; paragraph 0007) comprising: a first input unit (top switching capacitors unit C1, C2) configured to receive an input signal (analog input signal V3), which is a continuous analog signal (An analog signal is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) without being sampled (without addition sampling operation of V3), and to quantize (quantize top switching capacitors unit) the input signal (V3) to generate a quantized input signal (V4); a second input unit (bottom switching capacitors unit C1, C2) configured to receive the input signal V3) and to generate a residue signal (paragraph 0003 discloses “noise-shape SAR ADC feeds back the integrated value of the residual voltages”) corresponding to a difference between the input signal (V3) and a previous digital value output (previous digital value output D11).
Huang and Obata are common subject matter of noise shaping SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Obata into Huang for the purpose of providing the conversion error may be reduced by using an integrated value of the conversion error involved with the A/D conversion as the comparison reference voltage for the next A/D conversion (paragraph 0020 of Obata).
5. Claims 2-7, 11, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang and Obata applied to claims 1 and 15 above, in view of Thomas U.S. patent No. 5,581,252.
Regarding claim 2 Huang Pub. and Obata applied to clais 1 above, Fig. 1A of Huang further discloses wherein the first input unit (CT1) comprises the input signal (Vin) is applied, a first capacitor digital-to-analog converter (CT1) connected to the input signal (Vin), and a plurality of first switches (switches of CT1) configured to control an operation of the first CDAC (CT1), and the second input unit (CT2) comprises which the input signal is applied (Vin) , a second CDAC (CT2) connected to the input (Vin), and a plurality of second switches (switches of CT2) configured to control an operation of the second CDAC (CT2).
However, Huang does not disclose the first input unit CT1) comprises a first input capacitor to which the input signal is applied and the second input unit (CT2) comprises a second input capacitor.
Fig. 5 of Thomas discloses an SAR ADC comprising: a first input unit (MSB CDAC) comprises a first input capacitor (528) to which the input signal (Analog Input) is applied and a second input unit (LSB DAC) comprises a second input capacitor (548).
Huang/Obata and Thomas are common subject matter of SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Thomas into Obata for the purpose of improved high- resolution analog-to-digital converter circuit using CDACs which avoids the effects of parasitic capacitance on scaling capacitors, reduce the CMV to be within the CMR of the voltage comparator (Col. 1 lines 50-64 of Thomas).
Regarding claim 3. Huang, Obata and Thomas applied to claim 2, Fig. 1 of Obata further discloses wherein the input signal (Vin) is a continuous analog signal (An analog signal is a continuous signal that represents real-world quantities such as current, voltage, temperature, pressure, or light intensity. It is characterized by its continuous nature in both time and amplitude) applied to each of the first and second input capacitors (by capacitors 528, 548 of Thomas applied to claim 2 above) without an additional sampling operation (without addition sampling operation of V3 of Obata as applied to claim 1 above).
Regarding claim 4. Huang, Obata and Thomas applied to claim 3 above, Fig. 1A of Huang further discloses wherein an analog-to-digital conversion cycle (conversion cycle (k-1, and k) of SAR ADC 100) of the analog-to-digital converter (100) comprises a quantization operation period (quantization period Øc of comparator 142), in which the input signal (V1) is quantized (quantized by switching capacitors CT1 and comparator 142), and a reset operation period (Øclean S9; paragraph 0038) in which a next analog-to-digital conversion cycle (k-1) is prepared in which a next analog-to-digital conversion cycle (k), the residue signal (Vres2k) is continuously applied to the loop filter (Noise shape 102) during the quantization operation period (quantization period Øc of 142), and the residue signal integrated (Vres2 ) in the loop filter (noise shaping 102) ) is continuously input to the comparator (142) , together with the quantized input signal (N1 signal), during the quantization operation period (quantization period of Øc of 142).
Regarding claim 5. Huang, Obata and Thomas applied to claim 4 above, Fig. 1A of Huang further discloses wherein the controller (144, 146) controls the plurality of first switches (switches of CT1, CT2) based on an output of the comparator (Dout) to quantize the input signal (Vin) through the first CDAC (CT1) in the successive approximation scheme (paragraph 0019) during the quantization operation period (Øc).
Regarding claim 6. Huang, Obata, and Thomas applied to claim 5 above; Fig. 1A of Huang further discloses wherein the controller (144, 146) applies the previous digital value (previous digital output of 146) to the plurality of second switches (switches of CT2) to generate the residue signal (residue signal of N2)) through the second CDAC (CT2) during the quantization operation period (Øc of 142).
Regarding claim 7. Huang, Obata, and Thomas applied to claim 6 above; Fig. 1 Obata further discloses wherein the controller (144, 146) resets (re) the plurality of first switches (Q11, Q12) during the reset operation period (period of reset Q11 of Q12 ) and applies a digital value (digital value from control unit for to control the switches Q11 and A12), output from the comparator (output of comparator (D11), to the plurality of second switches (Q11, Q12) during the quantization operation period (quantization period of SAR ADC3).
Regarding claim 11. Huang, Obata and Thomas applied to claim 2, Fig. 1 of Obata further discloses wherein each of the first (top switching capacitor C1, C2) and second CDACs (bottom switching capacitors C1, C2) comprises at least one redundancy capacitor (redundancy of C1; and redundancy of C2).
Regarding claim 17 Huang Pub. and Obata applied to claim 16 above, Fig. 1A of Huang further discloses wherein the first input unit (CT1) comprises the input signal (Vin) is applied, a first capacitor digital-to-analog converter (CT1) connected to the input signal (Vin), and a plurality of first switches (switches of CT1) configured to control an operation of the first CDAC (CT1), and the second input unit (CT2) comprises which the input signal is applied (Vin) , a second CDAC (CT2) connected to the input (Vin), and a plurality of second switches (switches of CT2) configured to control an operation of the second CDAC (CT2).
However, Huang does not disclose the first input unit CT1) comprises a first input capacitor to which the input signal is applied and the second input unit (CT2) comprises a second input capacitor.
Fig. 5 of Thomas discloses an SAR ADC comprising: a first input unit (MSB CDAC) comprises a first input capacitor (528) to which the input signal (Analog Input) is applied and a second input unit (LSB DAC) comprises a second input capacitor (548).
Huang/Obata and Thomas are common subject matter of SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Thomas into Obata for the purpose of improved high- resolution analog-to-digital converter circuit using CDACs which avoids the effects of parasitic capacitance on scaling capacitors, reduce the CMV to be within the CMR of the voltage comparator (Col. 1 lines 50-64 of Thomas).
Regarding claim 18, Huang, Obata and Thomas applied to claim 17 above, Fig. 1A of Huang further discloses wherein the outputting the digital value (Dout) comprises outputting a digital value (digital output value of Dout ) corresponding to the input signal (V1) in units of bits (bits of Dout), the performing the quantization operation (quantization operation of CT1) comprises controlling (144, 146) operations of the plurality of first switches (top switches CT1) based on the digital value output (digital value of Dout) in units of bits (bits of Dout) to quantize the input signal (V2) in the successive approximation scheme (paragraph 0019), and the generating the residue signal (signal of N2) comprises applying the previous digital value (digital value output of 146) to the plurality of second switches (switches of CT2) to generate the residue signal (Signal of N2) while the quantization operation (quantization of CT1) is performed (performed of CT1).
Regarding claim 19. Huang, Obata and Thomas applied to claim 18 above, Fig. 1 of Obata further discloses comprising: resetting the plurality of first switches (resetting top switches Q1 to VH or VL) and applying the digital value (value of S1) corresponding to the input signal (V3) to the plurality of second switches (bottom switches Q2) when the digital value (value of S1) corresponding to the input signal (V3) is output in units of bits (paragraph 0030).
6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and Obata applied to claim 1 above in further vies of Kinyua Pub. No. 2023/0421166.
Obata applied to claim 1 above do not discloses wherein the analog-to-digital converter corresponds to a single stage, among a plurality of stages included in an analog-to-digital converter having a pipeline structure.
Fig. 1 of Kinyua disclose an analog to digital converter (102) corresponds to a single stage (single stage 102) among a plurality of stages (102, 104) included in an analog-to-digital converter (104) having a pipeline structure (paragraph 0021).
Obata/Thomas and Kinyua are common subject matter ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Kinyua into Obata for the purpose of providing pipelined architecture allows serial operations to be performed more quickly (paragraph 0022).
7. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and Obata applied to claim 1 above in further vies of Liu et al. U.S. patent No. 11,626,885.
Obata applied to claim 1 above do not discloses wherein the analog-to-digital converter comprises a delta-signal modulator having a nested structure.
Fig. 2 of Liu et al. disclose an analog to digital converter (200) wherein the analog-to-digital converter (200) comprises a delta-signal modulator (Col. 2 lines 53-55) having a nested structure (nested structure of 200).
Huang/Obata and Liu et al are common subject matter ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Liu et al. into Huang/Obata for the purpose of providing (SAR) based quantizer in a continuous time delta-sigma ADC that efficiently program and calibrate the ELD gain in ELD compensation SAR quantizers (Col. 1 lines 36-42 of Liu et al.).
Allowable Subject Matter
8. Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the input signal is a differential input signal comprising a first input signal and a second input signal, the first input unit comprises a first differential input unit configured to quantize the first input signal and a second differential input unit configured to quantize the second input signal, and the second input unit comprises a third differential input unit configured to generate a first residue signal corresponding to a difference between the first input signal and the previous digital value and a fourth differential input unit configured to generate a second residue signal corresponding to a difference between the second input signal and the previous digital value.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
08/05/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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