Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
The examiner has considered the remarks provided by the applicant, provided on
April 20, 2026, for the specification and claim objections on the non-final rejection mailed on February 4, 2026. The applicant’s remarks and corrections overcome the specification and claim objections issued on the non-final rejection. Therefore, the specification and claim objections have been withdrawn.
Applicant’s arguments, see 35 USC §112, filed April 20, 2026, with respect to claim 8 has been fully considered and is persuasive. The §112(b) rejection of February 4, 2026 has been withdrawn.
Response to Arguments
Applicant's arguments filed April 20, 2026 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach each and every element of amended claims 1 and 13..
Applicant’s arguments with respect to claims 1 and 13 have been considered but are moot because of the new ground of rejection.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the ramp signal generator is further configured to reset the ramp signal in response to the assertion of the comparator output signal must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The ramp signal generator is further configured to reset the ramp signal in response to the assertion of the comparator output signal, and the resetting the ramp signal responsive to the assertion of the output signal of the comparator have not been sufficiently described.
Claims 2 and 10-12 inherit the defects of independent claim 1.
Claims 14-16 inherit the defects of independent claim 13.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 10-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which the inventor or a joint inventor (or for
applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (lines 13-14) recites "wherein the ramp signal generator is further configured to reset the ramp signal in response to the assertion of the comparator output signal". It is unclear from the drawings and the specification how the output of the comparator would affect the ramp signal generator to reset the ramp signal. For compact prosecution, this claim limitation cannot be relied upon to distinguish over the prior art.
Claims 2 and 10-12 inherit the defects of independent claim 1.
Claim 13 (lines 11-12) recites "resetting the ramp signal responsive to the assertion of the output signal of the comparator". It is unclear from the drawings and the specification how the output of the comparator would affect the ramp signal response. For compact prosecution, this claim limitation cannot be relied upon to distinguish over the prior art.
Claims 14-16 inherit the defects of independent claim 13.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20210399636 A1), in view of So (US 6342822 B1); hereinafter Chang, in view of So.
Regarding Claim 1, as best understood, Chang discloses a comparator system [Fig. 1, 105], comprising: a ramp signal generator [115] configured to periodically generate a ramp signal [Fig. 1, output of 115; Fig. 2, V-Ramp signal]; an auxiliary comparator [145] configured to assert an enable signal [Boosting Signal] in response to the ramp signal being greater than a duty cycle voltage [Fig. 1, output of 150; Fig. 2, at time t1 when the V-Ramp signal is greater than the level-shifted error signal]; a main comparator [120] configured to assert a comparator output signal [Fig. 2, when the Comparator Output signal is high at time t2] in response to the ramp signal being greater than a threshold voltage [Fig. 1, VEA_o; Fig. 2, error signal] that is greater than the duty cycle voltage [Fig. 2, at time t2], wherein the main comparator includes [Fig. 3B, 120]: an always-on current source [I1] configured to conduct a bias current [paragraph 0023] throughout a period of the ramp signal [Fig. 2; paragraph 0023]; and a boost current source [I2] configured to conduct a boost current [paragraph 0023] only while the enable signal is asserted [paragraph 0023, switch SW closes by the Boosting Signal]. Chang does not explicitly disclose a set-reset latch configured to reset a clock signal in response to the assertion of the comparator output signal, wherein the ramp signal generator is further configured to reset the ramp signal in response to the assertion of the comparator output signal.
However, So discloses a comparator system [Fig. 1/2], comprising: a set-reset latch [latch (e.g. S-R flip flop)] configured to reset a clock signal [SYST. Clock] in response to the assertion of the comparator output signal [output signal from comparator], wherein the ramp signal generator is further configured to reset the ramp signal in response to the assertion of the comparator output signal [this claim limitation cannot be relied upon to distinguish over Chang, as modified with So]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang's comparator system, in view of So's comparator system, by adding the set-reset latch within the comparator system, for the purpose of steadying the output state.
Regarding Claim 2, as best understood, Chang, in view of So, discloses the comparator system of claim 1, wherein the main comparator [Chang, Fig. 3B] further includes: a power supply node for a power supply voltage [Chang, Fig. 3B; VDD]; and a first switch [Chang, Fig. 3B; SW] coupled to the power supply node [Chang, Fig. 3B; coupled through M4 or M5] and configured to close only while the enable signal is asserted [Chang, Fig. 3B; paragraph 0023, switch SW closes by the Boosting Signal], wherein the always-on current source [Chang, Fig. 3B; I1] is coupled to the power supply node [Chang, Fig. 3B; coupled through M4 or M5] and wherein the first switch is coupled between the power supply node and the boost current source [Chang, Fig. 3B; coupled between VDD and I2].
Regarding Claim 13, as best understood, Chang discloses a method of operation for a comparator [Fig. 1, 105; Fig. 3B, 120], comprising: periodically generating a ramp signal [Fig. 1, output of 115; Fig. 2, V-Ramp signal]; conducting a bias current [paragraph 0023; Fig. 2, Bias Current] through the comparator throughout a period of the ramp signal [Fig. 2; paragraph 0023]; conducting a boost current [paragraph 0023; Fig. 2, the Boosting Signal is high] through the comparator in response to the ramp signal being greater than a duty cycle voltage [Fig. 1, output of 150; Fig. 2, at time t1 when the V-Ramp signal is greater than the level-shifted error signal]; asserting an output signal of the comparator [Fig. 2, when the Comparator Output signal is high at time t2] in response to the ramp signal being greater than a threshold voltage [Fig. 1, VEA_o; Fig. 2, error signal] that is greater than the duty cycle voltage [Fig. 2, at time t2]. Chang does not explicitly disclose resetting a clock signal responsive to the assertion of the output signal of the comparator; and resetting the ramp signal responsive to the assertion of the output signal of the comparator.
However, So discloses a method of operation for a comparator [Fig. 1/2], comprising: resetting a clock signal [SYST. Clock] responsive to the assertion of the output signal of the comparator [output signal from comparator]; and resetting the ramp signal responsive to the assertion of the output signal of the comparator [this claim limitation cannot be relied upon to distinguish over Chang, as modified with So]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang's comparator system, in view of So's comparator system, for the purpose of steadying the output state.
Regarding Claim 15, as best understood, Chang, in view of So, discloses the method of claim 13, further comprising: stopping a conduction of the boost current through the comparator in response to the ramp signal being greater than the threshold voltage [Chang; Fig. 2, the V-Ramp is greater than error signal at time t3 which stops the Boosting Signal].
Regarding Claim 16, as best understood, Chang, in view of So, discloses the method of claim 13, wherein the boost current is larger than the bias current [Chang; Fig. 2, the Bias Current is shown to be lower than the Boosting Signal between times t1 to t3].
Claims 10-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of So, further in view of Loeda Pagliano (US 8878711 B1); hereinafter Chang, in view of So, further in view of Loeda Pagliano.
Regarding Claims 10 & 11, as best understood, Chang, in view of So, does not explicitly disclose the comparator system of claim 1, wherein the clock signal is output to a current digital-to-analog converter, and wherein the current digital-to-analog converter in included in a sigma-delta analog-to-digital converter.
However, Loeda Pagliano discloses a sigma-delta ADC [Fig. 2, 200], wherein the clock signal is output [204] to a current digital-to-analog converter [214/216/206/208]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of So, further in view of Loeda Pagliano, by incorporating the sigma-delta ADC, which includes integrators, quantizer, and digital-to-analog converters, for the purpose of steadying the output state.
Regarding Claim 14, as best understood, Chang, in view of So, does not explicitly disclose the method of claim 13, further comprising: outputting the clock signal to a current digital-to-analog converter.
However, Loeda Pagliano discloses outputting the clock signal [Fig. 2, 204] to a current digital-to-analog converter [214/216/206/208] within a sigma-delta ADC [200]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of So, further in view of Loeda Pagliano, by incorporating the sigma-delta ADC, which includes integrators, quantizer, and digital-to-analog converters, for the purpose of steadying the output state.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of So and Loeda Pagliano, further in view of Tam (US 20030016060 A1); hereinafter Chang, in view of So and Loeda Pagliano, further in view of Tam.
Regarding Claim 12, as best understood, Chang, in view of So, further in view of Loeda Pagliano, does not explicitly disclose the comparator system of claim 1, wherein the comparator system is included within a cellular telephone.
However, Tam discloses wherein the comparator system is included within a cellular telephone [Fig. 8; paragraph 0025]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of So and Loeda Pagliano, further in view of Tam, by adding a comparator system within a cellular telephone, for the benefit of comparing signal strengths and signal processing.
Allowable Subject Matter
Claims 3-9 and 17-20 allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 3, Chang et al. (US 20210399636 A1) discloses a comparator system [Fig. 1, 105], comprising: a ramp signal generator [115] configured to periodically generate a ramp signal [Fig. 1, output of 115; Fig. 2, V-Ramp signal]; an auxiliary comparator [145] configured to assert an enable signal [Boosting Signal] in response to the ramp signal being greater than a duty cycle voltage [Fig. 1, output of 150; Fig. 2, at time t1 when the V-Ramp signal is greater than the level-shifted error signal]; and a main comparator [120] configured to assert a comparator output signal [Fig. 2, when the Comparator Output signal is high at time t2] in response to the ramp signal being greater than a threshold voltage [Fig. 1, VEA_o; Fig. 2, error signal] that is greater than the duty cycle voltage [Fig. 2, at time t2], wherein the main comparator includes [Fig. 3B, 120]: an always-on current source [I1] configured to conduct a bias current [paragraph 0023] throughout a period of the ramp signal [Fig. 2; paragraph 0023]; and a boost current source [I2] configured to conduct a boost current [paragraph 0023] only while the enable signal is asserted [paragraph 0023, switch SW closes by the Boosting Signal]; a power supply node for a power supply voltage [Chang, Fig. 3B; VDD]; and a first switch [Chang, Fig. 3B; SW] coupled to the power supply node [Chang, Fig. 3B; coupled through M4 or M5] and configured to close only while the enable signal is asserted [Chang, Fig. 3B; paragraph 0023, switch SW closes by the Boosting Signal], wherein the always-on current source [Chang, Fig. 3B; I1] is coupled to the power supply node [Chang, Fig. 3B; coupled through M4 or M5] and wherein the first switch is coupled between the power supply node and the boost current source [Chang, Fig. 3B; coupled between VDD and I2]. The prior art of record does not disclose nor render obvious the a first self-biased transistor having a source coupled to ground; a first pair of transistors coupled in series between a current source output node of both the always-on current source and the boost current source and a drain of the first self-biased transistor; and a second pair of transistors coupled in series between the current source output node and the drain of the first self-biased transistor, wherein a gate of the first self- biased transistor is coupled to a node between the transistors in the second pair of transistors.
Claims 4-9 are allowed based on dependency.
Regarding Claim 17, Chang et al. (US 20210399636 A1) discloses a comparator system [Fig. 1, 105], comprising: a power supply node for a power supply voltage [Fig. 3B; ground]; an always-on current source [I1] coupled to the power supply node; a first switch [SW] coupled to the power supply node; a boost current source [I2] coupled to the first switch; a first NMOS transistor [M4] having a drain; and a second NMOS transistor [M5] having a drain. The prior art of record does not disclose nor render obvious the a first PMOS transistor having a source coupled to the always-on current source and to the boost current source; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor, wherein a gate of the first PMOS transistor is coupled to a gate of the first NMOS transistor; a second PMOS transistor having a source coupled to the always-on current source and to the boost current source; a second NMOS transistor having a drain coupled to a drain of the second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate of the second NMOS transistor; and a third NMOS transistor having a source coupled to ground, a gate coupled to the drain of the second NMOS transistor, and a drain coupled to a source of the first NMOS transistor and to a source of the second NMOS transistor.
Claims 18-20 are allowed based on dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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