Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 3, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0024 (lines 2-3) - recites "sources of transistors M3 and M4 thus couple to a drain of an NMOS transistor M4", needs to be reworded to match what is shown in Fig. 4.
Appropriate correction is required.
Claim Objections
Claims 2 and 11 are objected to because of the following informalities:
Claim 2 (line 3) - recites "a first switch configured coupled to the power supply node", shows a double verb. Possibly remove the word "configured".
Claim 11 (line 1) - recites "the current digital-to-analog converter in included in a sigma-delta". It appears the word "in" should be "is" within this phrase..
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112
(pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and
distinctly claim the subject matter which the inventor or a joint inventor (or for
applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 (lines 1-2) recites "wherein a gate of the second PMOS transistor and a gate of the second NMOS transistor are both coupled to a node for the duty cycle voltage". It is unclear how the gates of these transistors are coupled to the duty cycle voltage, as Fig. 4 shows the gates of these transistors directly coupled to the node of the threshold voltage.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 13, and 15-16 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Chang et al. (US 20210399636 A1); hereinafter Chang.
Regarding Claim 1, Chang discloses a comparator system [Fig. 1, 105], comprising: a ramp signal generator [115] configured to periodically generate a ramp signal [Fig. 1, output of 115; Fig. 2, V-Ramp signal]; an auxiliary comparator [145] configured to assert an enable signal [Boosting Signal] in response to the ramp signal being greater than a duty cycle voltage [Fig. 1, output of 150; Fig. 2, at time t1 when the V-Ramp signal is greater than the level-shifted error signal]; a main comparator [120] configured to assert a comparator output signal [Fig. 2, when the Comparator Output signal is high at time t2] in response to the ramp signal being greater than a threshold voltage [Fig. 1, VEA_o; Fig. 2, error signal] that is greater than the duty cycle voltage [Fig. 2, at time t2], wherein the main comparator includes [Fig. 3B, 120]: an always-on current source [I1] configured to conduct a bias current [paragraph 0023] throughout a period of the ramp signal [Fig. 2; paragraph 0023]; and a boost current source [I2] configured to conduct a boost current [paragraph 0023] only while the enable signal is asserted [paragraph 0023, switch SW closes by the Boosting Signal].
Regarding Claim 2, Chang discloses the comparator system of claim 1, wherein the main comparator [Fig. 3B] further includes: a power supply node for a power supply voltage [VDD]; and a first switch [SW] coupled to the power supply node [coupled through M4 or M5] and configured to close only while the enable signal is asserted [paragraph 0023, switch SW closes by the Boosting Signal], wherein the always-on current source [I1] is coupled to the power supply node [coupled through M4 or M5] and wherein the first switch is coupled between the power supply node and the boost current source [coupled between VDD and I2].
Regarding Claim 13, Chang discloses a method of operation for a comparator [Fig. 1, 105; Fig. 3B, 120], comprising: periodically generating a ramp signal [Fig. 1, output of 115; Fig. 2, V-Ramp signal]; conducting a bias current [paragraph 0023; Fig. 2, Bias Current] through the comparator throughout a period of the ramp signal [Fig. 2; paragraph 0023]; conducting a boost current [paragraph 0023; Fig. 2, the Boosting Signal is high] through the comparator in response to the ramp signal being greater than a duty cycle voltage [Fig. 1, output of 150; Fig. 2, at time t1 when the V-Ramp signal is greater than the level-shifted error signal]; and asserting an output signal of the comparator [Fig. 2, when the Comparator Output signal is high at time t2] in response to the ramp signal being greater than a threshold voltage [Fig. 1, VEA_o; Fig. 2, error signal] that is greater than the duty cycle voltage [Fig. 2, at time t2].
Regarding Claim 15, Chang discloses the method of claim 13, further comprising: stopping a conduction of the boost current through the comparator in response to the ramp signal being greater than the threshold voltage [Fig. 2, the V-Ramp is greater than error signal at time t3 which stops the Boosting Signal].
Regarding Claim 16, Chang discloses the method of claim 13, wherein the boost current is larger than the bias current [Fig. 2, the Bias Current is shown to be lower than the Boosting Signal between times t1 to t3].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of Zhang et al. (US 20200212902 A1); hereinafter Chang, in view of Zhang.
Regarding Claim 10, Chang does not explicitly disclose the comparator system of claim 1, further comprising: a set-reset latch configured to reset a clock signal to a current digital-to-analog converter in response to an assertion of the comparator output signal.
However, Zhang discloses wherein the comparator system [Fig. 2] further comprises a set-reset latch [204] configured to reset a clock signal [214] to a current digital-to-analog converter in response to an assertion of the comparator output signal [210]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of Zhang, by adding set-reset latch within a comparator system, for the purpose of steadying the output state.
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of Zhang, further in view of Loeda Pagliano (US 8878711 B1); hereinafter Chang, in view of Zhang, further in view of Loeda Pagliano.
Regarding Claim 11, Chang, in view of Zhang, does not explicitly disclose the comparator system of claim 10, wherein the current digital-to-analog converter is included in a sigma-delta analog-to-digital converter.
However, Loeda Pagliano discloses wherein the current digital-to-analog converter is included in a sigma-delta analog-to-digital converter [Fig.2 description, Fig. 3 description]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of Zhang, further in view of Loeda Pagliano, by including the current digital-to-analog converter in a sigma-delta analog-to-digital converter, for the purpose of lowering jitter sensitivity.
Regarding Claim 14, Chang does not explicitly disclose the method of claim 13, further comprising: resetting a clock to a current digital-to-analog converter in a sigma-delta analog digital converter responsive to an assertion of the output signal of the comparator.
However, Zhang discloses wherein the method [Fig. 2] further comprises resetting a clock [214] to a current digital-to-analog converter responsive to an assertion of the output signal of the comparator [210]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of Zhang, by adding set-reset latch within a comparator system, for the purpose of steadying the output state. Chang, in view of Zhang, does not explicitly disclose that the current digital-to-analog converter [Zhang, 210] is in a sigma-delta analog digital converter.
However, Loeda Pagliano discloses wherein the current digital-to-analog converter is included in a sigma-delta analog-to-digital converter [Fig.2 description, Fig. 3 description]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of Zhang, further in view of Loeda Pagliano, by including the current digital-to-analog converter in a sigma-delta analog-to-digital converter, for the purpose of lowering jitter sensitivity.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of Tam (US 20030016060 A1); hereinafter Chang, in view of Tam.
Regarding Claim 12, Chang does not explicitly disclose the comparator system of claim 1, wherein the comparator system is included within a cellular telephone.
However, discloses wherein the comparator system is included within a cellular telephone [Fig. 8; paragraph 0025]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chang, in view of Tam, by adding a comparator system within a cellular telephone, for the purpose of comparing signal strengths and signal processing.
Allowable Subject Matter
Claims 3-7 and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
Conclusion
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/Amit R Bhatia/Examiner, Art Unit 2842
/LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842