DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-16 and 21-24 are pending in the application. Claims 9-16 are withdrawn from further consideration.
Election/Restrictions
Claims 9-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 26 May 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 23 June 2025. The information therein was considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-8 and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0105545) (hereinafter, “Wang”) in view of Chen et al. (US 2022/0013462) (hereinafter, “Chen”).
Re: independent claim 1, Wang discloses in figs. 1D and 1L a semiconductor structure, comprising: at least one die (300) having a die thickness between a die active surface and a die back surface, wherein the die active surface comprises a die pad (320); a protective layer (350) formed on the die active surface, a molding layer (500) encapsulating the at least one die (300) and the protective layer (350), wherein the die back surface is exposed from the molding layer, and the molding layer (500) has a molding thickness larger than the die thickness and a thickness of the protective layer combined for forming a cavity contour (O1, R1); and a conductive layer (810) formed in the cavity contour (O1, R1).
Wang does not disclose expressly wherein the conductive layer is formed conformally to the cavity contour for forming a concave contour.
Chen discloses in fig. 9 a conductive layer (600) formed conformally to a cavity contour (310) for forming a concave contour.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive layer conformally to the cavity contour for the purpose of increasing the contact area between the conductive layer and a circuit layer as exemplified by Chen.
Re: claim 7, Wang in view of Chen discloses in fig. 9 of Chen the semiconductor structure of claim 1, further comprising: a heat sink (420) disposed on the conductive layer (600), wherein the heat sink (420) has a convex contour complementary to the concave contour of the conductive layer (600).
Re: claim 8, Wang in view of Chen discloses in fig. 1J of Wang the semiconductor structure of claim 1, further comprising: a sacrificial layer (214) formed on the die back surface, wherein the sacrificial layer (214) has a first surface in contact with the die back surface (300) and a second surface co-planar with a top surface of the molding layer (500).
Re: claim 23, Wang in view of Chen discloses the semiconductor structure of claim 1, wherein the cavity contour (Wang: fig. O1, R1; Chen: 310) comprises an interface between a top surface of the molding layer (Wang: 500; Chen: 300) and the die back surface (Wang: 300, Chen: 200), and the interface further comprises a sharp profile or a sloped profile (Wang: fig. 1K; Chen: fig. 5).
Re: claim 24, Wang in view of Chen discloses the semiconductor structure of claim 1, wherein the cavity contour (Wang: fig. O1, R1; Chen: 310) has a bottom surface for exposing the die back surface (Wang: 300, Chen: 200), and the bottom surface has an area substantially the same as a size of the die back surface (Wang: fig. 1K; Chen: fig. 5).
Allowable Subject Matter
Claims 2-6 and 21-22 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in claim 2, semiconductor structure of claim 1, wherein pre-vias are formed in the protective layer for exposing the die pad from the pre-vias, further comprising: filled vias in the protective layer by filling the pre-vias with a conductive medium, wherein the filled vias are electrically coupled to the die pad; and a build-up layer formed on the filled vias for being electrically coupled to the die pad.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Costa et al. US 10,068,831 teach a semiconductor package including a flip chip die, a mold compound surrounding the flip chip die and extending above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 6/10/2026
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