DETAILED ACTION
This action is in response to the 08/06/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 15 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2017/0264853; (hereinafter Tateishi) in view of US Pub. No. 2022/0045605; (hereinafter Wu).
Regarding claim 15, Tateishi [e.g. Fig. 1] discloses a power stage comprising:
a high side switching element [e.g. N1]; a low side switching element [e.g. N2]; an overcurrent protection circuit including a current sensor [e.g. 22], the current sensor configured to sense, in a first mode of operation in which the low side switching element is turned on, a first current indicative of a load current [e.g. IL; paragraph 072 recites “The low-side sensing type overcurrent protection circuit 22 detects the inductor current IL during the off-time of the upper-side transistor N1 from the switch voltage Vsw obtained during the on-time of the lower-side transistor N2”]; wherein the overcurrent protection circuit is configured to detect an overcurrent condition based on detection of the first current exceeding a first threshold value [e.g. paragraph 073 – 075 recite “The low-side sensing type overcurrent protection circuit 22 compares the voltage corresponding to the detected inductor current IL with the voltage corresponding to the bottom value threshold value THb by an internal comparator, so as to check a magnitude relationship between the inductor current IL and the bottom value threshold value THb….if the inductor current IL is more than the bottom value threshold value THb at the time point when the set signal S2 is decreased to the low level due to the decrease of the feedback voltage Vfb to the first reference voltage Vref1, the low-side sensing type overcurrent protection circuit 22 maintains the set signal S3 at high level regardless of the fall of the set signal S2, and after that generates a one-shot pulse (e.g. a falling pulse) in the set signal S3 by a trigger of the inductor current IL being the bottom value threshold value THb or less. In this case, in the state in which overcurrent may occur without overcurrent protection, the low-side sensing type overcurrent protection circuit 22 performs the overcurrent protection operation, and hence the bottom value (minimum value) of the inductor current IL is adjusted to the bottom value threshold value THb”].
Tateishi fails to disclose wherein the first sensing time interval begins after expiration of a first blanking time interval; wherein the first blanking time interval starts at a time of turning on the low side switching element.
Wu [e.g. Figs. 4 - 5] teaches wherein the first sensing time interval [e.g. Fig. 5; Tsense during low side transistor is ON (TL-ON)] begins after expiration of a first blanking time interval [e.g. TBlank; paragraph 025 recites “the dashed line is the inductor current (IL), which is the target Imon signal that is sought to be reconstructed, and the solid line is low-side FET current sense signal, as blanked by the blanking time (TBlank). Here further, the typical current sense point (ISense1) of the inductor current (IL) at the end of the blanking time (TBlank) is shown with an “X”]; wherein the first blanking time interval starts at a time of turning on the low side switching element [e.g. Fig. 5; TBlank with respect to TL-ON]..
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first sensing time interval begins after expiration of a first blanking time interval; wherein the first blanking time interval starts at a time of turning on the low side switching element as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 16, Tateishi fails to disclose wherein the first blanking time interval extends between a first instant of time in which the low side switching element is turned on and a second instance of time when the first sensing time interval begins.
Wu [e.g. Figs. 4 - 5] teaches wherein the first blanking time interval [e.g. TBlank] extends between a first instant of time in which the low side switching element is turned on [e.g. Fig. 5; instant at the beginning of TL-ON] and a second instance of time when the first sensing time interval begins [e.g. instant at beginning of Tsense].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first blanking time interval extends between a first instant of time in which the low side switching element is turned on and a second instance of time when the first sensing time interval begins as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant's arguments filed 08/06/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s) with respect to claim 15 in page 7:
“Claim 15 is been amended based on the allowable limitations in claim 7. Applicants submit that claim 15 and corresponding dependent claims are allowable as well”.
In response, claim 7 was not indicated as Allowable Subject Matter, in fact, claim 7 was rejected under 35 USC § 103 in page 6 of the Non-Final Office Action 05/11/2026. Furthermore, Therefore, the argument is not persuasive.
Allowable Subject Matter
Claims 1 – 8, 11, 13 – 14, 17 – 18, 20 – 28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 1 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the first mode of operation is implemented during a condition in which a magnitude of a pulse width of a pulse width modulation control signal controlling operation of the high side switching element and the low side switching element is less than a threshold level”.
The primary reason for the indication of the allowability of claim 26 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “after the expiration of the first blanking time interval, generating a truncation signal during a condition in which a magnitude of the first current is greater than the first threshold value”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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