DETAILED ACTION
This action is in response to the 04/01/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Allowable Subject Matter
The indicated allowability of previous claim 7 now incorporated in independent claim 1 is withdrawn in view of the newly discovered reference(s). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 1 – 2, 7, 8, 11, 14 – 18 and 20 – 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2017/0264853; (hereinafter Tateishi) in view of US Pub. No. 2022/0045605; (hereinafter Wu).
Regarding claim 1, Tateishi [e.g. Fig. 1] discloses a method of detecting an overcurrent conditions in a switched mode power supply [e.g. 1], the switched mode power supply comprising a high side switching element [e.g. N1] and a low side switching element [e.g. N2], the method comprising: sensing [e.g. 22], in a first mode of operation, during a first sensing time interval during which the low side switching element is turned on, a first current indicative of a load current [e.g. IL; paragraph 072 recites “The low-side sensing type overcurrent protection circuit 22 detects the inductor current IL during the off-time of the upper-side transistor N1 from the switch voltage Vsw obtained during the on-time of the lower-side transistor N2”]; and detecting a first overcurrent condition based on the first current exceeding a first threshold value [e.g. paragraph 073 – 075 recite “The low-side sensing type overcurrent protection circuit 22 compares the voltage corresponding to the detected inductor current IL with the voltage corresponding to the bottom value threshold value THb by an internal comparator, so as to check a magnitude relationship between the inductor current IL and the bottom value threshold value THb….if the inductor current IL is more than the bottom value threshold value THb at the time point when the set signal S2 is decreased to the low level due to the decrease of the feedback voltage Vfb to the first reference voltage Vref1, the low-side sensing type overcurrent protection circuit 22 maintains the set signal S3 at high level regardless of the fall of the set signal S2, and after that generates a one-shot pulse (e.g. a falling pulse) in the set signal S3 by a trigger of the inductor current IL being the bottom value threshold value THb or less. In this case, in the state in which overcurrent may occur without overcurrent protection, the low-side sensing type overcurrent protection circuit 22 performs the overcurrent protection operation, and hence the bottom value (minimum value) of the inductor current IL is adjusted to the bottom value threshold value THb”].
Tateishi fails to disclose wherein the first sensing time interval begins after expiration of a first blanking time interval.
Wu [e.g. Figs. 4 - 5] teaches wherein the first sensing time interval [e.g. Fig. 5; Tsense during low side transistor is ON (TL-ON)] begins after expiration of a first blanking time interval [e.g. TBlank; paragraph 025 recites “the dashed line is the inductor current (IL), which is the target Imon signal that is sought to be reconstructed, and the solid line is low-side FET current sense signal, as blanked by the blanking time (TBlank). Here further, the typical current sense point (ISense1) of the inductor current (IL) at the end of the blanking time (TBlank) is shown with an “X.””].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first sensing time interval begins after expiration of a first blanking time interval as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 2, Tateishi [e.g. Fig. 1] discloses further comprising: sensing, in a second mode of operation, during a second sensing time interval when the high side switching element is turned on, a second current indicative of the load current [e.g. paragraph 076 recites “The high-side sensing type overcurrent protection circuit 23 detects the inductor current IL during the on-time of the upper-side transistor N1 from the switch voltage Vsw obtained during the on-time of the upper-side transistor N1”]; and detecting a second overcurrent condition based on the second current exceeding a second threshold value [e.g. paragraph 077 recites “The high-side sensing type overcurrent protection circuit 23 compares the voltage corresponding to the detected inductor current IL with the voltage corresponding to the peak value threshold value THp by the internal comparator, so as to check a magnitude relationship between the inductor current IL and the peak value threshold value THp”. Paragraph 080 recites “…in the period after the upper-side transistor N1 is turned on until a predetermined on-time Ton elapses, the peak value threshold value THp is set to a value larger than the sum of the ripple component R of the inductor current IL and the bottom value threshold value THb. Therefore, the overcurrent protection is not enabled basically by the peak value threshold value THp, and the upper-side transistor N1 maintains the ON state. Further, in an unexpected accident, even if the inductor current IL exceeds the sum of the ripple component R of the inductor current IL and the bottom value threshold value THb in the period after the upper-side transistor N1 is turned on until a predetermined on-time Ton elapses, the overcurrent protection can be enabled by the peak value threshold value THp”].
Regarding claim 7, Tateishi fails to disclose wherein the first blanking time interval starts at a time of turning on the low side switching element.
Wu [e.g. Figs. 4 - 5] teaches wherein the first blanking time interval starts at a time of turning on the low side switching element [e.g. Fig. 5; TBlank with respect to TL-ON].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first blanking time interval starts at a time of turning on the low side switching element as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 8, Tateishi fails to disclose wherein the second sensing time interval begins after a second blanking time interval expires after the high side switching element is turned on.
Wu [e.g. Figs. 4 - 5] teaches wherein the second sensing time interval [e.g. Fig. 5; second Tsense on the “next switching cycle”] begins after a second blanking time interval expires [e.g. Fig. 5; end of TBlank] after the high side switching element is turned on [e.g. Fig. 5; TH-ON].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the second sensing time interval begins after a second blanking time interval expires after the high side switching element is turned on as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 11, Tateishi [e.g. Fig. 1] discloses wherein, during the first sensing time interval, the load current flows through the low side switching element and an inductive element [e.g. L1] to an output of the switched mode power supply [e.g. Vout terminal].
Regarding claim 14, Tateishi [e.g. Fig. 1] discloses further comprising: turning off, when the overcurrent condition is detected in the second mode of operation, the high side switching element [e.g. overcurrent protection is provided when the inductor current is higher than the threshold THp by cutting the current from the source by turning off the high side switch]; and turning on, when the overcurrent condition is detected in the second mode of operation, the low side switching element [e.g. see G2 in Fig. 3 at t21].
Regarding claim 15, Tateishi [e.g. Fig. 1] discloses a power stage comprising:
a high side switching element [e.g. N1]; a low side switching element [e.g. N2]; an overcurrent protection circuit including a current sensor [e.g. 22], the current sensor configured to sense, in a first mode of operation in which the low side switching element is turned on, a first current indicative of a load current [e.g. IL; paragraph 072 recites “The low-side sensing type overcurrent protection circuit 22 detects the inductor current IL during the off-time of the upper-side transistor N1 from the switch voltage Vsw obtained during the on-time of the lower-side transistor N2”]; wherein the overcurrent protection circuit is configured to detect an overcurrent condition based on detection of the first current exceeding a first threshold value [e.g. paragraph 073 – 075 recite “The low-side sensing type overcurrent protection circuit 22 compares the voltage corresponding to the detected inductor current IL with the voltage corresponding to the bottom value threshold value THb by an internal comparator, so as to check a magnitude relationship between the inductor current IL and the bottom value threshold value THb….if the inductor current IL is more than the bottom value threshold value THb at the time point when the set signal S2 is decreased to the low level due to the decrease of the feedback voltage Vfb to the first reference voltage Vref1, the low-side sensing type overcurrent protection circuit 22 maintains the set signal S3 at high level regardless of the fall of the set signal S2, and after that generates a one-shot pulse (e.g. a falling pulse) in the set signal S3 by a trigger of the inductor current IL being the bottom value threshold value THb or less. In this case, in the state in which overcurrent may occur without overcurrent protection, the low-side sensing type overcurrent protection circuit 22 performs the overcurrent protection operation, and hence the bottom value (minimum value) of the inductor current IL is adjusted to the bottom value threshold value THb”].
Tateishi fails to disclose wherein the first sensing time interval begins after expiration of a first blanking time interval.
Wu [e.g. Figs. 4 - 5] teaches wherein the first sensing time interval [e.g. Fig. 5; Tsense during low side transistor is ON (TL-ON)] begins after expiration of a first blanking time interval [e.g. TBlank; paragraph 025 recites “the dashed line is the inductor current (IL), which is the target Imon signal that is sought to be reconstructed, and the solid line is low-side FET current sense signal, as blanked by the blanking time (TBlank). Here further, the typical current sense point (ISense1) of the inductor current (IL) at the end of the blanking time (TBlank) is shown with an “X.””].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first sensing time interval begins after expiration of a first blanking time interval as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 16, Tateishi fails to disclose wherein the first blanking time interval extends between a first instant of time in which the low side switching element is turned on and a second instance of time when the first sensing time interval begins.
Wu [e.g. Figs. 4 - 5] teaches wherein the first blanking time interval [e.g. TBlank] extends between a first instant of time in which the low side switching element is turned on [e.g. Fig. 5; instant at the beginning of TL-ON] and a second instance of time when the first sensing time interval begins [e.g. instant at beginning of Tsense].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first blanking time interval extends between a first instant of time in which the low side switching element is turned on and a second instance of time when the first sensing time interval begins as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 17, Tateishi fails to disclose wherein the first blanking time interval prevents detection of the first overcurrent condition.
Wu [e.g. Figs. 4 - 5] teaches wherein the first blanking time interval prevents detection of the first overcurrent condition [e.g. the current sense is performed after TBlank which prevents a current sense before the end of TBlank, Fig. 5 and paragraph 025, therefore any overcurrent is prevented to be detected].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first blanking time interval prevents detection of the first overcurrent condition as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 18, Tateishi fails to disclose wherein the first sensing time interval resides between the first blanking time interval and a second blanking time interval.
Wu [e.g. Figs. 4 - 5] teaches wherein the first sensing time interval [e.g. Fig. 5; Tsense] resides between the first blanking time interval [e.g. Fig. 5; TBlank] and a second blanking time interval [e.g. Fig. 5; TBlank at the next switching cycle]
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first sensing time interval resides between the first blanking time interval and a second blanking time interval as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 20, Tateishi [e.g. Fig. 1] discloses further comprising: sensing, in a second mode of operation, during a second sensing time interval when the low side switching element is turned on, a second current indicative of the load current [e.g. paragraph 072 recites “The low-side sensing type overcurrent protection circuit 22 detects the inductor current IL during the off-time of the upper-side transistor N1 from the switch voltage Vsw obtained during the on-time of the lower-side transistor N2”]; and detecting a second overcurrent condition based on the second current exceeding a second threshold value [e.g. paragraph 075 recites “if the inductor current IL is more than the bottom value threshold value THb… the low-side sensing type overcurrent protection circuit 22 performs the overcurrent protection operation”].
Regarding claim 21, Tateishi fails to disclose wherein the second sensing time interval begins after a second blanking time interval and before a third blanking time interval.
Wu [e.g. Figs. 4 - 5] teaches wherein the second sensing time interval [e.g. Fig. 5; Tsense] begins after a second blanking time interval [e.g. Fig. 5; TBlank] and before a third blanking time interval [e.g. Fig. 5; next switch cycle, not shown].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the second sensing time interval begins after a second blanking time interval and before a third blanking time interval as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Regarding claim 22, Tateishi fails to disclose wherein the first blanking time represents a time duration in which monitoring of the first current for an overcurrent condition in the first mode of operation is disabled.
Wu [e.g. Figs. 4 - 5] teaches wherein the first blanking time represents a time duration in which monitoring of the first current for an overcurrent condition in the first mode of operation is disabled [e.g. Fig. 5; a monitoring of a current (even an overcurrent) is disabled during TBlank period].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the first blanking time represents a time duration in which monitoring of the first current for an overcurrent condition in the first mode of operation is disabled as taught by Wu in order of being able to provide current-sense accuracy, paragraph 01.
Claims 3 – 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tateishi in view of Wu and further in view of US Pub. No. 2023/0208297; (hereinafter Pahkala).
Regarding claim 3, Tateishi fails to disclose further comprising: receiving a pulse width modulation PWM (Pulse With Modulation) signal for controlling the switching of the high side switching element and the low side switching element; and switching between the first mode of operation and the second mode of operation based on a duty cycle of the PWM signal.
Pahkala [e.g. Fig. 2] teaches further comprising: receiving a pulse width modulation PWM (Pulse With Modulation) signal [e.g. Buck_PWM 227] for controlling the switching of the high side switching element [e.g. 210] and the low side switching element [e.g. 222]; and switching between the first mode of operation and the second mode of operation based on a duty cycle of the PWM signal [e.g. Fig. 5 with respect to HS_gate and LS_gate].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by further comprising: receiving a pulse width modulation PWM (Pulse With Modulation) signal for controlling the switching of the high side switching element and the low side switching element; and switching between the first mode of operation and the second mode of operation based on a duty cycle of the PWM signal as taught by Pahkala such that an over-current condition in the inductor is reliably detected, even when the switching is performed at high frequency, paragraph 04.
Regarding claim 4, Tateishi fails to disclose wherein the PWM signal comprises a control pulse for turning on the high side switching element, and wherein the method further comprises: switching between the first mode of operation and the second mode of operation based on the duty cycle of the PWM signal.
Pahkala teaches wherein the PWM signal comprises a control pulse [e.g. Fig. 5; pulse of Buck_PWM] for turning on the high side switching element, and wherein the method further comprises: switching between the first mode of operation and the second mode of operation based on the duty cycle of the PWM signal [e.g. as shown in Fig. 5 with respect to Buck_PWM, HS_gate and LS_gate].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by wherein the PWM signal comprises a control pulse for turning on the high side switching element, and wherein the method further comprises: switching between the first mode of operation and the second mode of operation based on the duty cycle of the PWM signal as taught by Pahkala such that an over-current condition in the inductor is reliably detected, even when the switching is performed at high frequency, paragraph 04.
Claims 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tateishi in view of Wu, Pahkala and further in view of US Pub. No. 2006/0221528; (hereinafter Li).
Regarding claim 13, Tateishi fails to disclose further comprising: reducing, when the overcurrent condition is detected in the first mode of operation, a duration of a subsequent control pulse following the control pulse of the PWM signal; and applying the subsequent control pulse with reduced duration to a gate of the high side switching element.
Li teaches further comprising: reducing, when the overcurrent condition is detected in the first mode of operation, a duration of a subsequent control pulse following the control pulse of the PWM signal [e.g. PWM_GD]; and applying the subsequent control pulse with reduced duration to a gate of the high side switching element [e.g. P1; paragraph 021 recites “The level 1 over-current protection circuit 28 may operate to reduce the current IL1 if the measured current is substantially between the first predetermined over-current threshold and the second predetermined over-current threshold. For example, the level 1 over-current protection circuit 28 may, upon detecting that the measured current is substantially between the first predetermined over-current threshold and the second predetermined over-current threshold, send a control signal to the gate signal logic controller 12. The gate signal logic controller 12, in response to the level 1 over-current protection circuit 28 control signal, could, for example, begin narrowing the pulses of the signal PWM_GD on a cycle-by-cycle basis. As another example, the gate signal logic controller 12 could deactivate the current pulse early. Therefore, the first power FET P1 becomes activated for less time based on the narrow pulses, thus reducing the current of the switching power supply 10”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Tateishi by further comprising: reducing, when the overcurrent condition is detected in the first mode of operation, a duration of a subsequent control pulse following the control pulse of the PWM signal; and applying the subsequent control pulse with reduced duration to a gate of the high side switching element as taught by Li in order of being able to provide a reliable overcurrent detection.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 5 – 6 are allowed.
Claims 19, 23 – 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 5 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the PWM signal comprises a control pulse for turning on the high side switching element, and wherein the method further comprises: switching to the first mode of operation in response to a first condition in which a duration of the control pulse is shorter than a threshold duration; and switching to the second mode of operation in response to a second condition in which the duration of the control pulse is longer than the threshold duration”.
The primary reason for the indication of the allowability of claim 19 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the first mode of operation is implemented during a condition in which a magnitude of a pulse width of a pulse width modulation control signal controlling operation of the high side switching element and the low side switching element is less than a threshold level”.
The primary reason for the indication of the allowability of claim 23 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: switching between the first mode of operation and a second mode of operation of detecting the overcurrent conditions in the switched mode power supply depending on a duty cycle of a pulse width modulation signal controlling the high side switching element and the low side switching element, the second mode of operation of detecting the overcurrent conditions including: i) during a second sensing time interval during which the high side switching element is turned on, sensing a second current indicative of the load current; and detecting a second overcurrent condition based on the second current exceeding a second threshold value”.
The primary reason for the indication of the allowability of claim 25 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: switching to the first mode of operation in response to a first condition in which a duration of a control pulse controlling the high side switching element is shorter than a threshold duration; and switching to a second mode of operation in response to a second condition in which the duration of the control pulse is longer than the threshold duration, the second mode of operation of detecting overcurrent including: i) during a second sensing time interval during which the high side switching element is turned on, sensing a second current indicative of the load current”.
The primary reason for the indication of the allowability of claim 26 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: after the expiration of the first blanking time interval, generating a truncation signal during a condition in which a magnitude of the first current is greater than the first threshold value”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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