DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 07/21/2026.
Currently, claims 1-22 are pending in the application. Currently, claims 1-8 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 9-22) in the reply filed on 07/21/2026 is acknowledged. However, Applicant’s reply did not include an species election as required in the Restriction Requirement of 06/22/2026. During a telephone conversation with Damian Aquino on 09/09/2026, a provisional election was made to prosecute the invention of Species I (Figs. 3A-3F). Claims 1-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Further, claims 10-12 and 18-20 are withdrawn by the Examiner as being directed to non-elected Species II and Species III. Claims 9, 13-17, and 21-22 are examined in this Office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/26/2024, 7/30/2024, and 12/30/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Objections
Claim 14 is objected to because of the following informality:
In claim 14, “when driver injects” should read “when the driver injects”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 13-17, and 21-22 are rejected under 35 U.S.C. 103 as being obvious over DONG et al. (M. Dong, R. Yu, Y. Jiang, J. Bu, J. Knapp and D. Brdar, "B-TRAN™ Optimization and Performance Characterization," 2023 IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL, USA, 2023, pp. 1835-1839 ).
Regarding independent claim 9, Dong teaches a switch assembly (Figs. 1-4) comprising:
an upper terminal (Fig. 4, connection between Q1 and VDC, II. Test), a lower terminal (Fig. 4, connection between Q2 and VDC, II. Test), and a control input (Fig. 3, input signals into power supply and control, I. Introduction);
a double-sided double-base bipolar junction transistor (DSDB-BJT) (Fig. 1) defining an upper base (Fig. 1, B1, I. Introduction), an upper collector-emitter (Fig. 1, E1, I. Introduction), a lower base (Fig. 1, B2, I. Introduction), and a lower collector-emitter (Fig. 1, E2, I. Introduction);
an upper-main FET (Fig. 4, Q1, II. Test) defining a first lead (Fig. 4, connection from Q1 to D1, II. Test) coupled to the upper terminal, a second lead (Fig. 4, connection from Q1 to E1, II. Test) coupled to the upper collector-emitter, and a gate (Fig. 4, connection of Q1 to Driver, II. Test);
a lower-main FET (Fig. 4, Q1, II. Test) defining a first lead (Fig. 4, connection from Q2 to E2, II. Test) coupled to the lower collector-emitter, a second lead (Fig. 4, connection from Q2 to VDC, II. Test) coupled to the lower terminal, and a gate (Fig. 4, connection from Q2 to Driver, II. Test);
a driver (Figs. 3-4, Driver, II. Test) coupled to the control input, the gate of the upper-main FET, the gate of the lower-main FET, and the upper and lower bases of the DSDB-BJT (Figs. 3-4, I. Introduction);
responsive to assertion of the control input, and for a first applied voltage (Figs. 4, VDC, I. Introduction) across the upper terminal and lower terminal, the driver configured to:
arrange the DSDB-BJT for conduction (Fig. 1, I. Introduction);
inject charge carriers (Figs. 1-4, On-Mode, I. Introduction) into an upper drift region (Fig. 1, upper half of N- region, I. Introduction) of the DSDB-BJT and simultaneously inject charge carriers (Figs. 1-4, On-Mode, I. Introduction teaches that B1 and B2 are each connected to the driver as control inputs and would therefore be capable of injecting current/charge carriers. Therefore, it would be obvious that Dong’s device assembly would be capable of simultaneous charge carrier injection depending on the input from the driver) into a lower drift region (Fig. 1, lower half of N- region, I. Introduction ) of the DSDB-BJT; and
assert the gate of the lower-main FET to make the lower-main FET conductive such that a first load current flows from the upper terminal to the lower terminal (Fig. 4(a), II. Test).
Regarding claim 13, Dong teaches the switch assembly of claim 9, and Dong teaches that the DSDB-BJT (Fig. 1, I. Introduction) comprises a monolithic structure with a continuous drift region (Fig. 1, N- drift region is continuous).
Regarding claim 14, Dong teaches the switch assembly of claim 13, and Dong teaches that when the driver injects charge carriers into the upper drift region (Figs. 1-4, I. Introduction teaches that B1 and B2 are each connected to the driver as control inputs and would therefore be capable of injecting current/charge carriers. Therefore, it would be obvious that Dong’s device assembly would be capable of the claimed current/charge carrier injection depending on the control input from the driver), the driver is configured to inject an upper current into the upper base; and
wherein when the driver injects charge carriers (Figs. 1-4, I. Introduction teaches that B1 and B2 are each connected to the driver as control inputs and would therefore be capable of charge carrier injection and current injection depending on the input from the driver) into the lower drift region, the driver is configured to inject a lower current into the lower base.
Regarding claim 15, Dong teaches the switch assembly of claim 9, and Dong teaches that responsive to de-assertion of the control input (Fig. 3, input signals into power supply and control, II. Test), the driver is configured to:
de-assert the gate of the upper-main FET to make the upper-main FET non-conductive (Fig. 4, Dong’s Driver is connected to the gate of MOSFET Q1 and would therefore be able to de-assert the gate of Q1 and make Q1 non-conductive depending on the signal from the Driver);
de-assert the gate of the lower-main FET to make the lower-main FET non-conductive such that no current flows from the lower collector-emitter to the lower terminal (Fig. 4, Dong’s Driver is connected to the gate of MOSFET Q2 and would therefore be able to de-assert the gate of Q2 and make Q2 non-conductive depending on the input from the Driver); and
arrange the DSDB-BJT into a non-conductive state by coupling the upper base (Fig. 1, B1, I. Introduction) to the upper collector-emitter and coupling the lower base (Fig. 1, B2, I. Introduction) to the lower terminal (Fig. 1, Off-Mode, I. Introduction).
Regarding claim 16, Dong teaches the switch assembly of claim 9, and Dong teaches that responsive to assertion of the control input (Fig. 3, input signals into power supply and control, I. Introduction), and for a first applied voltage across the upper terminal and the lower terminal (Fig. 4(a), II. Test), the driver is further configured to assert the gate of the upper-main FET to make the upper-main FET conductive (Fig. 4, the driver is connected to the gate of MOSFET Q1 and would therefore be capable of making Q1 conductive depending on the input from the driver).
Regarding independent claim 17, Dong teaches a switch assembly (Figs. 1-4) comprising:
an upper terminal (Fig. 4, connection between Q1 and VDC, II. Test), a lower terminal (Fig. 4, connection between Q2 and VDC, II. Test), and a control input (Fig. 3, input signals into power supply and control, I. Introduction);
a bipolar junction device (Fig. 1) defining an upper collector-emitter Fig. 1, E1, I. Introduction) coupled to the upper terminal (Fig. 5, connection from Q1 to E1, I. Introduction), a lower base (Fig. 1, B2, I. Introduction), and a lower collector-emitter (Fig. 1, E2, I. Introduction);
a lower-main FET (Fig. 4, Q1, II. Test) defining a first lead (Fig. 4, connection from Q2 to E2, II. Test) coupled to the lower collector-emitter, a second lead (Fig. 4, connection from Q2 to VDC, II. Test) coupled to the lower terminal, and a gate (Fig. 4, connection from Q2 to Driver, II. Test);
a driver (Figs. 3-4, Driver, I. Introduction) coupled to the control input, the gate of the lower-main FET, and the lower base of the bipolar junction device (Figs. 3-4, I. Introduction);
responsive to assertion of the control input, and for a first applied voltage (Figs. 4, VDC, I. Introduction) across the upper terminal and lower terminal, the driver configured to:
arrange the bipolar junction device for conduction (Figs. 1-4, On-Mode, I. Introduction), including injection of charge carriers into an upper drift region (Fig. 1, upper half of N- region, I. Introduction) of the bipolar junction device and simultaneously inject charge carriers into a lower drift region (Fig. 1, lower half of N- region, I. Introduction) of the bipolar junction device (Figs. 1-4, On-Mode, I. Introduction teaches that B1 and B2 are each connected to the driver as control inputs and would therefore be capable of injecting current/charge carriers. Therefore, it would be obvious that Dong’s device assembly would be capable of simultaneous charge carrier injection depending on the input from the driver); and
assert the gate of the lower-main FET to make the lower-main FET conductive such that a first load current flows from the upper terminal to the lower terminal (Fig. 4(a), II. Test).
Regarding claim 21, Dong teaches the switch assembly of claim 17, and Dong teaches that the bipolar junction device (Fig. 1, I. Introduction) comprises a monolithic structure with a continuous drift region (Fig. 1, N- drift region is continuous).
Regarding claim 22, Dong teaches the switch assembly of claim 17, and Dong teaches that responsive to de-assertion of the control input (Fig. 3, input signals into power supply and control, II. Test), the driver is configured to:
de-assert the gate of the lower-main FET to make the lower-main FET non-conductive such that no current flows from the lower collector-emitter to the lower terminal (Fig. 4, Dong’s Driver is connected to the gate of MOSFET Q2 and would therefore be able to de-assert the gate of Q2 and make Q2 non-conductive depending on the input from the Driver); and arrange the bipolar junction device into a non-conductive state (Fig. 1, Off-Mode, I. Introduction).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2021/0359678 by Mojab discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2019/0363196 by Wood discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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