Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the amendment filed 08/07/2026.
Claims 1-14 are pending in this application.
Claims 1 and 14 are independent claims.
Claims 1,11 and 12 are currently amended.
This Office Action is made final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2, 4, 6 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chodor (US 2023/0138635 A1) in view of Catron (US 2024/0054384 A1).
As per claim 1, Chodor teaches A method performed by one or more processors, the method comprising:
obtaining a trace from a source program comprising an artificial intelligence calculation; (Chodor [0030] The improved computing system technology uses a new C-like programming language allowing application developers to create source files [source program] that, when compiled, produce complex command lists having a set of hardware-specific executable commands for a GPU. This allows an application to dispatch a command list of the executable commands to a GPU command buffer for execution by the GPU. The command list can be a complex, mutable list of hardware instructions for the GPU and [0034] The source file includes software code written in a new, C-like language that is specifically designed to generate complex, mutable command lists of executable hardware instructions (i.e., executable hardware commands) specifically to be executed by the GPU without further interpretation or encoding by an API or driver. The source file is compiled with a new compiler 21 that is designed specifically to compile or interpret code written in the new C-like language and generate executable hardware commands that can be used to build a command list to take advantage of functionality of the GPU command streamer 25.).
The examiner believes this is consistent with what is disclosed in the specification ([0018] In addition, the acquiring the original call list may include acquiring a trace from a source program including an artificial intelligence calculation, wherein the trace includes at least one of code or primitive operation associated with the source program, and acquiring an original call list based on the trace, in which the plurality of primitive operations may be included in an operation library accessible to each of the plurality of accelerators)
.
obtaining, based on the trace of the source program, an original call list associated with the artificial intelligence calculation and comprising a plurality of primitive operations (Chodor [0029] The improved computing system technology as described herein provides for programming GPU command buffers using complex, mutable command lists [call list]. The technology helps improve the overall performance of computing systems by allowing applications to express complex scheduling models to be executed on the GPU by providing complex command lists to as GPU command buffer for processing by GPU command streamers (as consumers of command buffers). The disclosed technology helps in blending the border between compute devices and hosts, allowing program source level creation of complex scenarios and algorithms on multiple levels of execution. [0106] For example, in one embodiment the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or compute operations [0128] In one embodiment the additional fixed function logic 238 can also include machine-learning acceleration logic, such as fixed function matrix multiplication [primitive operation] logic, for implementations including optimizations for machine learning training or inferencing. [0193] In one embodiment the graphics execution unit 508 includes one or more SIMD floating point units (FPU(s)) 534 to perform floating-point operations. In one embodiment, the FPU(s) 534 also support integer computation. In one embodiment the FPU(s) 534 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 54-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present, and may be specifically optimized to perform operations associated with machine learning computations.).
The examiner believes this interpretation of “artificial intelligence calculation” is consistent with what is disclosed in the specification ([0051] …. “artificial intelligence calculation” may refer to any calculation associated with a machine learning model (e.g., an artificial neural network model, etc.). For example, an artificial intelligence calculation may be a calculation performed in each layer included in an artificial neural network model. For example, the artificial intelligence calculation may include an addition calculation, a subtraction calculation, a maximum value computation calculation, a minimum value computation calculation, a floating point multiplication calculation, weighting calculation, convolution calculation, matrix multiplication calculation…)
Chodor does not teach determining a plurality of accelerators to parallelly process the original call list and generating, based on the original call list and based on a quantity of the plurality of accelerators, a plurality of sub call lists and
transmitting each of the plurality of sub call lists to a corresponding one of the plurality of accelerators.
However, Catron teaches determining a plurality of accelerators to parallelly process the original call list; (Catron [0017] Spreading sparse lookups across multiple machine learning accelerator hardware units allows memory bandwidth to be expanded by a factor equal to the number of machine learning accelerator hardware units operating in parallel, which alleviates memory bottlenecks and [0043]… For example, in a personalized recommendation machine learning model network, by assigning a first specified number of cores to sparse lookups and a second specified number of cores to MLP computation, sparse lookups can run in parallel across different machine learning accelerator hardware units and MLP computation can execute simultaneously with sparse lookups in a pipelined fashion (e.g., see FIG. 2C). Stated alternatively, concurrent execution of different portions of the machine learning model network is allowed.)
generating, based on the original call list and based on a quantity of the plurality of accelerators, a plurality of sub call lists; (Catron [0017] If the machine learning model network is partitioned across two machine learning accelerator hardware units [quantity of accelerators], then these two dependency chains can run independently, potentially halving latency. Spreading sparse lookups across multiple machine learning accelerator hardware units allows memory bandwidth to be expanded by a factor equal to the number of machine learning accelerator hardware units [quantity of accelerators]operating in parallel, which alleviates memory bottlenecks. [0041] At 304, the machine learning model network is partitioned across a plurality of different machine learning accelerator hardware units. In various embodiments, the partitioning is based at least in part on the analysis in 302.)
transmitting each of the plurality of sub call lists to a corresponding one of the plurality of accelerators. (Catron [0043] At 306, parallelization and pipelining of an execution of the machine learning model network is allowed. In various embodiments, allowing parallelization and pipelining includes allocating computing cores of a machine learning accelerator hardware unit between different operators of the machine learning model network. For example, in a personalized recommendation machine learning model network, by assigning a first specified number of cores to sparse lookups and a second specified number of cores to MLP computation, sparse lookups can run in parallel across different machine learning accelerator hardware units….)
Catron improves Chodor by dispatching instructions to multiple GPU for parallelization.
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Catron with the system of Chodor to determine a plurality of accelerators. One having ordinary skill in the art would have been motivated to use Catron into the system of Chodor for the purpose of achieving parallelism for machine learning (Catron paragraph 01).
As per claim 2, Catron teaches dividing, based on the quantity of the plurality of accelerators, input data comprised in the original call list into a plurality of pieces of sub input data; and generating the plurality of sub call lists such that each of the plurality of pieces of sub input data is comprised in a corresponding one of the plurality of sub call lists. (Catron [0017] A machine learning model network may be regarded as a directed graph, wherein nodes of the directed graph correspond to machine learning model operators. In various embodiments, machine learning model operators (also referred to simply as operators) compute an output given an appropriate number and types of inputs and parameters. For example, an operator can correspond to an SLS operation. An operator can also correspond to a matrix multiply operation using an input tensor, a weights matrix, and/or a bias vector. [0018] In various embodiments, in addition to partitioning a machine learning model network across multiple machine learning accelerator hardware units, concurrent execution within a single machine learning accelerator hardware unit is allowed. Parts of the machine learning model network that that can be executed concurrently can be identified and run in parallel on a machine learning accelerator hardware unit. For example, in some embodiments, a sparse lookup is executed concurrently with a combination operation by an MLP. Concurrent execution can improve computational performance by splitting a machine learning model network into a memory bandwidth intensive portion and a compute intensive portion that run in parallel and saturate both the memory bus and the compute unit on a machine learning accelerator hardware unit to achieve higher throughput. [0022] In various embodiments, each accelerator receives input data. The input may be a tensor data object. The tensor can store various types of data. For example, for image recognition applications, the tensor may include image data (e.g., two-dimensional or three-dimensional images) [0029] The machine learning model network may be divided into several sub-networks and loaded onto multiple accelerators because it is too large to run on a single accelerator. For example, embedding tables used in sparse lookups may not fit into the memory of a single accelerator. Sparse lookups 232 and 234 can be divided so as to balance embedding table sizes across accelerators. It is also possible to divide them so as to balance runtimes across partitions (requiring performance information associated with the sparse lookups, e.g., as done in profile-guided partitioning as described in further detail herein). Splitting the machine learning model network can improve performance via model parallelism and [0031] Regardless of model complexity, memory bandwidth intensive operations can be split across accelerators to alleviate memory bottlenecks and compute intensive operations can be duplicated on different accelerators to allow for pipelining (decreasing latency of a sequence of machine learning computation requests) and allow for more options for execution.).
As per claim 4, Catron teaches wherein the generating the plurality of sub call lists comprises generating the plurality of sub call lists such that the plurality of sub call lists are pipelined. (Catron [0009] FIG. 5 is a flow chart illustrating an embodiment of a process for allowing parallel and pipelined execution of a machine learning model network. [0013] Parallelization and pipelining of an execution of the machine learning model network is allowed based on the partitioning. [0031] Regardless of model complexity, memory bandwidth intensive operations can be split across accelerators to alleviate memory bottlenecks and compute intensive operations can be duplicated on different accelerators to allow for pipelining (decreasing latency of a sequence of machine learning computation requests) and allow for more options for execution. With more complex models, additional partitions may be created to better fit the models into on-chip memory.)
As per claim 6, Catron teaches wherein the generating the plurality of sub call lists comprises:
dividing, based on the quantity of the plurality of accelerators, parameter data applied to each of the plurality of primitive operations comprised in the original call list; and generating the plurality of sub call lists such that each of the divided parameter data is comprised in a corresponding one of the plurality of sub call lists. (Catron [0017] A machine learning model network may be regarded as a directed graph, wherein nodes of the directed graph correspond to machine learning model operators. In various embodiments, machine learning model operators (also referred to simply as operators) compute an output given an appropriate number and types of inputs and parameters. For example, an operator can correspond to an SLS operation. An operator can also correspond to a matrix multiply operation using an input tensor, a weights matrix, and/or a bias vector. [0018] In various embodiments, in addition to partitioning a machine learning model network across multiple machine learning accelerator hardware units, concurrent execution within a single machine learning accelerator hardware unit is allowed. Parts of the machine learning model network that that can be executed concurrently can be identified and run in parallel on a machine learning accelerator hardware unit. For example, in some embodiments, a sparse lookup is executed concurrently with a combination operation by an MLP. Concurrent execution can improve computational performance by splitting a machine learning model network into a memory bandwidth intensive portion and a compute intensive portion that run in parallel and saturate both the memory bus and the compute unit on a machine learning accelerator hardware unit to achieve higher throughput. [0022] In various embodiments, each accelerator receives input data. The input may be a tensor data object. The tensor can store various types of data. For example, for image recognition applications, the tensor may include image data (e.g., two-dimensional or three-dimensional images) [0029] The machine learning model network may be divided into several sub-networks and loaded onto multiple accelerators because it is too large to run on a single accelerator. For example, embedding tables used in sparse lookups may not fit into the memory of a single accelerator. Sparse lookups 232 and 234 can be divided so as to balance embedding table sizes across accelerators. It is also possible to divide them so as to balance runtimes across partitions (requiring performance information associated with the sparse lookups, e.g., as done in profile-guided partitioning as described in further detail herein). Splitting the machine learning model network can improve performance via model parallelism and [0031] Regardless of model complexity, memory bandwidth intensive operations can be split across accelerators to alleviate memory bottlenecks and compute intensive operations can be duplicated on different accelerators to allow for pipelining (decreasing latency of a sequence of machine learning computation requests) and allow for more options for execution.).
As per claim 11, Chodor teaches the trace comprises at least one of: a code associated with the source program; or a primitive operation associated with the source program; and the plurality of primitive operations are comprised in an operation library accessible to each of the plurality of accelerators. (Chodor [0030] The improved computing system technology uses a new C-like programming language allowing application developers to create source files [source program or code] that, when compiled, produce complex command lists having a set of hardware-specific executable commands for a GPU. This allows an application to dispatch a command list of the executable commands to a GPU command buffer for execution by the GPU. The command list can be a complex, mutable list of hardware instructions for the GPU and [0034] The source file includes software code written in a new, C-like language that is specifically designed to generate complex, mutable command lists of executable hardware instructions (i.e., executable hardware commands) specifically to be executed by the GPU without further interpretation or encoding by an API or driver. The source file is compiled with a new compiler 21 that is designed specifically to compile or interpret code written in the new C-like language and generate executable hardware commands that can be used to build a command list to take advantage of functionality of the GPU command streamer 25.).
As per claim 13, Carton teaches A non-transitory computer-readable medium storing instructions that, when executed, cause performance of the method of claim 1. (Catron [0011] The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor)
As per claim 12, it is rejected based on the same reason as claim 11.
As to claim 14, it is rejected based on the same reason as claim 1.
With respect to claim 14, a processor is shown above (see claim 1 rejection above which shows paragraph 11 of Catron teaching this).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chodor (US 2023/0138635 A1) in view of Catron (US 2024/0054384 A1) in further view of Ramesh (US 2021/0225443 A1).
As per claim 3, Chodor and Catron do not teach wherein the generating the plurality of sub call lists comprises inserting, into each of the plurality of sub call lists, a command for transmitting a calculation result obtained based on a corresponding one of the plurality of sub call lists to a specific accelerator, and wherein the specific accelerator is configured to receive, from each of the plurality of accelerators, the calculation result obtained based on the corresponding one of the plurality of sub call lists, and to generate, based on the calculation result received from each of the plurality of accelerators, output data associated with the original call list.
However, Ramesh teaches wherein the generating the plurality of sub call lists comprises inserting, into each of the plurality of sub call lists, a command for transmitting a calculation result obtained based on a corresponding one of the plurality of sub call lists to a specific accelerator, and wherein the specific accelerator is configured to receive, from each of the plurality of accelerators, the calculation result obtained based on the corresponding one of the plurality of sub call lists, and to generate, based on the calculation result received from each of the plurality of accelerators, output data associated with the original call list. (Ramesh [0013] The computing device can perform hardware acceleration by sending instructions and/or commands to a number of hardware accelerators to perform the operation. In some examples, a portion of the operation can be sent to a first hardware accelerator and a second portion of the operation can be sent to a second hardware accelerator. In some examples, the operation can be sent to a hardware accelerator for completion and the hardware accelerator can send a portion of the operation to an additional hardware accelerator to complete a portion of the operation. In this way, results from more than one hardware accelerator can be sent to the computing device to combine the results or a primary hardware accelerator can combine the results and send the completed result to the computing device).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Ramesh with the system of Chodor and Catron to use a calculation result of an operation. One having ordinary skill in the art would have been motivated to use Ramesh into the system of Chodor and Catron for the purpose of improving performance of the computing system. (Ramesh paragraph 14)
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chodor (US 2023/0138635 A1) in view of Catron (US 2024/0054384 A1) in further view of Nelson (US 11,934,802 B2).
As per claim 5, Chodor and Catron do not teach wherein the plurality of sub call lists comprise a first sub call list and a second sub call list, and
wherein the generating the plurality of sub call lists comprises inserting, into at least one of the first sub call list or the second sub call list, a command for providing output data obtained based on the first sub call list as input data of a primitive operation comprised in the second sub call list.
However, Nelson teaches wherein the plurality of sub call lists comprise a first sub call list and a second sub call list, and wherein the generating the plurality of sub call lists comprises inserting, into at least one of the first sub call list or the second sub call list, a command for providing output data obtained based on the first sub call list as input data of a primitive operation comprised in the second sub call list. (Nelson [col 8, lines 38-45] The one or more processors 202 may include one or more microprocessors capable of performing instructions stored in the memory 206. Additionally or alternatively, the one or more processors 202 may include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and/or other devices designed to perform some or all of the functions discussed herein without calling instructions from the memory 206. and [Claim 16]. The method of claim 13, wherein retrieving the output of the execution of the first set of functions or retrieving the output of the execution of the second set of functions comprises: executing a Callback function, a Retrieve Action function, a Retrieve Sub-flow function, a Retrieve Flow function, or a combination thereof, using the first unique identifier or the second unique identifier).
The examiner is interpreting this “command” according to what is disclosed in the specification ([0014] In addition, the creating the plurality of sub call lists may include inserting, into each of the plurality of sub call lists, a first command for transmitting a calculation result obtained based on each of the plurality of sub call lists to a predetermined specific accelerator, and inserting, into each of the plurality of sub call lists, a second command for sharing the calculation result obtained by the determined specific accelerator with each of the plurality of accelerators). This is being treated like a “callback” that returns the result or output of an operator (once acted upon by an accelerator).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Nelson with the system of Chodor and Catron to using a callback or a command. One having ordinary skill in the art would have been motivated to use Nelson into the system of Chodor and Catron for the purpose of improving the manner in which information workflows in certain data repositories may be automated, including cloned data repository information workflows. (Nelson col 1, lines 58-62)
As per claim 7, Chodor and Catron do not teach inserting, into each of the plurality of sub call lists, a first command for transmitting a calculation result obtained based on a corresponding one of the plurality of sub call lists to a specific accelerator; and inserting, into each of the plurality of sub call lists, a second command for sharing the calculation result obtained by the specific accelerator with each of the plurality of accelerators.
However, Nelson teaches wherein the generating the plurality of sub call lists comprises: inserting, into each of the plurality of sub call lists, a first command for transmitting a calculation result obtained based on a corresponding one of the plurality of sub call lists to a specific accelerator; and inserting, into each of the plurality of sub call lists, a second command for sharing the calculation result obtained by the specific accelerator with each of the plurality of accelerators. ( Nelson [col 8, lines 38-45] The one or more processors 202 may include one or more microprocessors capable of performing instructions stored in the memory 206. Additionally or alternatively, the one or more processors 202 may include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and/or other devices designed to perform some or all of the functions discussed herein without calling instructions from the memory 206. [Claim 16]. The method of claim 13, wherein retrieving the output of the execution of the first set of functions or retrieving the output of the execution of the second set of functions comprises: executing a Callback function, a Retrieve Action function, a Retrieve Sub-flow function, a Retrieve Flow function, or a combination thereof, using the first unique identifier or the second unique identifier).
This is “command” is being treated like a “callback” that returns the result or output of an operator (once acted upon by an accelerator).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Nelson with the system of Chodor and Catron to use a calculation result of an operator. One having ordinary skill in the art would have been motivated to use Nelson into the system of Chodor and Catron for the purpose of improving the manner in which information workflows in certain data repositories may be automated, including cloned data repository information workflows. (Nelson col 1, lines 58-62)
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chodor (US 2023/0138635 A1) in view of Catron (US 2024/0054384 A1) in further view of Yamato (US 2023/0385178 A1).
As per claim 8, Chodor and Catron do not teach wherein the transmitting each of the plurality of sub call lists comprises determining, based on a position of each accelerator comprised in accelerator position information, the plurality of accelerators to which a corresponding one of the plurality of sub call lists is to be transmitted.
However, Yamato teaches wherein the transmitting each of the plurality of sub call lists comprises determining, based on a position of each accelerator comprised in accelerator position information, the plurality of accelerators to which a corresponding one of the plurality of sub call lists is to be transmitted. (Yamato [0022] According to the present invention, even if the environment in which the plurality of types of accelerators coexist is the migration destination, the performance can be automatically improved. Further, when the migration destination has a plurality of types of accelerators in the same node, offloading is performed to the plurality of types of accelerators at the same time, thereby achieving faster offloading than in the case of using a single accelerator [0130] When acceleration with a plurality of accelerators is possible, capability of offloading to the same node is set as the first condition. A many-core CPU and a GPU of the same node can be candidates, but a GPU and an FPGA of another node cannot be candidates.).
The position of an accelerator is being treated as which node it is on. This is consistent with what is disclosed in the specification. This is consistent with what is disclosed in the specification ([0016] In addition, the determining the plurality of accelerators may include determining, based on the position of each the accelerator included in the accelerator position information, whether a node including the determined number or more of accelerators is searched, and if a node including the determined number or more of accelerators is searched, determining, from among all accelerators included in the searched nodes, the plurality of accelerators to which each of the plurality of sub call lists is to be transmitted).
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Yamato with the system of Chodor and Catron to use the position (i.e. location) of an accelerator. One having ordinary skill in the art would have been motivated to use Yamato into the system of Chodor and Catron for the purpose of offload control method using GPU and CPUs (Yamato paragraph 02).
As per claim 9, Yamato teaches The method according to claim 8, wherein the determining the plurality of accelerators comprises: determining, based on the position of each accelerator comprised in the accelerator position information, whether a node comprising the quantity or more of accelerators is identified; and based on a node comprising the quantity or more of accelerators being identified, determining, from among all accelerators comprised in the identified node, the plurality of accelerators to which a corresponding one of the plurality of sub call lists is to be transmitted. (Yamato [0022] According to the present invention, even if the environment in which the plurality of types of accelerators coexist is the migration destination, the performance can be automatically improved. Further, when the migration destination has a plurality of types of accelerators in the same node, offloading is performed to the plurality of types of accelerators at the same time, thereby achieving faster offloading than in the case of using a single accelerator [0130] When acceleration with a plurality of accelerators is possible, capability of offloading to the same node is set as the first condition. A many-core CPU and a GPU of the same node can be candidates, but a GPU and an FPGA of another node cannot be candidates. [0346] A fourth aspect of the present disclosure is the offload server according to the second aspect, wherein the at least one accelerator is a plurality of accelerators, wherein the at least one function block is a plurality of function blocks, wherein the at least one remaining loop statement for which the second performance is measured or the at least one loop statement for which the third performance is measured is a plurality of performance-measured loop statements, wherein the control section is further configured to, regarding offloading of the plurality of function blocks or the plurality of performance-measured loop statements: when a pattern faster than original processing is found for plural ones of the plurality of accelerators and a same function block or a same loop statement can be offloaded to the plural ones of the plurality of accelerators, select an accelerator providing higher performance as an offload destination among the plural ones of the plurality of accelerators; when first different function blocks among the plurality of function blocks or first different loop statements among the plurality of performance-measured loop statements can be offloaded to first different accelerators among the plurality of accelerators and cannot be offloaded to the first different accelerators of a same node, select an accelerator providing higher performance as an offload destination among the first different accelerators; and when second different function blocks among the plurality of function blocks or second different loop statements among the plurality of performance-measured loop statements can be offloaded to second different accelerators among the plurality of accelerators and can be offloaded to the second different accelerators of a same node, select the second different accelerators of the same node as offload destinations of the second different blocks or the second different loop statements)
The examiner believes this is consistent with what is disclosed in the specification ([0112] Meanwhile, a target accelerator to transmit the plurality of sub call lists 820 and 830 to may be determined based on the position of the accelerator. In order to minimize a communication delay between accelerators based on the commands inserted in the sub call lists 820 and 830, a target accelerator to transmit the plurality of sub call lists 820 and 830 to may be determined such that the first accelerator (GPU 0) and the second accelerator (GPU 1) that communicate with each other through the inserted commands are included in the same node)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chodor (US 2023/0138635 A1) in view of Catron (US 2024/0054384 A1) in further view of Yamato (US 2023/0385178 A1) and Ganju (US 2024/0129380 A1).
As per claim 10, Chodor and Catron and Yamato do not teach based on a determination that a node comprising the quantity or more of accelerators being not identified, determining the plurality of accelerators to which a corresponding one of the plurality of sub call lists is to be transmitted such that the plurality of accelerators are comprised in a plurality of adjacent nodes.
However, Ganju teaches based on a determination that a node comprising the quantity or more of accelerators being not identified, determining the plurality of accelerators to which a corresponding one of the plurality of sub call lists is to be transmitted such that the plurality of accelerators are comprised in a plurality of adjacent nodes. (Ganju [0045] For example, the scheduler 160 can receive a request or be programmed to optimize for temperature of the node—e.g., the scheduler 160 can train ML model 204 to select nodes for an operation in a manner that causes a least amount of increase in temperate at the node, at a rack, or at a data center when executing the operation. In such embodiments, the agent 202 can take an action 210 and select a first node to execute the operation at. The environment 204 can receive the action and simulate running the operation at the first node to predict a first temperature associated with performing the operation at the first node. In response to predicting the first temperature, the environment 204 can provide a next state 212 to the agent 202. In some embodiments, the agent 202 can receive the next state 212 and perform a second action 210 to select a second node to execute the operation at. The environment 204 can receive the second action 210 and simulate executing the operation at the second node to predict a second temperature associated with performing the operation at the second node. In such embodiments, the environment 204 can compare the first temperature with the second temperature. If the environment 204 determines the second temperature is less than the first temperature, the environment 204 can generate a positive next reward 214. If the environment determines the second temperature is greater than the first temperature, the environment 204 can generate a negative next reward 214. Accordingly, the agent 202 can update (e.g., re-train) the machine learning model 104 in response to receiving the next reward 214—e.g., the agent 202 can re-train the machine learning model 104 to take similar actions 210 if the next reward 214 is positive or re-train the machine learning model 104 to take different actions 210 if the next reward 214 is negative. The system 200 can continue to simulate actions 210 until the actions 210 no longer result in positive rewards 214 (e.g., the system is fully optimized) or until actions 210 result in a temperature that satisfies a target temperature threshold. In some embodiments, actions 210 can include selecting multiple graphics processing units (GPUs) within a same node, selecting multiple GPUs across different nodes (e.g., across adjacent nodes or nodes that not adjacent), selecting multiple GPUs across different racks, etc)
The examiner is treating this search for adjacent nodes as a condition that determines whether the GPUs can be fit on the same node (based on temperature constraints in Ganju) and if not to put the GPUs on an adjacent node.
It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Ganju with the system of Chodor and Catron and Yamato to find accelerators in adjacent nodes. One having ordinary skill in the art would have been motivated to use Ganju into the system of Chodor and Catron and Yamato for the purpose of scheduling utilizing reinforcement learning (Ganju paragraph 01)
Response to Arguments
Applicant's arguments filed on 08/07/2026 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claims 1 and 14 have been considered but are moot because the arguments do not apply because of the introduction of new art by Chodor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHRAN KAMRAN whose telephone number is (571)272-3401. The examiner can normally be reached on 9-5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor April Blair, can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MEHRAN KAMRAN/Primary Examiner, Art Unit 2196
