DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-18 are currently pending and have been examined.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/25/2024 has been considered by the examiner and an initialed copy of the IDS is hereby attached.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the combiner circuit". There is insufficient antecedent basis for this limitation in the claim as claim 14 depends on claim 10 which does not disclose any “combiner circuit”. The Examiner is interpreting claim 14 to depend on claim 11.
Allowable Subject Matter
Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In reference to dependent claim 9, the prior arts made of record individually or in
any combination, failed to teach, render obvious, or fairly suggest to one of ordinary skill in
the art at the time of filing the combination of the claimed features of “re-generate the LO signal from the modulated LO signal to obtain a re-generated LO signal, and
demodulate the binary clock signal from the modulated LO signal using the re-generated LO signal” of claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5,7,10-13 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melzer et al. (US 20200386854 A1), hereinafter Melzer, in view of Barrilado Gonzalez et al. (US 20190386810 A1), hereinafter Barrilado Gonzalez.
Regarding claim 1, MELZER discloses [Note: what MELZER fails to disclose is strike-through]
A cascaded radar system (see Figs. 5 and 6), comprising:
a primary monolithic microwave integrated circuit (MMIC) (see Fig. 5, MMIC 1; Fig. 6, Master Chip 1);
a secondary MMIC coupled to the primary MMIC via a signal channel (see Fig. 5, MMIC 12; Fig. 6, Slave Chip 2);
wherein the primary MMIC (see Fig. 5, MMIC 1; Fig. 6, Master Chip 1) is configured to:
combine a local oscillator (LO) signal with at least a second signal to generate a combined LO signal (see Fig. 6, at PLL 101 the clock signal is combined with the local oscillator signal to output a combined LO signal, SLO(t), further see paragraph 0030, “In accordance with FIG. 6, the master MMIC 1 comprises a local oscillator 101, which generates an LO signal s.sub.LO(t) e.g. with the aid of a phase locked loop on the basis of the clock signal s.sub.CLK(t).”);
transmit the combined LO signal to the secondary MMIC via the signal channel (see Fig. 6, the combined LO signal is transmitted to the secondary MMIC (i.e. slave chip 2));
wherein the secondary MMIC (see Fig. 6, slave chip 2 receives the combined LO signal) is configured to:
receive the combined LO signal via the signal channel (see Fig. 6, Slave Chip 2 receives the combined LO signal via the signal channel across which it is transmitted, also see Fig. 5, where the SLO(t) signal which is the combined LO signal is received by MMIC 2 via a signal channel),
perform radar operations based on the LO signal and at least the second signal (see Fig. 5, further see paragraph 0024, “FIG. 5 is a block diagram illustrating by way of example a MIMO radar system comprising a plurality of coupled (cascaded) MMICs. In the example illustrated, four MMICs are arranged on a carrier PCB, for example a printed circuit board (PCB). Each MIMIC 1, 2, 3 and 4 can comprise a plurality of transmitting channels TX01, TX02, etc. and a plurality of receiving channels RX01, RX02, etc. The system can also comprise MMICs that include a plurality of transmitting channels, but no receiving channels. For the operation of the radar system it is important for the LO signals used by the MMICs to be coherent. Therefore, the LO signal is only generated in one MIMIC—the master MMIC 1—and distributed to the slave MMICs 2, 3 and 4. In the example illustrated, for this purpose, the LO signal s.sub.LO(t) is passed from an LO output LO.sub.out of the master MIMIC 1 to the input of a power splitter 8; the outputs of the power splitter are connected to LO inputs LO.sub.in of the respective slave MMICs 2, 3 and 4.”, further see paragraph 0025, “For normal radar operation, the LO signal s.sub.LO(t) is generated centrally in the master MIMIC and distributed among the slave MMICs. What is achieved in this way is that the LO signals processed in the MMICs are coherent.”).
Barrilado Gonzalez discloses,
separate the LO signal and at least the second signal from the combined LO signal (see paragraph 0026, “At 322, the Master 102 determines a duration of the sequence of clock cycles based on a code. At 324, a Slave (e.g., 104, 106 or 108) demodulates the sequence of clock cycles to recover the clock and the RFS signal. In so doing, the cycle and RFS are phase aligned (e.g., a leading edge of the clock aligns with a leading edge of the RFS, within typical manufacturing and environmental tolerances). At 326, the code is decoded with the Slave based on the duration (e.g., 310, 312 or 314) of the clock sequence that has the higher amplitude due to modulation with the RFS signal. The code determines an action by the Slave in response to receiving a data signal (e.g., LO signal) from the Master.”);
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. Both references are considered analogous arts to the claimed invention as they both disclose cascading circuits used for radar operations. MELZER discloses combining of a clock signal with a LO signal in an MMIC to transmit to a second MMIC; however, MELZER fails to disclose the feature of “separate the LO signal and at least the second signal from the combined LO signal” in the second MMIC. This feature is disclosed by Barrilado Gonzalez where a clock signal and RFS (ramp frame start signal) are combined with the LO signal in a master circuit and this combined signal is transmitted to a slave circuit. The slave circuit then demodulates (i.e. separates) the clock signal and RFS signal from the LO signal to “recover” the clock and RFS signal. The combination would be obvious with a reasonable expectation of success in order to synchronize the cascading circuits for accurate radar detection.
Regarding claim 2, Melzer further discloses
The cascaded radar system of claim 1, wherein the signal channel comprises a printed circuit board (PCB) trace (see paragraph 0024, “FIG. 5 is a block diagram illustrating by way of example a MIMO radar system comprising a plurality of coupled (cascaded) MMICs. In the example illustrated, four MMICs are arranged on a carrier PCB, for example a printed circuit board (PCB).”, further see paragraph 0025, “The connection between the MMICs and the power splitter 8 can be realized e.g. by means of (e.g. differential) strip lines on the carrier printed circuit board PCB.”, where the signal channels are therefore a “PCB trace”), or a waveguide.
Regarding claim 3, the combination of MELZER and Barrilado Gonzalez discloses [Note: what MELZER fails to disclose is strike-through]
The cascaded radar system of claim 1, wherein the LO signal is a frequency modulated signal (see paragraph 0021, “The RF front end 10 comprises a local oscillator 101 (LO), which generates an RF oscillator signal s.sub.LO(t). The RF oscillator signal s.sub.LO(t), as described above with reference to FIG. 2, can be frequency-modulated and is also referred to as LO signal.”, further see Fig. 1)
Barrilado Gonzalez discloses,
the second signal is not frequency modulated (see Fig. 4, where the clock signals are not frequency modulated and rather binary clock signals).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. Both references are considered analogous arts to the claimed invention as they both disclose cascading circuits used for radar operations. MELZER discloses combining of a clock signal with a LO signal in an MMIC to transmit to a second MMIC; however, MELZER fails to disclose that the clock signal is not frequency modulated. This feature is disclosed by Barrilado Gonzalez where the clock signal is a binary clock signal. The combination would be obvious with a reasonable expectation of success in order to synchronize the cascading circuits for efficient and accurate radar detection.
Regarding claim 4, Melzer further discloses
The cascaded radar system of claim 1, wherein the second signal is a clock signal (see Fig. 6, at PLL 101 the clock signal is combined with the local oscillator signal to output a combined LO signal, SLO(t), further see paragraph 0030, “In accordance with FIG. 6, the master MMIC 1 comprises a local oscillator 101, which generates an LO signal s.sub.LO(t) e.g. with the aid of a phase locked loop on the basis of the clock signal s.sub.CLK(t).”), and
wherein a number of oscillations of the LO signal within a clock period of the clock signal constantly increases or constantly decreases within a ramp time interval of a LO frequency modulation (see Fig. 1, where the number of oscillations of the LO signal withing a clock period constantly increases within a ramp time interval of the LO frequency modulation).
Regarding claim 5, the combination of MELZER and Barrilado Gonzalez discloses [Note: what MELZER fails to disclose is strike-through]
The cascaded radar system of claim 1, wherein the primary MMIC is configured to:
modulate the LO signal with at least the second signal to obtain a modulated LO signal (see Fig. 6, at PLL 101 the clock signal is modulated with the local oscillator signal to output a combined LO signal, SLO(t), further see paragraph 0030, “In accordance with FIG. 6, the master MMIC 1 comprises a local oscillator 101, which generates an LO signal s.sub.LO(t) e.g. with the aid of a phase locked loop on the basis of the clock signal s.sub.CLK(t).”), and
transmit the modulated LO signal to the secondary MMIC via the signal channel (see Fig. 6, the combined LO signal is transmitted to the secondary MMIC (i.e. slave chip 2)), and
wherein the secondary MMIC (see Fig. 6, slave chip 2 receives the combined LO signal) is configured to:
Barrilado Gonzalez discloses,
demodulate the modulated LO signal to obtain the LO signal and at least the second signal for performing the radar operations (see paragraph 0026, “At 322, the Master 102 determines a duration of the sequence of clock cycles based on a code. At 324, a Slave (e.g., 104, 106 or 108) demodulates the sequence of clock cycles to recover the clock and the RFS signal. In so doing, the cycle and RFS are phase aligned (e.g., a leading edge of the clock aligns with a leading edge of the RFS, within typical manufacturing and environmental tolerances). At 326, the code is decoded with the Slave based on the duration (e.g., 310, 312 or 314) of the clock sequence that has the higher amplitude due to modulation with the RFS signal. The code determines an action by the Slave in response to receiving a data signal (e.g., LO signal) from the Master.”, where this process of synchronization is used for performing radar operations, further see paragraph 0020, “An MCU 150 includes a control interface 152 and a Camera Serial Interface 2 (CSI2) 160, 162, 164 and 168 for the Master 102, first Slave 104, second Slave 106 and third Slave 108 respectively. The CSI2 is a high-speed protocol under the Mobile Industry Processor Interface (MIPI) alliance. A raw RADAR data treatment 170 circuit receives data from the four CSI2 circuits 160, 162, 164 and 168 and transferred post processed data to a communication link 172 to a car, or other vehicle using the cascaded RADAR system.”);
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. Both references are considered analogous arts to the claimed invention as they both disclose cascading circuits used for radar operations. MELZER discloses combining of a clock signal with a LO signal in an MMIC to transmit to a second MMIC; however, MELZER fails to disclose the feature of “demodulate the modulated LO signal to obtain the LO signal and at least the second signal for performing the radar operations” in the second MMIC. This feature is disclosed by Barrilado Gonzalez where a clock signal and RFS (ramp frame start signal) are combined with the LO signal in a master circuit and this combined signal is transmitted to a slave circuit. The slave circuit then demodulates (i.e. separates) the clock signal and the RFS signal from the LO signal to “recover” the clock signal and RFS signal. The combination would be obvious with a reasonable expectation of success in order to synchronize the cascading circuits for accurate radar detection.
Regarding claim 7, the combination of MELZER and Barrilado Gonzalez discloses [Note: what MELZER fails to disclose is strike-through]
The cascaded radar system of claim 5,
Barrilado Gonzalez discloses,
wherein the primary circuit (see Fig. 1, Master 12)
modulate the LO signal with a binary clock signal and with a second binary signal (see paragraph 0035, “In one embodiment, a RADAR cascaded synchronization system comprises a first one of a plurality of RADAR systems forming a master including a clock modulation circuit configured to transmit a sequence of clock cycles of a clock, and to change an amplitude of the sequence of clock cycles in response to a Ramp Frame Start (RFS) signal. A code is defined by a duration of the sequence of clock cycles. A Local Oscillator (LO) transmitter circuit is configured to transmit an LO signal. A master state machine is configured to communicate the code to the clock modulation circuit to generate the sequence of clock cycles for at least the duration.”, where the Rampe Frame Start (RFS) signal is the “second binary signal”, further see paragraph 0039, “The master modulates an amplitude of the sequence of clock cycles in response to a Ramp Frame Start (RFS) signal received from a Microcontroller Unit (MCU). A code is determined by the slave from a duration of the sequence of clock cycles, wherein the code determines an action performed by the slave.”), and
transmit the modulated LO signal to the secondary MMIC via the signal channel (see paragraphs 0035 and 0037, where paragraph 0035 recites, “A second one of the RADAR systems forms a slave including a clock demodulation circuit configured to receive the sequence of clock cycles and to recover the clock and the RFS signal therefrom, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. A decoder is configured to determine the code by determining the duration of the sequence of clock cycles. An LO receiver circuit is configured to receive the LO signal and perform an action with a radio frequency circuit based on the code.”).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. Both references are considered analogous arts to the claimed invention as they both disclose cascading circuits used for radar operations. Barrilado Gonzalez discloses where a clock signal and RFS (ramp frame start signal) are combined with the LO signal in a master circuit and this combined signal is transmitted to a slave circuit. The slave circuit then demodulates (i.e. separates) the clock signal and the RFS signal from the LO signal to “recover” the clock signal and RFS signal. The combination of would be obvious with a reasonable expectation of success in order to synchronize the cascading circuits for accurate radar detection.
Regarding claim 10, the combination of MELZER and Barrilado Gonzalez discloses [Note: what MELZER fails to disclose is strike-through]
The cascaded radar system of claim 5,
Barrilado Gonzalez discloses,
wherein the primary circuit (see Fig. 1, Master 12)
modulate the second signal with a third signal to generate a modulated second signal (see paragraph 0035, “In one embodiment, a RADAR cascaded synchronization system comprises a first one of a plurality of RADAR systems forming a master including a clock modulation circuit configured to transmit a sequence of clock cycles of a clock, and to change an amplitude of the sequence of clock cycles in response to a Ramp Frame Start (RFS) signal. A code is defined by a duration of the sequence of clock cycles. A Local Oscillator (LO) transmitter circuit is configured to transmit an LO signal. A master state machine is configured to communicate the code to the clock modulation circuit to generate the sequence of clock cycles for at least the duration.”, where the Rampe Frame Start (RFS) signal is the “a third signal”, further see paragraph 0039, “The master modulates an amplitude of the sequence of clock cycles in response to a Ramp Frame Start (RFS) signal received from a Microcontroller Unit (MCU). A code is determined by the slave from a duration of the sequence of clock cycles, wherein the code determines an action performed by the slave.”), and
modulate the modulated second signal with the LO signal to generate the combined LO signal (see paragraphs 0035 and 0037, where paragraph 0035 recites, “In one embodiment, a RADAR cascaded synchronization system comprises a first one of a plurality of RADAR systems forming a master including a clock modulation circuit configured to transmit a sequence of clock cycles of a clock, and to change an amplitude of the sequence of clock cycles in response to a Ramp Frame Start (RFS) signal. A code is defined by a duration of the sequence of clock cycles. A Local Oscillator (LO) transmitter circuit is configured to transmit an LO signal. A master state machine is configured to communicate the code to the clock modulation circuit to generate the sequence of clock cycles for at least the duration. A second one of the RADAR systems forms a slave including a clock demodulation circuit configured to receive the sequence of clock cycles and to recover the clock and the RFS signal therefrom, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. A decoder is configured to determine the code by determining the duration of the sequence of clock cycles. An LO receiver circuit is configured to receive the LO signal and perform an action with a radio frequency circuit based on the code.”).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. Both references are considered analogous arts to the claimed invention as they both disclose cascading circuits used for radar operations. Barrilado Gonzalez discloses where a clock signal and RFS (ramp frame start signal) are combined with the LO signal in a master circuit and this combined signal is transmitted to a slave circuit. The slave circuit then demodulates (i.e. separates) the clock signal and the RFS signal from the LO signal to “recover” the clock signal and RFS signal. The combination of would be obvious with a reasonable expectation of success in order to synchronize the cascading circuits for accurate radar detection.
Regarding claim 11, the same cited section and rationale as claim 1 is applied.
Regarding claim 12, the same cited section and rationale as claim 3 is applied.
Regarding claim 13, the same cited section and rationale as claim 7 is applied.
Regarding claim 15, the same cited section and rationale as claim 1 is applied, where the feature of “activating” is implicit in the steps noted in the citations.
Regarding claim 16, the same cited section and rationale as claim 1 is applied.
Regarding claim 17, the combination of MELZER and Barrilado Gonzalez discloses [Note: what MELZER fails to disclose is strike-through]
The MMIC of claim 15,
Barrilado Gonzalez discloses,
wherein the second signal comprises a clock signal for analog to digital converters (ADCs) of the radar processing circuit (see paragraph 0021, “In example embodiments, the master clock 182 is used by an Analog to Digital Converter (ADC) to convert the received signal from the receiver circuit 124, in addition to other uses.”) or for a frequency-modulated continuous-wave (FMCW) ramp start signal for triggering a start of an FMCW ramp (see paragraph 0035, “In one embodiment, a RADAR cascaded synchronization system comprises a first one of a plurality of RADAR systems forming a master including a clock modulation circuit configured to transmit a sequence of clock cycles of a clock, and to change an amplitude of the sequence of clock cycles in response to a Ramp Frame Start (RFS) signal. A code is defined by a duration of the sequence of clock cycles. A Local Oscillator (LO) transmitter circuit is configured to transmit an LO signal. A master state machine is configured to communicate the code to the clock modulation circuit to generate the sequence of clock cycles for at least the duration.”, further see for support paragraph 0018, “The RFS signal is communicated to the Master 12 to begin a RADAR modulation or ramp (e.g., to start a RADAR frequency chirp). In various embodiments, the master clock generated by the Master 12 is also present at the Master 12 and the Slave 14”).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. Both references are considered analogous arts to the claimed invention as they both disclose cascading circuits used for radar operations. Barrilado Gonzalez discloses where a clock signal and RFS (ramp frame start signal) are combined where the RFS signal triggers the start of the FMCW ramp. The combination of would be obvious with a reasonable expectation of success in order to synchronize the cascading circuits for accurate radar detection.
Regarding claim 18, where the feature of “activating” is implicit in the steps noted in the citations.
Claim(s) 6,8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melzer et al. (US 20200386854 A1), hereinafter Melzer, in view of Barrilado Gonzalez et al. (US 20190386810 A1), hereinafter Barrilado Gonzalez, further in view of Heide (US 20060097906 A1).
Regarding claim 6, the combination of Melzer and Barrilado Gonzalez discloses [Note: what the combination of Melzer and Barrilado Gonzalez fails to disclose is strike-through]
The cascaded radar system of claim 5,
Heide discloses,
wherein the primary MMIC is configured to modulate the LO signal with at least the second signal in accordance with at least one of an amplitude-shift keying scheme, a frequency shift keying scheme, or a phase shift keying scheme (see paragraph 0056, “Amplitude shift keying ASK or frequency shift keying FSK are applicable e.g., for purposes of simple close distance data communication. Amplitude shift keying is achieved by switching the signal source (the oscillator or the transmission amplifier, if available) on and off at the clock rate of the data bits. Frequency shift keying is achieved by clocking a frequency regulating loop.”).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Heide into the invention of Barrilado Gonzalez in view of MELZER. The combination would be obvious with a reasonable expectation of success in order to utilize a known process to perform modulation of a signal simply and with low cost.
Regarding claim 8, the combination of Melzer and Barrilado Gonzalez discloses [Note: what Melzer fails to disclose is strike-through]
The cascaded radar system of claim 7,
Barrilado Gonzalez discloses [Note: what Barrilado Gonzalez fails to disclose is strike-through],
wherein the primary circuit (see Fig. 1, Master 12)
add the second binary signal as a DC offset (see paragraph 0003, further see paragraph 0026, “Turning to FIG. 5, a method for synchronizing a cascaded RADAR system is described. At 320, a master RADAR system modulates an amplitude of a sequence of clock cycles in response to an RFS signal. At 322, the Master 102 determines a duration of the sequence of clock cycles based on a code. At 324, a Slave (e.g., 104, 106 or 108) demodulates the sequence of clock cycles to recover the clock and the RFS signal. In so doing, the cycle and RFS are phase aligned (e.g., a leading edge of the clock aligns with a leading edge of the RFS, within typical manufacturing and environmental tolerances). At 326, the code is decoded with the Slave based on the duration (e.g., 310, 312 or 314) of the clock sequence that has the higher amplitude due to modulation with the RFS signal. The code determines an action by the Slave in response to receiving a data signal (e.g., LO signal) from the Master.”, where the RFS signal is added as a “DC offset” to phase align with the clock cycles).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Barrilado Gonzalez into the invention of MELZER. The combination would be obvious with a reasonable expectation of success in order to utilize a known processes to perform modulations of signals simply and with low cost.
Heide discloses,
modulate the LO signal with the binary clock signal according to an amplitude-shift keying scheme (see paragraph 0056, “Amplitude shift keying ASK or frequency shift keying FSK are applicable e.g., for purposes of simple close distance data communication. Amplitude shift keying is achieved by switching the signal source (the oscillator or the transmission amplifier, if available) on and off at the clock rate of the data bits. Frequency shift keying is achieved by clocking a frequency regulating loop.”).
It would have been obvious to someone with ordinary skill in the art prior to the
effective filing date of the claimed invention to incorporate the features as disclosed by Heide into the invention of Barrilado Gonzalez in view of MELZER. The combination would be obvious with a reasonable expectation of success in order to utilize a known processes to perform modulations of signals simply and with low cost.
Regarding claim 14, the same cited section and rationale as claim 6 is applied.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KHALID et al. (US 20190293784 A1) is considered close pertinent art to the claimed invention as it discloses cascaded MMIC radar chips (see Fig. 5).
STARZER et al. (US 20200025899 A1) is considered close pertinent art to the claimed invention as it discloses cascaded MMIC radar chips (see Fig. 8).
Searcy et al. (US 10641881 B2) is considered close pertinent art to the claimed invention as it discloses cascaded MMIC radar chips where a clock signal is recovered in the slave MMIC to remove jitter (see Fig. 4).
KHALID et al. (US 20190273502 A1) is considered close pertinent art to the claimed invention as it discloses cascaded MMIC radar chips where a clock signal is distributed across multiple cascaded MMIC (see Fig. 6, data clock signal 630).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAZRA N. WAHEED whose telephone number is (571)272-6713. The examiner can normally be reached M-F (8 AM - 4:30 PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vladimir Magloire can be reached at (571)270-5144. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NAZRA NUR WAHEED/Examiner, Art Unit 3648