DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-24 of the current application (18/422946) is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of copending Application No.18/422,920 (US20250247055A1) and also over claims 1-19 of the copending Application No.18/422,906 (US20250244167).
A cross-reference of the pending claims in the current application with the claims of co-pending applications 18/422,920 and 18/422,906 demonstrates substantial overlapping subject matter.
Claim 1 of Current Application recites a device comprising a logarithmic transimpedance amplifier (TIA) device and a processor. The TIA is configured to generate first, second, and third digital signals during distinct time intervals (corresponding to temperature, log input current, and log reference current, respectively). The processor calculates a logarithmic ratio of the input current and reference current.
Claim 1 of 18/422,920 recites a method comprising the identical steps of generating first, second, and third digital signals during the same respective time intervals using a device comprising a logarithmic TIA and a processor, and determining the same logarithmic ratio.
Claim 1 of 18/422,906 recites a system comprising a first device (configured to generate and output the analog thermometer signal, analog voltage signal, and second analog voltage signal) and a second device (configured to digitize these signals over first, second, and third time intervals and calculate the logarithmic ratio).
The current application and the co-pending applications share an identical inventive entity and common ownership.
The structural apparatus limitations of Claim 1 in the current application merely recite a hardware device configured to execute the exact functional steps defined in the method claims of the copending application 18/422,920. Under established patent law, claiming a method of operating a device is generally not patentably distinct from claiming the device itself configured to perform that method, unless the device can perform patentably distinct alternative methods.
Similarly, the division of the system into a "first device" and a "second device" in copending application 18/422,906 represents an insubstantial, obvious modification of the unified "device" architectures recited in the current application’s claims 1 and 21. The underlying technical features—multiplexed digital sampling of temperature and compressed logarithmic input/reference signals to determine a corrected current ratio—are identical and lack patentable distinction.
The modifications across these three applications represent insubstantial variations of form (Device vs. Method vs. System) rather than patentably distinct inventions. A person having ordinary skill in the art would find it obvious to express the same underlying core hardware layout as a series of operational method steps or as an interconnected split-device system configuration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-8, 11-13, 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Suzunaga (US 2008/0054163 A1) in view of Ceballos et al. (US 2023/0344398 A1).
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Fig. 1 of Suzunaga block diagram showing a logarithmic compression
analog-digital conversion circuit.
Regarding Claims 1, 19 and 21, Suzunaga teaches a device comprising a logarithmic amplifier (Fig. 1, 30, §0019-§0020) configured to logarithmically convert an input current to a voltage, functioning as a transimpedance amplifier.
Suzunaga discloses generating an analog voltage signal that is logarithmically proportional to an input current utilizing the forward characteristics of a p-n junction (§0007, §0019).
Suzunaga discloses a reference current source (24, Fig. 1, §0021, §0024) that generates a reference current.
Suzunaga teaches temperature-dependent reference voltage sources (261, 262, Fig. 1, Fig. 6A-6B, §0024, §0032) that output an analog voltage dependent on ambient temperature, which serves as an analog thermometer signal.
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Figs. 6A (left) and 6B(right) of Suzunaga representing circuits of the temperature dependent reference voltage source.
Suzunaga teaches outputting these analog signals to an A/D converter (60, Fig. 1, §0024, §0030) to generate digital output signals based on the analog voltages.
These elements correspond to the foundational device and signal generation limitations of Claims 1, 19, and 21.
Suzunaga, however, does not explicitly disclose a processor functionally coupled to the logarithmic transimpedance amplifier device that is specifically configured to determine a logarithmic ratio of the input current and the reference current.
Furthermore, Suzunaga does not explicitly detail generating the respective digital signals (thermometer signal, input current signal, and reference current signal) over separated, distinct time intervals (first, second, and third intervals) for the purpose of a ratio determination by a processor.
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Fig. 1A (left) and 1B (right) of Ceballos representing exemplary
logarithmic amplifier system comprising an analog programmable gain amplifier, an analog-to-digital converter (ADC), and a digital anti-logarithmic component.
Ceballos, in a similar field of endeavor, teaches a logarithmic amplifier system comprising an analog programmable gain amplifier (PGA, Fig. 1A), an analog-to-digital converter (ADC 106, Fig. 1A-1B, §0024-§0025), and digital signal processing components.
Ceballos teaches the integration of a microprocessor (908, Fig. 9, §0041) that communicates with the ASIC components via bidirectional buses (914, 916, Fig. 9, §0041) to process digital signals and provide the functionality of digital or software components.
Ceballos also discloses utilizing the microprocessor and digital components (108, Fig. 1B, §0025) to process digitized logarithmic signals to generate linearized digital signals and compensations corresponding to the analog input.
It would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) to modify the logarithmic-compression analog-digital conversion circuit of Suzunaga to include the microprocessor and digital processing architecture of Ceballos.
Specifically, a PHOSITA would find it obvious to couple the microprocessor (908, Fig. 9) taught by Ceballos to the A/D converter (60, Fig. 1) of Suzunaga to receive the digitized signals representing the temperature (thermometer signal), the input current, and the reference current over sequential time intervals. The processor would logically be configured to compute the logarithmic ratio of the input current to the reference current using these digitized signals to achieve a highly accurate, digitally processed output.
The motivation to incorporate the microprocessor and digital signal processing of Ceballos into the architecture of Suzunaga is to simplify the anti-logarithmic digital signal processing and to maintain a quasi-constant signal-to-noise ratio (SNR) over a wide input signal range (§0023).
Additionally, utilizing a microprocessor to digitally compute the ratio of the input and reference currents alongside a digitized temperature signal provides a highly precise, software-adjustable temperature compensation method. This directly solves the problem addressed in Suzunaga, which explicitly seeks to reduce output errors caused by the temperature dependence of logarithmic amplifiers (§0007, §0020).
Regarding Claim 2 (Averaging Signals), Suzunaga teaches that the initial logic and parameters are validated. Suzunaga also teaches an adder (56, Fig. 5, §0045) used for averaging digital signals. Suzunaga, however, does not explicitly specify determining averages of multiple distinct first, second, and third digital signals specifically in a processor to compute a log ratio.
Ceballos, in a similar field of endeavor, teaches using a microprocessor 908 to process digital signals and perform digital algorithms.
It would be obvious to modify Suzunaga to utilize the microprocessor (908, Fig. 9, §0041) of Ceballos in conjunction with the adder to calculate mathematical averages before computing the final ratio to reduce noise, smooth transient signal variations, and improve the overall Signal-to-Noise Ratio (SNR) of the digital output (§0023), which is a stated objective in Ceballos.
Regarding Claims 3 & 20 (Digital Calibration & Temp Correction), Suzunaga teaches canceling temperature variations using temperature-dependent reference voltages ((261, 262, Fig. 1, Fig. 6A-6B, §0024, §0032). Suzunaga, however, does not explicitly teach adding a digital calibration value to the thermometer signal to determine a temperature-dependent correction in the digital domain.
Ceballos, in a similar field of endeavor, teaches digital signal processing components (anti-logarithmic component 108) capable of applying specific offsets and linear corrections to digitized signals.
It would be obvious to modify Suzunaga to perform the temperature-dependent correction mathematically in the digital domain using the microprocessor (908, Fig. 9, §0041) of Ceballos by applying a stored digital calibration value.
Implementing calibration digitally simplifies the analog circuitry and allows for highly flexible, software-adjustable post-processing (§0023) to correct for p-n junction temperature dependence.
Regarding Claims 5 & 13 (Second Input/Reference Currents), Suzunaga teaches a system with a first photodiode 52 (52, Fig. 5, §0044) and a second photodiode (50, Fig. 5, §0044) providing multiple current input sources.
Suzunaga, however, does not explicitly frame this as generating distinct digital signals for a second input and reference current for a second log ratio.
Ceballos, in a similar field of endeavor, teaches a scalable architecture using multiple parallel programmable gain paths (A1, A2, A3) to process distinct analog signals.
It would be obvious to modify Suzunaga to explicitly process the second input current from the second photodiode (and a second reference current) using the parallel digital processing architecture (104A-C, Fig. 1B, §0025) taught by Ceballos to expand the dynamic range and handle different spectrums (visible vs. infrared light) independently (§0047), ensuring accurate measurement across multiple signal paths.
Regarding Claims 6 & 22 (ADC Sampling), Suzunaga explicitly teaches an A/D converter 60 (Fig. 1, §0024) that converts analog output voltages into digital representations. Suzunaga, however, does not explicitly detail sequentially sampling the exact thermometer and voltage signals over defined intervals.
Ceballos, in a similar field of endeavor, teaches using an ADC 106 coupled with digital logic to sequentially sample and convert analog inputs.
It would be obvious to explicitly configure the A/D converter 60 of Suzunaga to sample the thermometer and reference analog signals sequentially as taught by Ceballos (106, Fig. 1A-1B, §0024-[0025), utilizing a single ADC to sample multiple analog signals over distinct time intervals is a standard, cost-effective electronics method to digitize all parameters without duplicating expensive ADC hardware.
Regarding Claim 7 (Integrated ADC), Suzunaga explicitly teaches that the logarithmic amplifier 30 and the A/D converter 60 are put on one chip to form an integrated circuit 70 (Fig. 5, §0045), integrating the ADC and logarithmic amplifier on a single die reduces temperature differentials between the components, improving accuracy as stated by Suzunaga.
Regarding Claim 8 (Compensation Current Subtraction), Suzunaga teaches a current mirror circuit 53 (Fig. 5, §0044) used to subtract currents (e.g., subtracting infrared current from visible light current).
Suzunaga, however, does not explicitly teach subtracting a digitally computed compensation current derived from a calibrated signal.
Ceballos teaches processing digital signals to compute offsets and utilizing anti-log transfer functions.
It would be obvious to modify Suzunaga to calculate a specific compensation current digitally based on the calibrated signal and subtract it from the input current utilizing the components of Ceballos (108, Fig. 1B, §0024-§0025) to dynamically adjust and remove parasitic or dark currents via digital logic, significantly improving the accuracy of the logarithmic digital output.
Regarding Claim 11 (Serial Interface), Suzunaga explicitly teaches an I2C interface 58 (Fig. 5, §0045) configured to exchange digital signals utilizing an I2C interface is a standard, robust communication protocol essential for integrating the sensor into portable devices like mobile phones.
Regarding Claim 12 (Current Generator Device), Suzunaga explicitly teaches a reference current source 24 (Fig. 1, §0021) connected to the logarithmic amplifier. A reference current generator is necessary to set a stable baseline prescribed value for accurate logarithmic compression (§0027).
Regarding Claims 17 & 18 (WLCSP Packaging), Suzunaga teaches that the entire system (photodiodes, current mirror, log amp, ADC) is formed on one chip as an integrated circuit 70 (Fig. 5, §0045). Suzunaga, however, does not explicitly mention the acronym "WLCSP" (Wafer Level Chip Scale Package).
Ceballos mentions integrated circuit area reduction and ASIC implementations for MEMS packaging.
It would be obvious to package the integrated circuit 70 (Fig. 5) of Suzunaga using standard Wafer Level Chip Scale Packaging (WLCSP) as supported by the ASIC integrations in Ceballos (904, Fig. 9, §0041) because WLCSP is a universally known, industry-standard packaging technique used extensively in mobile phones (the target application of Suzunaga) to minimize physical device size (§0002) and manufacturing costs.
Allowable Subject Matter
Claims 4, 9-10, 14-16 and 23-24 are objected to as being dependent upon a rejected base claim 1 and 21 respectively but would be allowable if rewritten in independent form including all of the limitations of the base claim 1 and 21 and any intervening claims.
Claims 4 and 23 require "sensing circuitry that includes a current digital-to-analog converter that is driven by a digital calibration value". Neither Suzunaga nor Ceballos discloses a current digital-to-analog converter (IDAC) specifically utilized to generate an analog thermometer signal.
Claims 9, 10, and 24 recite a highly specific mathematical calibration condition where the digital calibration value causes "a logarithmic ratio of a first output... to be equal to a logarithmic ratio of the first input calibration current and the second input calibration current". The cited references do not disclose this algorithmic calibration method.
Claim 14 requires "multiple multiplying current digital-to-analog converter devices" (MDACs). The applied prior art lacks any disclosure of MDAC hardware.
Claim 15 requires determining a voltage offset by multiplying the input current by an "emitter-resistance equivalent value". Neither reference mentions non-ideality correction specific to an emitter-resistance equivalent.
Claim 16 requires determining a compensation current by evaluating a "polynomial function of input current". Neither reference discloses using polynomial functions for logarithmic conformance correction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights