DETAILED ACTION
This action is responsive to the following: the amendments to claims and arguments made in amendment filed on January 16, 2026 and the information disclosure statements filed on December 8th, 2025 and April 1, 2026.
Claims 1-20 are pending. Claims 1, 9, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 8th 2025 and April 1, 2026 were filed after the mailing date of the FAOM on October 17, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendments filed on January 16, 2025 have been entered. Claims 1-20 remain pending.
Claim Interpretation
Claims 1-6, 9, 11-12, and 19 recite “signed inputs,” referring signals on the wordlines, “signed weights” referring to threshold voltages of memory cells, and “signed results” referring to the output of a device that is “based on” summed currents on bit lines.
Kirchoff’s Current Law is implicated, which summarizes as: the electrical current output at a node is equal to the sum of the electrical currents input to the node.
The “signed input” and “signed weight” do not refer to the sign of a voltage, the sign of a threshold voltage of a memory cell, or the sign of the output from a comparator circuit. The “signed” aspect of the input and weight simply represents a label applicant used for a particular combination of voltages applied to two different bit lines or combination of data stored in two memory cells.
Application Figure 16 illustrates the “signed” input is simply a label, when word line voltage is applied, for three combinations of the voltages applied to two bitlines (e.g., BL1, BL2) at two different times (i.e., T0, T1), which is best described in applicant’s Specification paragraphs 354–360. A table prepared by the Examiner is below, which exemplifies the three combinations and the “sign” applicant labels for each combination:
While WL = V
“sign”
BL1 at T0
BL2 at T0
BL1 at T1
BL2 at T1
“-1” (i.e., negative sign)
-V
0
0
-V
“0” (i.e., no sign)
0
0
0
0
“+1” (i.e., positive sign)
0
-V
-V
0
The Examiner’s Markups of Application Figure 15 illustrate the “signed” weight is simply a label applicant uses for three combinations of data stored in two memory cells.
PNG
media_image1.png
737
793
media_image1.png
Greyscale
As illustrated in the 1st Examiner’s Markup of application Figure 15, when the two memory cells store “01” then applicant labels this “weight” as “-1” (i.e., negative sign).
PNG
media_image2.png
737
775
media_image2.png
Greyscale
As illustrated in the 2nd Examiner’s Markup of application Figure 15, when the two memory cells store “00” then applicant labels this “weight” as “0” (i.e., no sign).
PNG
media_image3.png
724
802
media_image3.png
Greyscale
As illustrated in the 3rd Examiner’s Markup of application Figure 15, when the two memory cells store “10” then applicant labels this “weight” as “+1” (i.e., positive sign).
Additionally, Figure 8 shows an operating range of exemplary memory cells, which have two data states both represented by positive threshold voltages. Therefore, it is understood that certain threshold voltages programmed into cells are not actually data bits, but are simply the storage vehicle utilized by the memory cell employed (e.g., EEPROM have variable threshold voltages that “represent” distinct data states, but the number of data states is determinative by the read voltages applied at a later time).
Therefore, the term “signed,” as an adjective for claim terms (i.e., weight, input, result), is not interpreted as being an actual sign, positive or negative, because it is not. Instead, the adjective “signed” is interpreted consistent with applicant’s disclosure as merely a label ascribed to exemplary voltage patterns as indicated above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 7-8 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al (US 20220398438).
Regarding Independent Claim 1, Zhang teaches a device comprising:
a memory cell array (Fig. 5: 502) having sets of memory cells (Fig. 15: 1501-1 to 1501-n), wherein each set is programmable to store a signed weight (Fig. 20: 2001);
voltage drivers configured to apply voltages (Fig. 20: 2011) to the memory cells in each set, the voltages corresponding to a signed input to be multiplied by the signed weight for each set (Fig. 20: 2015);
at least one line coupled to each set, wherein the line is configured to sum output currents from the sets (Fig. 20: 2017).
Regarding Claim 4, Zhang teaches the limitations of Claim 1. Zhang further teaches wherein:
a first bit result and a second bit result are based on summing the output currents from the sets; and
a magnitude of the signed result is determined based on a difference between magnitudes of the first and second bit results (Fig. 18: GSL; figure 18 shows the summing of currents from different set of cells connected to local source lines. It would follow that the magnitude of the output would be based on the sum of these currents.)
Regarding Claim 7, Zhang teaches the limitations of Claim 1. Zhang further teaches the voltages are applied to each set at first and second time instances (para 82 “The memory cells of a NOR string are usually read one at a time to extract their individual data content.”); and
at least one line is configured to sum the output currents from the sets for each of the first and second time instances (Fig. 18: GSL)
Regarding Claim 8, Zhang teaches the limitations of Claim 1. Zhang further teaches wherein the memory cells are resistive random-access memory (RRAM) cells, NAND flash memory cells, or NOR flash memory cells (Fig. 15: NOR string).
Regarding Independent Claim 19, Zhang teaches A method comprising:
programming sets of memory cells (Fig. 15: 1501-1 to 1501-n) in a memory cell array (Fig. 5: 502), wherein each set of memory cells (Fig. 15: 1501-1 to 1501-n) is programmed to store a signed weight (Fig. 20: 2001);
applying voltages to the sets (Fig. 20: 2011), wherein for each set the voltages represent a respective signed input to be multiplied by the signed weight stored in the set (Fig. 20: 2015); and
determining a signed result based on summing output currents from the sets on at least one line (Fig. 20: 2017);
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 20220398438) in view of Lesso et al (US 20200356848 A1).
Regarding Claim 2, Zhang teaches the limitations of Claim 1. Zhang fails to teach one set represents a negative signed weight and one set represents a positive signed weight.
Lesso teaches herein each set includes first (Fig. 2: 203p) and second cells (Fig. programmable to store a positive version of the signed weight, and third and fourth cells (Fig. 2: 203n) programmable to store a negative version of the signed weight.
Having some cells correspond to a negative weight and positive weight allows for signed multiplication. Designating specific sets of cells such that they correspond to one sign or the other allows for performing operations such that the cells selected can produce a signed output based on the operation performed by the device.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lesso to the teachings of Zhang to produce a memory device capable of multiplying weighted values where the sets are divided between negative and positive signed values.
Regarding Claim 3, Zhang and Lesso teach the limitations of Claim 2. Zhang further teaches lines attached to different sets of cells (Fig. 16: WL0-WLn, 1600, 1601i, page).
Regarding Claim 5, Zhang teaches the limitations of Claim 1.
Zhang teaches at least one digitizer (Fig. 18: 1850), the digitizer configured to provide a signed result based on summing the output currents from the sets (para 100 “the output from the sense amplifiers 1850 can either be an analog value or an analog to digital conversion can convert the current value to a digital value.”).
Zhang fails to teach summing the currents to determine the sign.
Lesso teaches summing the currents to determine the sign of the output (para 116 “In some embodiments, as described above, separate weighted sums may be determined for the positive and negative current components and thus the output OUT.sub.S may itself comprise positive and negative components, e.g. a positive weighted sum OUT.sub.PS and a negative weighted sum OUT.sub.NS, although in other embodiments the combiner module 206 may generate a single value based on the weighted sum of the differential outputs from the memory cells.”).
Determining the sign of the output from the sum of the input currents is advantageous because it would allow that to be determined as part of the same process as determining the magnitude. Thus, allowing for faster computing times.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lesso to the teachings of Zhang to produce a memory device that determines the sign of the output based on one the differences in the magnitudes of the summed currents.
Regarding Claim 6, Zhang teaches the limitations of Claim 1. Zhang further teaches the voltages are applied to first and second cells in each set at first and second time instances (para 82 “The memory cells of a NOR string are usually read one at a time to extract their individual data content.”);
Zhang fails to teach positive and negative signs from different sets of cells.
Lesso teaches different sets of cells corresponding to different signs (Fig. 2: 203p, 203n).
The rationale for combining is the same as claims 2 and 5.
Claims 9-11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 20220398438) in view of Li et al (US 20220044719).
Regarding Independent Claim 9, Zhang teaches an apparatus comprising:
a plurality of sets (Fig. 5: 502) each having two or more memory cells (Fig. 15: 1501-1 to 1501-n), and
a controller (Fig. 5: 520, 510) configured to:
program the memory cells of each set to store the respective signed weight (Fig. 20: 2001);
apply voltages to the sets (Fig. 20: 2011), wherein the voltages are based on the data received from the sensor, and wherein for each set the voltages represent a respective signed input to be multiplied by the respective signed weight stored in the set (Fig. 20: 2015); and
determine a signed result based on summing output currents from the sets on at least one line (Fig. 20: 2017);
However, Zhang fails to teach a sensor.
Li teaches a sensor (Fig. 8b: 872).
Using such a memory device that can multiply inputs is useful for managing the large amounts of data produced by sensors.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Li to the teachings of Zhang to produce an apparatus that contained a sensor and sets consisting of two or more memory cells which can be used to multiply signed weights together.
Regarding Claim 10, Zhang and Li teach the limitations of Claim 9. Li teaches at least one line comprises first and second lines (Fig. 1: 102_1, 102_2); and
summing the output currents (Fig. 1: 120_1, 120_2) comprises determining a first sum of output currents on the first line, and determining a second sum of output currents on the second line.
Regarding Claim 11, Zhang and Li teach the limitations of Claim 10. Zhang teaches wherein a magnitude of the signed result is based on a difference in magnitudes of the first and second sums. (Fig. 18: GSL; figure 18 shows the summing of currents from different set of cells connected to local source lines. It would follow that the magnitude of the output would be based on the sum of these currents.)
Regarding Claim 13, Zhang and Li teach the limitations of Claim 9. Zhang teaches wherein the line is a digit line (Fig. 16: GSL1, GSL2), the apparatus further comprising:
bitlines (Fig. GBL1, GBL2) coupled to each set (Fig. 16: 1600); and
select transistors (Fig. 16: SG1, SG2) configured to electrically connect the bitlines (Fig. GBL1, GBL2) of each set to the digit line.
Regarding Claim 14, Zhang and Li teach the limitations of Claim 13. Zhang further teaches wherein the voltages are applied to gates of the select transistors (para 100 “To perform the multiplication between the activations and weights of a layer of a neural network, the corresponding select gate are turned on”).
Regarding Claim 15, Zhang and Li teach the limitations of Claim 9. Zhang teaches wherein summing the output currents comprises determining a first sum of output currents on the line in a first clock cycle, and determining a second sum of output currents on the line in a second clock cycle (para 82 “The memory cells of a NOR string are usually read one at a time to extract their individual data content.”).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 20220398438) and Li et al (US 20220044719) in view of Lesso et al (US 20200356848).
Regarding Claim 12, Zhang and Li teach the limitations of Claim 10. Zhang and Li fail to teach summing the currents to determine the sign.
Lesso teaches summing the currents to determine the sign of the output (para 116 “In some embodiments, as described above, separate weighted sums may be determined for the positive and negative current components and thus the output OUT.sub.S may itself comprise positive and negative components, e.g. a positive weighted sum OUT.sub.PS and a negative weighted sum OUT.sub.NS, although in other embodiments the combiner module 206 may generate a single value based on the weighted sum of the differential outputs from the memory cells.”).
Determining the sign of the output from the sum of the input currents is advantageous because it would allow that to be determined as part of the same process as determining the magnitude. Thus, allowing for faster computing times.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Lesso to the teachings of Zhang and Li to produce a memory device that determines the sign of the output based on one the differences in the magnitudes of the summed currents.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 20220398438) and Li et al (US 20220044719) in view of Seo et al (US 20210073621 A1).
Regarding Claim 16, Zhang and Li teach the limitations of Claim 9. Zhang and Li fail to teach a NAND flash memory device.
Seo teaches a NAND flash memory device (Fig. 1: 300).
NAND memory is denser than NOR or resistive non-volatile memories. Thus, it would represent an obvious variant to use if denser or larger amounts of memory are required.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Seo to the teachings of Li and Zhang to produce an apparatus with a sensor and memory devices capable of multiplying inputs using the programmed weighted values in the memory array.
Regarding Claim 17, Zhang, Li, and Seo teach the limitations of Claim 16. Seo further teaches wherein when performing multiplication, one or more memory cells in each set are selected by applying a respective read voltage to gates of the memory cells (para 51 “For example, in a read operation, a plurality of word line voltages have levels of a read voltage VRead or a pass voltage VPass, respectively.”).
Regarding Claim 18, Zhang, Li, and Seo teach the limitations of Claim 16. Seo further teaches wherein gates of non-selected memory cells in a respective same string with the selected memory cells are biased by applying a bypass voltage to the gates during the multiplication (para 51 “For example, in a read operation, a plurality of word line voltages have levels of a read voltage VRead or a pass voltage VPass, respectively.”).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 20220398438) in view of Tran et al (US 20210280240).
Regarding Claim 20, Zhang teaches the limitations of Claim 19. Zhang fails to teach an integrator.
Tran teaches and integrator (Fig. 26: 2600), used to sum the current as it accumulates over a specific time period in order to perform certain operations on input data.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Tran to the teachings of Zhang to produce a circuit that integrates the current on the bit lines using an integrator, such that current can be summed for use in artificial neural network calculations.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Applicants arguments against the rejections of claims 1 and 19 under 35 U.S.C. 102 (a)(1) and the rejection of claim 9 under 35 U.S.C. 103 have to do mainly with the fact that Zhang fails to teach “signed weights” and “signed inputs” however as shown in the rejections from the FAOM, Zhang teaches “weighted threshold voltages” and “input voltage levels” of various magnitudes. Since “signed weights” and “signed inputs” merely refer to how positive voltages are interpreted these terms are understood not to refer to analog voltages that are positive or negative, but merely how relative magnitude of positive voltages are converted from or to binary values that correspond to negative numbers. Therefore, the difference between a “signed weight” and a “weighted threshold voltage” (or “signed input” and “input voltages leves”) is merely a difference in terminology for labels and not a difference in the sign of the voltages themselves. MPEP 2131 states that for anticipation “The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required.”
Applicant also argued that in claim 9 Zhang fails to interpret a “signed result” however, for the reasons outlined with respect to the limitations of “signed inputs” and “signed weights,” a signed result is understood to merely be difference in terminology and not a difference in the claim element. And therefore, the argument is found to not be persuasive.
Finally, applicant argues that that Zhang and Li individually fail to teach voltages driven by a sensor. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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