Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on June 12, 2026 has been entered.
General Remarks
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 9 and 18.
Claims 1-2, 9-10 and 18-19 has been amend.
c. Claims 1-20 are pending on the application.
Drawings
3. The drawings were received on 01/25/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 07/15/26. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claim(s) 1, 3 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,144,589 to Micheloni et al. (hereafter Micheloni et al).
Regarding Independent Claim 1, Micheloni et al in Figures 1-4 are directly discloses a device (a boosting circuit associated to a row decoding circuit of a memory device, Figures 1 and 4) comprising:
a memory cell array having memory cells (a matrix of memory cells 16, Fig. 1, and a memory half-sector S1-1…..S2-2), wherein each memory cell is programmable to store a bit having one of a plurality of significances, and wherein first memory cells are configured to store a first multi-bit weight (the matrix of memory cell 16 and memory half-sector S1-1…S2-2 use as a programming for store a bit); and
voltage drivers (a boosting circuit A composed by a sub-circuit A1, a sub-circuit A2 and a boosting circuit 72 by the voltage boosting circuit 70, Fig. 1) configured to apply voltages to the memory cells, wherein the voltages include first voltages representing a first input to be multiplied by the first multi-bit weight (the boosting circuit A composed by the sub-circuit A1 and the sub-circuit A2 that capable of generating on respective node 7 and node 8 as the boosting voltage of the value higher than a voltage supply Vcc, see at least in Figures 1 and 4, column 3, lines 15-37, column 7, lines 24-55 and the related disclosures).
Regarding dependent Claim 3, Micheloni et al in Figures 1-4 are directly discloses a device (a boosting circuit associated to a row decoding circuit of a memory device, Figures 1 and 4) wherein each of the first memory cells (the matrix of memory cells 16) is a NAND flash memory cell (the memory cell matrix 16 is the nonvolatile memory such as Flash EEPROM, column 1, lines 6-7), the device further comprising a common wordline coupled to a gate of each first memory cell (the memory cell 16 is a flash memory such as the nonvolatile the word-line coupled to the gate of the memory cells 16, Fig. 1).
Regarding dependent Claim 8, Micheloni et al in Figures 1-4 are directly discloses a device (a boosting circuit associated to a row decoding circuit of a memory device, Figures 1 and 4) wherein the memory cells (the matrix of memory cells 16, Fig. 1) of the array are resistive random access memory cells (the nonvolatile memory cell 16 such as a resistive random access memory cell in memory).
Allowable Subject Matter
6. Claims 2 and 4-7, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, further comprising: common line coupled to each of the first memory cells, wherein the common line is configured to sum output currents from the first memory cells; at least one digitizer configured to provide at least one result based on summing the output currents; wherein the respective output current from each first memory cell corresponds to a significance of the respective bit stored by the first memory cell; and wherein the magnitudes of the output currents from the first memory cells are configured to differ from one another by a power of two based on the significance of the respective bit.
With respected to dependent claim 4, the prior art fails to tech or suggest the claimed limitations, namely, a fixed bias is applied to the common wordline when performing multiplication using the first memory cells.
With respected to dependent claim 5, the prior art fails to tech or suggest the claimed limitations, namely, select transistors coupling the first memory cells to the common line, wherein the first voltages are applied to gates of the select transistors.
With respected to dependent claim 6, the prior art fails to tech or suggest the claimed limitations, namely, the first voltages are applied as a series of input bits in a plurality of time slices, and wherein each input bit has a different bit significance.
With respected to dependent claim 7, the prior art fails to tech or suggest the claimed limitations, namely, the common line is a digit line, the device further comprising: bitlines coupled to the first memory cells; select transistors coupling the bitlines to the digit line; and select lines configured to control the select transistors.
7. Claims 9-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 9: there is no teaching, suggestion, or motivation for combination in the prior art to “a memory cell array having memory cells programmable to store weights for performing multiplication, wherein the memory cells are organized in horizontal tiers of memory cells, and wherein the tiers are stacked above the semiconductor substrate; and a controller configured to: program first memory cells to store a multi-bit weight, wherein each first memory cell stores a bit having one of a plurality of significances” in an apparatus as claimed in the independent claim 9. Claims 10-17 are also allowed because of their dependency on claim 9; or
Per claim 18: there is no teaching, suggestion, or motivation for combination in the prior art to “a memory cell array having memory cells, wherein each memory cell is programmable to store a plurality of bits representing a number corresponding to a respective weight; sensing circuitry configured to measure a respective output current from each memory cell during programming” in a system as claimed in the independent claim 18. Claims 19-20 are also allowed because of their dependency on claim 18.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu et al (US. 10,665,313) discloses a detecting short circuit between word-line and source-line in memory device.
Hanzawa (US. 2023/0333816) discloses a signal processing device imaging device and a signal processing method.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights