Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 9 and 18.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 01/25/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 03/21/2024. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 05/02/2024. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 09/10/2024. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 09/17/2024. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 06/16/2025. The information disclosed therein was considered.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “In one approach” in page 1, line 3-4, which is implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 3 and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Micheloni et al (US Pat 6,144,589).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Micheloni et al in Figures 1-4 are directly discloses a device (shows a boosting circuit associated a row decoding circuit of a memory device, Figs. 1 and 4) comprising:
a memory cell array having memory cells (a matrix of memory cells 16, memory half-sector S1-1…S2-2), wherein each memory cell is programmable to store a bit having one of a plurality of significances, and wherein first memory cells are configured to store a first multi-bit weight (the matrix of memory cells 16 and memory half-sector S1-1…S2-2, use as a programming for store a bit);
voltage drivers (a boosting circuit A composed by two sub-circuits A1 and A2 and Boosting circuit 72 composed by voltage boosting circuit 70) configured to apply voltages to the memory cells, wherein the voltages include first voltages representing a first input to be multiplied by the first multi-bit weight (the boosting circuit A composed by two sub-circuits A1 and A2 that capable of generating on respective node 7 and 8 as a boosted voltage of value higher than a voltage supply Vcc, column 3, lines 26-30);
a common line (a generate signal 5) coupled to each of the first memory cells (the matrix of memory cell 16), wherein the common line is configured to sum output currents from the first memory cells, and wherein the respective output current from each first memory cell corresponds to a significance of the respective bit stored by the first memory cell (the internal address signals 3 supply the row decoder circuit 4 , which generate siganls 5 that through respective driving stage 400 allow for selecting each one of the rows of the memory cell matrix 16, column 3, lines 22-26); and
at least one digitizer (a read start signal 6 and an internal address signal 3) configured to provide at least one result based on summing the output currents (the read start signal 6 and an internal address signal 3, which is activated upon transition of state of the external address signal 1, see at least in Figures 1 and 4, column 3, lines 15-37 and column 7, lines 24-55 and the related disclosures).
Regarding dependent claim 3, Micheloni et al in Figures 1-4 are directly discloses a device (shows a boosting circuit associated a row decoding circuit of a memory device, Figs. 1 and 4) wherein each of the memory cells (the matrix of memory cells 16) is a Nand flash memory cell (memory cells 16 is the nonvolatile memory such as Flash EEPROM, column 1, lines 6-7), the device further comprising a common wordline coupled to a gate of each first memory cell (memory cells 16 is flash memory such as the wordline coupled to the gate of memory cells).
Regarding dependent claim 8, Micheloni et al in Figures 1-4 are directly discloses a device (shows a boosting circuit associated a row decoding circuit of a memory device, Figs. 1 and 4) wherein the memory cells (the matrix of memory cells 16) of the array are resistive random access memory cells (the nonvolatile memory cells 16 such as resistive random access memory cells).
Allowable Subject Matter
6. Claims 2 and 4-7, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the device, wherein the magnitudes of the output currents from the first memory cells are configured to differ from one another by a power of two based on the significance of the respective bit (claim 2), the device, wherein a fixed bias is applied to the common wordline when performing multiplication using the first memory cells (claim 4), the device, further comprising select transistors coupling the first memory cells to the common line, wherein the first voltages are applied to gates of the select transistors (claim 5), the device, wherein the first voltages are applied as a series of input bits in a plurality of time slices, and wherein each input bit has a different bit significance (claim 6) and the device, wherein the common line is a digit line, the device further comprising: bitlines coupled to the first memory cells; select transistors coupling the bitlines to the digit line; and select lines configured to control the select transistors (claim 7).
7. Claims 9-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 9: there is no teaching, suggestion, or motivation for combination in the prior art to “a controller configured to: program first memory cells to store a multi-bit weight, wherein each first memory cell stores a bit having one of a plurality of significances; provide at least one input signal to the first memory cells, wherein the input signal is to be multiplied by the multi-bit weight, the first memory cells provide output currents based on the input signal, and the respective output current from each first memory cell corresponds to the significance of the bit stored by the respective first memory cell; and determine a result based on summing the output currents from the first memory cells” in an apparatus as claimed in the independent claim 9. Claims 10-17 are also allowed because of their dependency on claim 9; or
Per claim 18: there is no teaching, suggestion, or motivation for combination in the prior art to “sensing circuitry configured to measure a respective output current from each memory cell during programming, wherein each memory cell is programmed so that the respective output current corresponds to the number represented by the plurality of bits stored by the respective memory cell and voltage drivers configured to apply voltages to the memory cells, wherein the voltages represent inputs to be multiplied by the weights stored in the memory cells; and at least one line coupled to each of the memory cells, wherein the line is configured to sum output currents from each of the memory cells to provide an accumulation result” in a system as claimed in the independent claim 18. Claims 19-20 are also allowed because of their dependency on claim 18.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu et al (US. 10,665,313) discloses detecting short circuit between word line and source line in memory device.
Hanzawa (US. 2023/0333816) discloses signal processing device imaging device and signal processing method.
Seo et al (US. 11,526,739) discloses nonvolatile memory device performing a multiplication and accumulation operation.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights