Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Election/Restriction
During a telephone conversation with Justin Flanagan (Reg. No. 62826) on 01/22/2026 a provisional election was made without traverse to prosecute the invention of elected group I corresponding to claims 1-23. Affirmation of this election must be made by applicant in replying to this Office action. Claims 24-29 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/29/2025 and 03/25/2024 are being considered by the examiner.
Priority
Acknowledgement is made of applicant’s claim for priority dated 01/25/2024.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Akselrod (US 11846865 B1) and further in view of Akselrod (US 20190301025 A1), hereinafter Akselrod025.
Regarding claim 1, Akselrod teaches in Fig. 1A: an optical metasurface (“optical metasurface 100”; col 6 line 45), comprising:
an optical reflector layer (“reflective layer 110”; col 6 line 44) that includes a plurality of metallic reflector patches (“reflector patches 115”; col 7 line 15);
resonator layer (“resonator layer 120”; col 6 line 44) with an array of optical resonators (“pillars 125 in each row of pillars form optical resonators”; col 6 lines 58-59), wherein each optical resonator is formed by two vertically extending metallic optical elements (125) positioned adjacent to one another to form a gap therebetween (“the resonator layer 120 includes a two-dimensional array of metallic optical pillars 125 arranged in parallel rows”; col 6 lines 46-48, see Fig. 1A, “The gaps between adjacent pillars 125 in each row of pillars form optical resonators”; col 6 lines 58-59);
an interconnect layer (“dielectric via layer 150 may be positioned between the reflective layer 110 and the resonator layer 120”; col 7 lines 30-31) positioned between the optical reflector layer (110) and the resonator layer (120), wherein the interconnect layer (150) comprises a plurality of metallic vias (“conductor vias 155”; col 7 line 46), wherein each metallic via (155) electrically connects to one of the metallic optical elements of the resonator layer (120) (“Each conductor via 155 of the dielectric via layer 150 … connects one pillar 125 to one of the underlying reflector patches 115”; col 7 lines 45-49).
Akselrod fails to explicitly teach: a first conductive barrier deposited during a first single-damascene process used to form the metallic vias of the interconnect layer; and a second conductive barrier deposited during a second single-damascene process used to form the metallic optical elements of the resonator layer, wherein the second conductive barrier physically separates the metallic vias and the metallic optical elements.
However, in a related invention in the field of fabricating a metallic optical metasurface, Akselrod025 teaches in Fig. 7A-B: a first conductive barrier deposited during a first single-damascene process used to form the metallic vias of the interconnect layer (“the damascene process may be a dual-damascene process, which may involve making the electrical via connections between elements in copper pillars 622 and copper patches 614”; [0092], “The damascene process may be a single damascene process, or a dual damascene process”; [0078]); and
a second conductive barrier deposited during a second single-damascene process used to form the metallic optical elements of the resonator layer (“copper pillars 718 are formed with a conducting barrier layer 720”; [0106], Fig. 7A, “FIG. 7A shows a cross-sectional view of forming patterned copper pillars and copper patches using a damascene process in according to embodiments of the disclosure”; [0106], “The damascene process may be a single damascene process, or a dual damascene process”; [0078]), wherein the second conductive barrier physically separates the metallic vias and the metallic optical elements (see Fig. 7B which shows that barrier layer 720 separates metallic elements 718 and the vias 706, 704).
Furthermore, Akselrod025 teaches this configuration such that “In the damascene process, a conducting barrier layer completely surrounds all copper interconnections. The conducting barrier layer prevents copper from diffusion into any surrounding materials, which would degrade the properties of the surrounding materials. For example, silicon can form deep-level traps when doped with copper. The conducting barrier layer can reduce copper diffusivity sufficiently, thus chemically isolates the copper from the dielectric insulator (e.g. silicon oxide) while still having high electrical conductivity in order to maintain a good electronic contact” (Akselrod025, [0081]). Additionally, Akselrod025 specifies that “the dual-damascene process and the single damascene process are largely identical. It would be known to those skilled in the art that anything possible in the single-damascene process is likely possible in the dual-damascene process” (Akselrod025, [0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Akselrod to incorporate the teachings of Akselrod025 to provide a device in which a first conductive barrier deposited during a first single-damascene process used to form the metallic vias of the interconnect layer; and a second conductive barrier deposited during a second single-damascene process used to form the metallic optical elements of the resonator layer, wherein the second conductive barrier physically separates the metallic vias and the metallic optical elements, for the purpose of having high electrical conductivity in order to maintain a good electronic contact (Akselrod025, [0081]).
Regarding claim 2, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod further teaches in Fig. 1A: each metallic via (155) is formed as a copper via, and wherein each metallic optical element (125) comprises a copper optical element (“metal pillars (e.g., copper)”; col 11 line 44).
However, Akselrod fails to explicitly teach that the vias are formed as copper vias.
However, in a related invention in the field of fabricating a metallic optical metasurface, Akselrod025 teaches in Fig. 7A-B: each metallic via is formed as a copper via (“The vias and the trenches are formed using the dual-damascene process. The copper is deposited in the vias and trenches simultaneously in a single deposition operation”; [0097]), and wherein each metallic optical element comprises a copper optical element (“patterned copper pillars and copper patches using a damascene process”; [0106]).
Furthermore, Akselrod025 teaches this configuration such that “the metal pillars reduce the coupling between the hologram elements of the metallic holographic metasurfaces. The metal pillars do not allow the optical field to be penetrated in from the electrically-tunable material, such that the optical field is substantially confined within the electrically-tunable material. As a result, the metal pillars isolate the hologram elements from each other in the array and reduce the optical coupling between the hologram elements” (Akselrod025, [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Akselrod to incorporate the teachings of Akselrod025 to provide a device in which the vias are formed as copper vias, for the purpose of substantially confining the optical field within the electrically-tunable material (Akselrod025, [0042]).
Regarding claim 3, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod further teaches in Fig. 1A: each metallic reflector patch (115) is formed as a copper reflector patch (“metal walls of the reflector patches 615 and 616”; col 11 lines 60-61).
However, Akselrod fails to explicitly teach that each metallic reflector patch is formed as a copper reflector patch.
However, in a related invention in the field of fabricating a metallic optical metasurface, Akselrod025 teaches in Fig. 7A-B: each metallic reflector patch is formed as a copper reflector patch (“patterned copper pillars and copper patches using a damascene process”; [0106], “copper patches 704”; [0106]).
Furthermore, Akselrod025 teaches this configuration such that “The method includes fabricating the partial backplane structure including copper patches. The method also includes forming patterned copper pillars with a dielectric barrier layer (e.g. nitride layer). The method replaces a conducting barrier layer (e.g. Ta and/or Ta nitride) commonly used in a conventional damascene process with a dielectric barrier layer for the copper holographic metasurfaces. The method also includes recoating the copper pillars with a dielectric coating layer (e.g. nitride layer) to prevent copper from migrating into the dielectric insulator layer (e.g. silicon oxide)” (Akselrod025, [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Akselrod to incorporate the teachings of Akselrod025 to provide a device in which each metallic reflector patch is formed as a copper reflector patch, for the purpose of preventing copper from migrating into the dielectric insulator layer (Akselrod025, [0083]).
Regarding claim 4, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod fails to teach: the first conductive barrier layer comprises one or more of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN), and wherein the second conductive barrier layer comprises one or more of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).
However, in a related invention in the field of fabricating a metallic optical metasurface, Akselrod025 teaches in Fig. 7A-B: the first conductive barrier layer comprises one or more of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN), and wherein the second conductive barrier layer comprises one or more of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN) (“The present disclosure also provides methods for adding a conductive barrier layer including Ta and/or TaN to the copper”; [0047]).
Furthermore, Akselrod025 teaches this configuration such that “The presence of Ta and TaN would affect the optical performance of the metallic optical metasurface, but does not affect the electrical performances of the circuits” (Akselrod025, [0047]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Akselrod to incorporate the teachings of Akselrod025 to provide a device in which the first barrier comprises specific materials, for the purpose of selecting a material that will not inhibit the electrical performance of the circuits (Akselrod025, [0047]).
Regarding claim 5, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod fails to teach: each metallic via connects multiple metallic optical elements to a single metallic optical reflector patch, via the first and second conductive barriers.
However, in a related invention in the field of fabricating a metallic optical metasurface, Akselrod025 teaches in Fig. 6A-B and 7A-B: each metallic via (“electrical via connections between elements in copper pillars 622 and copper patches 614”; [0092]) connects multiple metallic optical elements to a single metallic optical reflector patch (622), via the first and second conductive barriers (“copper pillars 718 are formed with a conducting barrier layer 720”; [0106], “conducting barrier 706”; [0106]).
Furthermore, Akselrod025 teaches this configuration such that “The method includes fabricating the partial backplane structure including copper patches. The method also includes forming patterned copper pillars with a dielectric barrier layer (e.g. nitride layer). The method replaces a conducting barrier layer (e.g. Ta and/or Ta nitride) commonly used in a conventional damascene process with a dielectric barrier layer for the copper holographic metasurfaces. The method also includes recoating the copper pillars with a dielectric coating layer (e.g. nitride layer) to prevent copper from migrating into the dielectric insulator layer (e.g. silicon oxide)” (Akselrod025, [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Akselrod to incorporate the teachings of Akselrod025 to provide a device in which each metallic via connects multiple metallic optical elements to a single metallic optical reflector patch, via the first and second conductive barriers, for the purpose of prevent copper from migrating into the dielectric insulator layer (Akselrod025, [0083]).
Regarding claim 6, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod further teaches in Fig. 1A: the optical reflector layer (110) comprises a two-dimensional array of reflector patches (“reflective layer 110 includes a two-dimensional array of elongated rectangular reflector patches 115 extending lengthwise along parallel rows”; col 7 lines 10-14).
Regarding claim 7, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod further teaches in Fig. 1A: the array of optical resonators of the resonator layer (120) comprises a two-dimensional array of optical resonators (“pillars 125 in each row of pillars form optical resonators”; col 6 lines 58-59, see Fig. 1A).
Regarding claim 8, Akselrod and Akselrod025 teach the metasurface of claim 7. Akselrod further teaches in Fig. 1A: the two vertically extending metallic optical elements (125) of each optical resonator in the two-dimensional array of optical resonators (“the resonator layer 120 includes a two-dimensional array of metallic optical pillars 125 arranged in parallel rows”; col 6 lines 46-48, see Fig. 1A) comprises a rectangular prism pillar (see the shape of 125 as displayed by Fig. 1A).
Regarding claim 9, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod further teaches in Fig. 1A: the array of optical resonators of the resonator layer (120) comprises a one-dimensional array of optical resonators (“Gaps between row-adjacent pillars form optical resonators, such that each row of pillars includes a plurality of optical resonator gaps or cavities”; col 4 lines 12-14, “a single row of optical resonators is formed by the metallic optical pillars 425 in the resonator layer 420”; col 9 lines 27-29).
Regarding claim 11, Akselrod and Akselrod025 teach the metasurface of claim 1. Akselrod further teaches in Fig. 1A: the resonator layer (120) further comprises a tunable dielectric material that has a tunable refractive index positioned within the gap between the adjacent metallic optical elements of each respective optical resonator (“A tunable dielectric material may be deposited within the resonator layer to fill the space between the pillars 125 in all direction, such that tunable dielectric material is positioned within the optical resonators formed by the gaps between row-adjacent pillars 125”; col 6 lines 49-64), and wherein the tunable dielectric material comprises one or more of: liquid crystal, an electro-optic polymer, electro-optical crystal, and chalcogenide glass (“Examples of suitable tunable dielectric materials that have tunable refractive indices include liquid crystals, electro-optic polymer, electro-optic crystals, chalcogenide glasses, and/or various semiconductor materials.”; col 6 lines 64-6).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Akselrod (US 11846865 B1) and further in view of Akselrod (US 20190301025 A1), hereinafter Akselrod025, as in claim 9, and further in view of Akselrod (US 20190285798 A1), hereinafter Akselrod798.
Regarding claim 10, Akselrod and Akselrod025 teach the metasurface of claim 9. Akselrod fails to teach: the two vertically extending metallic optical elements of each optical resonator in the one-dimensional array of optical resonators comprises an elongated rectangular rail.
However, in a related invention in the field metasurfaces for optical beam steering, Akselrod798 teaches in Fig. 2B and 3A: the two vertically extending metallic optical elements (“first and second metal rails 240 and 242”; [0093], Fig. 2B) of each optical resonator (“plasmonic resonant waveguide 250”; [0093], Fig. 2B) in the one-dimensional array of optical resonators (“optical surface scattering antenna device 300”; [0093], Fig. 3A) comprises an elongated rectangular rail (“optical surface scattering antenna device 300 with a plurality of elongated, plasmonic metal rails 350-364 forming channels within which an electrically-adjustable dielectric is disposed”; [0096], Fig. 3A).
Furthermore, Akselrod798 teaches this configuration such that “the elongated metal rails may be spaced by a channel width corresponding to the fundamental harmonic mode of the frequencies within an optical operating bandwidth. In such an embodiment, one antinode can be realized in the channel width. The height of the metal rails may correspond to the fundamental harmonic mode as well, such that the number of magnetic field antinodes within the channel is 1 multiplied by the number of magnetic field antinodes that can be realized along the length of the channel” (Akselrod798, [0058]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Akselrod and Akselrod025 to incorporate the teachings of Akselrod798 to provide a device in which the two vertically extending metallic optical elements of each optical resonator in the one-dimensional array of optical resonators comprises an elongated rectangular rail, for the purpose of designing the magnetic field to correspond to the fundamental harmonic mode (Akselrod798, [0058]).
Allowable Subject Matter
Claims 12-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12, the closest prior art, Akselrod, teaches in Fig. 1A: an optical metasurface (“optical metasurface 100”; col 6 line 45), comprising:
an optical reflector layer (“reflective layer 110”; col 6 line 44) that includes a plurality of metallic reflector patches (“reflector patches 115”; col 7 line 15);
a resonator layer (“resonator layer 120”; col 6 line 44) with an array of optical resonators (“pillars 125 in each row of pillars form optical resonators”; col 6 lines 58-59), wherein each optical resonator is formed by two vertically extending metallic optical elements (125) positioned adjacent to one another to form a gap therebetween (“the resonator layer 120 includes a two-dimensional array of metallic optical pillars 125 arranged in parallel rows”; col 6 lines 46-48, see Fig. 1A, “The gaps between adjacent pillars 125 in each row of pillars form optical resonators”; col 6 lines 58-59);
an interconnect layer (“dielectric via layer 150 may be positioned between the reflective layer 110 and the resonator layer 120”; col 7 lines 30-31) positioned between the optical reflector layer (110) and the resonator layer (120).
Akselrod fails to explicitly teach: the interconnect layer including: a dielectric etch-stop layer to control an etch depth in the interconnect layer, a dielectric mid-layer to be etched as part of a first single-damascene process, and a dielectric cap layer resistant to being etched by an etching solution used to etch the resonator layer as part of a second single-damascene process; and a plurality of metallic vias formed within the interconnect layer as part of the first single-damascene process, wherein each metallic via electrically connects to one of the metallic optical elements of the resonator layer.
However, in a related publication in the field of fabricating a metallic optical metasurface, Zhang teaches: “We instead explore the use of Damascene lithography for HfO2 meta surface fabrication, a process that involves first patterning resist using electron beam (e-beam) lithography, con formally filling the open volumes of the resist template with HfO2 using ALD, back-etching the over-coated HfO2 layer using argon (Ar) ion milling, and finally removing the remaining resist with solvent to form the required high aspect-ratio nanopillars” (Zhang, page 2 col 1 para 1).
The literature suggests use of the Damascene process to be a viable method in the optical metasurface fabrication process, however the prior art of record cannot teach to the specific etching limitations of claim 12.
Based on the configuration of Akselrod it would be improper to modify the prior art to provide a device in which “a dielectric etch-stop layer to control an etch depth in the interconnect layer, a dielectric mid-layer to be etched as part of a first single-damascene process, and a dielectric cap layer resistant to being etched by an etching solution used to etch the resonator layer as part of a second single-damascene process; and a plurality of metallic vias formed within the interconnect layer as part of the first single-damascene process, wherein each metallic via electrically connects to one of the metallic optical elements of the resonator layer.” Therefore, the combination of features is considered to be allowable.
Claims 13-23 would be allowable for its dependence on claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20230326944 A1: damascene technique in a semiconductor manufacturing process
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/RUBY L KAUFFMAN/Examiner, Art Unit 2872
/THOMAS K PHAM/Supervisory Patent Examiner, Art Unit 2872