DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220336742) in view of Choi et al. (US 20070090443).
Regarding claim 1, Lee discloses that a semiconductor device comprising:
a substrate 101 with a logic device 111/307 (para. 0028 & 0062), the conductive line may be part of logic circuit or another type of circuit) formed on the substrate 101;
an interconnect structure 113 comprising a plurality of metal routing layers disposed above the substrate, the plurality of metal routing layers comprising an intermetal dielectric (IMD) layer 102 with metal routing 113/303 embedded in the IMD layer 102/302, wherein the metal routing in at least one of the plurality of metal routing layers 113 is connected to the logic device 111/ (para. 0028); and
a plurality of multiple-time programmable (MTP) non-volatile memory (NVM) cells 250 formed in the interconnect structure 113/303 between the plurality of metal routing layers 113/303, the plurality of memory cells 250 comprising a fin structure disposed in the IMD layer 102 (Fig. 14).
Lee fails to specify that a storage gate disposed around channel regions of the fin structure, and a control gate formed around side walls of the storage gate.
However, Choi suggests that a storage 77F gate disposed around channel regions 22 of the fin structure 53 , and a control gate 57 formed around side walls of the storage gate 77F.
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lee with a storage gate disposed around channel regions of the fin structure, and a control gate formed around side walls of the storage gate as taught by Choi in order to enhance variation of memory device by substituting equivalent devices and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Lee & Choi disclose that the plurality of memory cells comprise a NOR device (Lee, Fig. 14).
Reclaim 3, Lee & Choi disclose that a first source/drain region of the fin structure is connected to a source line, a second source/drain region of the fin structure is connected to a bit line, and the control gate is connected to a word line (Lee, Fig. 14).
Reclaim 4, Lee & Choi disclose that the plurality of memory cells comprise a NAND device (Lee, Fig. 14).
Reclaim 5, Lee & Choi disclose that a first source/drain region of the fin structure is connected to a source/drain region of a first series-connected transistor, a second source/drain region of the fin structure is connected to a source/drain region of a second series-connected transistor, and the control gate is connected to a word line (Lee, Fig. 14).
Reclaim 6, Lee & Choi disclose that the fin structure is formed from Indium gallium zinc oxide (IGZO) (para. 0045).
Reclaim 7, Lee & Choi disclose that the storage gate is formed from Silicon nitride (SiN) and the control gate is formed from Titanium nitride (TiN) (Choi, para. 0045).
Reclaim 8, Lee & Choi disclose that a high-K dielectric formed between the storage gate and the fin structure (para. 0039).
Regarding claim 9, Lee & Choi disclose that a method comprising:
providing a substrate 101 with a logic device 111/307 formed on the substrate 101 and an interconnect structure 113/303 comprising a plurality of metal routing layers disposed above the logic device 111/307 and substrate 101, the plurality of metal routing layers 113/303 comprising an intermetal dielectric (IMD) layer 102/302 with metal routing embedded in the IMD layer, 102/302 wherein the metal routing 113/303 in at least one of the plurality of metal routing layers is connected to the logic device 111/307, the plurality of metal routing layers including an upper metal routing layer with metal lines, vias 307/303, and a planarized oxide layer 302 (para. 0025);
forming a fin structure 53 (Choi, Fig. ) over the oxide layer 102 in the upper metal routing layer 303 from IGZO (para. 0045);
forming a high-K dielectric layer over the oxide layer and the fin structure (Lee in view of Choi, Fig. 19);
forming a storage gate 77F over channel regions of the fin structure 53;
forming a control gate 87 on a first side and a second side of the storage gate (Fig. 19);
and connecting at least one of the control gate and a source/drain regions of the fin structure to the logic device using VIAs and metal lines (Lee in view of Choi).
Reclaim 10, Lee & Choi disclose that forming the fin structure over the oxide layer in the upper metal routing layer from IGZO comprises depositing an IGZO layer by atomic layer deposition (ALD) or physical vapor deposition (PVD) and forming the deposited IGZO layer into a fin structure by patterning and etching techniques (Lee, para. 0045).
Reclaim 11, Lee & Choi disclose that forming the high-K dielectric layer over the oxide layer and the fin structure comprises depositing the high-K dielectric layer by atomic layer deposition (ALD) and wherein the high-K dielectric layer comprises Hafnium oxide (HfO2) (Lee, para. 0045).
Reclaim 12 , Lee & Choi disclose that forming the storage gate comprises forming a nitride storage gate from Silicon nitride (SiN) by chemical vapor deposition (CVD) or physical vapor deposition (PVD) (Lee, para. 0045).
Reclaim 13 , Lee & Choi disclose that forming the control gate comprises depositing a control gate material layer from Titanium nitride (TiN) or Tantalum nitride (TaN)) over and around the storage gate and planarizing the control gate material layer using CMP to separate a first control gate from a second control gate (Lee in view of Choi).
Reclaim 14 , Lee & Choi disclose that connecting a first source/drain region of the fin structure to a source line, a second source/drain region of the fin structure to a bit line, and the control gate to a word line (Lee in view of Choi).
Reclaim 15 , Lee & Choi disclose that connecting a first source/drain region of the fin structure to a source/drain region of a first series-connected transistor, a second source/drain region of the fin structure to a source/drain region of a second series-connected transistor, and the control gate to a word line (Lee in view of Choi).
Regarding claim 16, Lee & Choi disclose that a memory device comprising:
a logic device 111;
an interconnect structure 113/303 comprising a plurality of metal routing layers, the plurality of metal routing layers comprising an intermetal dielectric (IMD) layer 102/302 with metal routing 113/303 embedded in the IMD layer 102/302, wherein the metal routing in at least one of the plurality of metal routing layers is connected to the logic device; and
a multiple-time programmable (MTP) non-volatile memory (NVM) cell 250 in the interconnect structure between the plurality of metal routing layers, the memory cell comprising an IGZO (Indium gallium zinc oxide) (para. 0045, Lee) fin in the IMD layer 250, a storage gate 87 disposed around channel regions 53 of the IGZO fin in the IMD layer, and a control gate 87 formed around side walls of the storage gate in the IMD layer (Lee in view of Choi, Fig. 19).
Reclaim 17, Lee & Choi disclose that the memory cell is connected to a plurality of other memory cells to form a NOR device (Lee in view of Choi, Fig. 14 & 19, para. 0045).
Reclaim 18, Lee & Choi disclose that the memory cell is connected to a plurality of other memory cells to form a NAND device (Lee in view of Choi, Fig. 14 & 19, para. 0045).
Reclaim 19, Lee & Choi disclose that a high-K dielectric formed between the storage gate and the IGZO fin (Lee in view of Choi, Fig. 14 & 19, para. 0045).
Reclaim 20, Lee & Choi disclose that the logic device comprises a planar FET, FinFET, or gate all around (GAA) FET device (Lee in view of Choi, Fig. 14 & 19, para. 0045).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SU C KIM/ Primary Examiner, Art Unit 2899
