DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 12, 19 and 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Briesen et al. (US 6,603,647), hereinafter Briesen.
Regarding claim 1, Briesen discloses (see figures 1-9) a phase power supply path switching circuit (figure 1), receiving three phase power supplies from a power supply end (figure 1, part three phase power supplies connected at input of 12) (column 6; lines 52-54; The input phases U, V and W are linked to an LC filter 10, whose input side is connected to a network, which is not illustrated in any more detail), wherein the phase power supply path switching circuit (figure 1) comprises: three phase input ends (figure 1, part three phase input ends at U-W), comprising a first phase input end (figure 1, part U), a second phase input end (figure 1, part V), and a third phase input end (figure 1, part W), respectively receiving the three phase power supplies from the power supply end (figure 1, part three phase power supplies connected at input of 12); three phase output ends (figure 1, part three phase output ends at X-Z), comprising a first phase output end (figure 1, part X), a second phase output end (figure 1, part Y), and a third phase output end (figure 1, part Z); a matrix switch unit (figure 1, part matrix switch unit 2) (column 6; lines 43-47; This three-phase matrix converter 2 has nine bidirectional power switches 4, which are arranged in a 3.times.3 switch matrix 6), comprising a plurality of bidirectional switches (figures 1 and 3, parts 4), each of the plurality of bidirectional switches (figures 1 and 3, parts 4) is coupled between one of the three phase input ends (figure 1, part three phase input ends at U-W) and one of the three phase output ends (figure 1, part three phase output ends at X-Z), wherein the first phase input end (figure 1, part U) and the first phase output end (figure 1, part X) are coupled through a first bidirectional switch (figure 1, part first bidirectional switch 4 between U-X) in the plurality of bidirectional switches (figures 1 and 3, parts 4) to form a first phase line (figure 1, part first phase line U-4-X), and the second phase input end (figure 1, part V) and the second phase output end (figure 1, part Y) are coupled through a second bidirectional switch (figure 1, part second bidirectional switch 4 between V-Y) in the plurality of bidirectional switches (figures 1 and 3, parts 4) to form a second phase line (figure 1, part second phase line V-4-Y) (column 6; lines 47-50; The arrangement of the nine bidirectional power switches 4 in a 3.times.3 switch matrix 6 allows each output phase X, Y, Z to be connected to any desired input phase U, V, W); a detection unit (figure 8, part detection unit that input Uuv-Uwu to 22/24) (column 12; lines 16-18; The measured phase-to-phase voltages UUV, UVW and UWU of the matrix converter 2 are each applied to the devices 22 and 24), configured to detect the first phase line (figure 1, part first phase line U-4-X), the second phase line (figure 1, part second phase line V-4-Y), and a third phase line (figure 1, part third phase line W-4-Z), wherein the third phase line (figure 1, part third phase line W-4-Z) is coupled between the third phase input end (figure 1, part W) and the third phase output end (figure 1, part Z); and a control unit (figure 8, part control unit generated by 18-30), coupled to the detection unit (figure 8, part detection unit that input Uuv-Uwu to 22/24) and the matrix switch unit (figures 1 and 8, part matrix switch unit 2; through control Sx), and configured to, after receiving a switching signal (figure 8, part control unit generated by 18-30), in response to detecting (figure 8, part detection unit that input Uuv-Uwu to 22/24) that a first line voltage (figures 4 and 8, part Uuv; difference between Uu and Uv) between the first phase line (figure 1, part first phase line U-4-X) and the second phase line (figure 1, part second phase line V-4-Y) is zero (figures 4 and 8, part Uuv; difference between Uu and Uv = zero at region 6 [5π/2] and 12 [11π/6]) and a second line voltage (figures 4 and 8, part Uvw; difference between Uv and Uw) between the second phase line (figure 1, part second phase line V-4-Y) and the third phase line (figure 1, part third phase line W-4-Z) is within a polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]) (column 9; lines 45-67; This modified freewheeling method according to the invention is used only in the region of the zero crossings of the phase-to-phase voltages. Additional paths are switched on once again even in this modified method. If one phase-to-phase voltage is in the range+/-several volts, then two unidirectional power switches 4 are connected directly to this phase-to-phase voltage. One bidirectional power switch 4 is connected to the phase-to-phase voltages which are not in the range of +/-several volts. Freewheeling paths are proposed as a function of the nature of the zero-crossing region (positive/negative). If the zero-crossing region occurs at a negative line voltage, then the two positive paths of those bidirectional power switches 4 in the matrix converter 2 which are connected to these voltages are proposed. Otherwise, the zero-crossing region occurs at a positive line voltage, as a result of which the negative paths of the bidirectional power switches 4 that are involved are proposed), perform the following steps in sequence:(a) turning off first conduction directions of the first bidirectional switch (figures 1 and 7, part turning off S1P of bidirectional switch 4 between U-X) and the second bidirectional switch (figures 1 and 7, part turning off S2P of bidirectional switch 4 between V-Y), wherein the first conduction direction is opposite to a current direction of the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]); (b) turning on second conduction directions of a third bidirectional switch (figures 1 and 7, part turning ON S2N of bidirectional switch 4 between V-X) and a fourth bidirectional switch in the polarity of bidirectional switches (figures 1 and 7, part turning ON S1N of bidirectional switch 4 between U-Y), wherein the second conduction direction is the same as the current direction of the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]), the third bidirectional switch (figures 1 and 7, part third bidirectional switch 4 between V-X) is coupled between the second phase input end (figure 1, part V) and the first phase output end (figure 1, part X), and the fourth bidirectional switch (figures 1 and 7, part fourth bidirectional switch 4 between U-Y) is coupled between the first phase input end (figure 1, part U) and the second phase output end (figure 1, part Y);(c) turning off second conduction directions of the first bidirectional switch (figures 1 and 7, part turning off S1N of bidirectional switch 4 between U-X) and the second bidirectional switch (figures 1 and 7, part turning off S2N of bidirectional switch 4 between V-Y); and (d) turning on first conduction directions of the third bidirectional switch (figures 1 and 7, part turning ON S2P of bidirectional switch 4 between V-X) and the fourth bidirectional switch (figures 1 and 7, part turning ON S1P of bidirectional switch 4 between U-Y) (column 11; lines 20-67; Regions are defined in which the network-side phase-to-phase voltages are at the zero crossing (modified freewheeling method), and those at which none of the phase-to-phase voltages is in the zero-crossing region (simple freewheeling method). A zero-crossing region occurs whenever one of the phase-to-phase voltages is in the range from -10V to +10V. The regions 2, 6, 10 in FIG. 4 are positive zero-crossing regions. The regions 4, 8 and 12 in this FIG. 4 are negative zero-crossing regions. If none of the phase-to-phase voltages are within these regions, then the matrix converter is in the "outside the zero crossings" mode. The corresponding regions are denoted by the numbers 1, 3, 5, 7, 9 and 11 in FIG. 4… As during a commutation process, care must be taken during such a state change to ensure that there is no interruption in the current path. The new semiconductor switch must be switched on before the old semiconductor switch is switched off. During the change between the methods, there must be an overlap between the two methods, in order that the freewheeling path is not interrupted in any circumstances. In order to allow the overlap, the modified freewheeling method is activated immediately on reaching a +/-10 V region. Those semiconductor switches which were previously active likewise still remain switched on for a predetermined time. Both methods are active during this time period, and one freewheeling path is always connected. Once the overlap time has elapsed, the simple freewheeling method can be deactivated. The modified freewheeling method is now fully functional. Based on the same principle, on leaving a +/-10 V region, the semiconductor switches for this region still remain active for an adjustable time, while the semiconductor switches for the area outside this region are activated immediately).
Regarding claim 2, Briesen discloses everything claimed as applied above (see claim 1). Further, Briesen discloses (see figures 1-9) the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]) is selected from a group comprising a positive half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a positive half cycle at region 6 [5π/2]) and a negative half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a negative of half cycle at 12 [11π/6]).
Regarding claim 3, Briesen discloses everything claimed as applied above (see claim 1). Further, Briesen discloses (see figures 1-9) each of the plurality of bidirectional switches (figures 1 and 3, parts 4) comprises a first switch (figure 3, parts S1P-S3P) and a second switch connected in series (figure 3, parts S1N-S3N), the first switch turns off the first conduction direction (figure 3, parts S1P-S3P; turn-off the first conduction direction) in a turn-off state (figure 3, parts S1P-S3P; turn off state), and the second switch turns off the second conduction direction (figure 3, parts S1N-S3N; turns off the second conduction direction) in a turn-off state (figure 3, parts S1N-S3N; turn off state) (column 1; lines 38-57).
Regarding claim 4, Briesen discloses everything claimed as applied above (see claim 3). Further, Briesen discloses (see figures 1-9) the first switch turns on the first conduction direction (figure 3, parts S1P-S3P; turn-on the first conduction direction) in a turn-on state (figure 3, parts S1P-S3P; turn-on state), and the second switch turns on the second conduction direction (figure 3, parts S1N-S3N; turns on the second conduction direction) in a turn-on state (figure 3, parts S1N-S3N; turn-on state).
Regarding claim 5, Briesen discloses everything claimed as applied above (see claim 3). Further, Briesen discloses (see figures 1-9) the first switch (figure 3, parts S1P-S3P) and the second switch (figure 3, parts S1N-S3N) are two power semiconductor switches connected in reverse series (figure 3, parts S1P-S3P and S1N-S3N) (column 1; lines 38-57; The bidirectional power switches in the matrix converter each have two back-to-back series-connected semiconductor switches).
Regarding claim 12, Briesen discloses everything claimed as applied above (see claim 4). Further, Briesen discloses (see figures 1-9) the first switch (figure 3, parts S1P-S3P) and the second switch (figure 3, parts S1N-S3N) are two power semiconductor switches connected in reverse series (figure 3, parts S1P-S3P and S1N-S3N) (column 1; lines 38-57; The bidirectional power switches in the matrix converter each have two back-to-back series-connected semiconductor switches).
Regarding claim 19, Briesen discloses everything claimed as applied above (see claim 1). Further, Briesen discloses (see figures 1-9) the detection unit (figure 8, part detection unit that input Uuv-Uwu to 22/24) is coupled to the three phase input ends (figure 1, part three phase input ends at U-W) (column 8; lines 30-32; determined from the measured phase-to-phase input voltages of the matrix converter).
Regarding claim 21, Briesen discloses everything claimed as applied above (see claim 1). Further, Briesen discloses (see figures 1-9) every three bidirectional switches (figures 1 and 3, parts every three of 4) form a switch group (figures 1 and 3, parts switch group of every three of 4), and the matrix switch unit (figure 1, part matrix switch unit 2) comprises three switch groups (figures 1 and 3, parts three switch groups of every three of 4), wherein two ends of each of the plurality of bidirectional switches are respectively a first end and a second end (figures 1 and 3, part left and right ends of each 4), the first ends of the plurality of bidirectional switches (figures 1 and 3, part left end of each 4) of each of the three switch groups (figures 1 and 3, parts three switch groups of every three of 4) are coupled to the three phase input ends in a one-to-one manner (figure 1, part three phase input ends at U-W), and the second ends of the plurality of bidirectional switches (figures 1 and 3, part right ends of each 4) of each of the three switch groups (figures 1 and 3, parts three switch groups of every three of 4) are together coupled to one of the three phase output ends (figure 1, part three phase output ends at X-Z), so that each of the three switch groups (figures 1 and 3, parts three switch groups of every three of 4) is coupled to the three phase output ends in a one-to-one manner (figure 1, part three phase output ends at X-Z), wherein the third phase line (figure 1, part third phase line W-4-Z) is formed by coupling of the third phase input end (figure 1, part W) to the third phase output end (figure 1, part Z) through a fifth bidirectional switch (figure 1, part fifth bidirectional switch 4 between W-Z) in the plurality of bidirectional switches (figures 1 and 3, parts 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 13-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Briesen et al. (US 6,603,647), hereinafter Briesen, in view of Blasko (US 10,320,306).
Regarding claim 6, Briesen discloses everything claimed as applied above (see claim 5). Further, Briesen discloses (see figures 1-9) the power semiconductor switch is a transistor (figure 3, parts S1P-S3P and S1N-S3N), the first switch (figure 3, parts S1P-S3P) and the second switch respectively (figure 3, parts S1N-S3N) and a corresponding phase input end (figures 1 and 3, parts U-W) and a corresponding phase output end (figures 1 and 3, parts X-Z), and the gate of the first switch (figure 3, parts S1P-S3P) and the gate of the second switch (figure 3, parts S1N-S3N) are coupled to the control unit (figure 8, part control unit generated by 18-30). However, Briesen does not expressly disclose a metal-oxide-semiconductor field-effect transistor, the first switch and the second switch respectively have a source, a gate, and a drain, the drain of the first switch is coupled to the drain of the second switch, the source of the first switch and the source of the second switch are respectively coupled to a corresponding phase input end and a corresponding phase output end.
Blasko teaches (see figures 1-5) the power semiconductor switch (figure 3B, parts 40) is a metal-oxide-semiconductor field-effect transistor (figure 3B, parts 40), the first switch (figure 3B, part 42) and the second switch (figure 3B, part 44) and respectively have a source, a gate, and a drain (figure 3B, parts 42 and 44; source, gate, and drain), the drain of the first switch (figure 3B, part 42; drain) is coupled to the drain of the second switch (figure 3B, part 44; drain), the source of the first switch (figure 3B, part 42; source) and the source of the second switch (figure 3B, part 44; source) are respectively coupled to a corresponding phase input end (figure 2, part phase input end at left side of 22) and a corresponding phase output end (figure 2, part phase output end at right side of 22), and the gate of the first switch (figure 3B, part 42; gate) and the gate of the second switch (figure 3B, part 44; gate) are coupled to the control unit (figure 2, part 26) (column 4; lines 22-35).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the mosfet transistors as taught by Blasko in the power semiconductor switch of Briesen and obtain the power semiconductor switch is a metal-oxide-semiconductor field-effect transistor, the first switch and the second switch respectively have a source, a gate, and a drain, the drain of the first switch is coupled to the drain of the second switch, the source of the first switch and the source of the second switch are respectively coupled to a corresponding phase input end and a corresponding phase output end, and the gate of the first switch and the gate of the second switch are coupled to the control unit, because it provides more efficient switching performance with conduction losses reduction (column 4; lines 22-35).
Regarding claim 7, Briesen and Blasko teach everything claimed as applied above (see claim 6). Further, Briesen discloses (see figures 1-9) the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]) is the positive half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a positive half cycle at region 6 [5π/2]), the left terminal of the first switch (figure 3, parts S1P-S3P; left terminal) is coupled to the corresponding phase input end (figures 1 and 3, parts U-W), and the right terminal of the second switch (figure 3, parts S1N-S3N; right terminal) is coupled to the corresponding phase output end (figures 1 and 3, parts X-Z). However, Briesen does not expressly disclose the source of the first switch is coupled to the corresponding phase input end, and the source of the second switch is coupled to the corresponding phase output end.
Blasko teaches (see figures 1-5) the source of the first switch (figure 3B, part 42; source) is coupled to the corresponding phase input end (figure 2, part phase input end at left side of 22), and the source of the second switch (figure 3B, part 44; source) is coupled to the corresponding phase output end (figure 2, part phase output end at right side of 22).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the mosfet transistors as taught by Blasko in the power semiconductor switch of Briesen and obtain the polarity half cycle is the positive half cycle, the source of the first switch is coupled to the corresponding phase input end, and the source of the second switch is coupled to the corresponding phase output end, because it provides more efficient switching performance with conduction losses reduction (column 4; lines 22-35).
Regarding claim 8, Briesen and Blasko teach everything claimed as applied above (see claim 6). Further, Briesen discloses (see figures 1-9) the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]) is the negative half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a negative of half cycle at 12 [11π/6]), the left terminal of the first switch (figure 3, parts S1P-S3P; left terminal) is coupled to the corresponding phase output end (figures 1 and 3, parts X-Z), and the right terminal of the second switch (figure 3, parts S1N-S3N; right terminal) is coupled to the corresponding phase input end (figures 1 and 3, parts U-W). However, Briesen does not expressly disclose the source of the first switch is coupled to the corresponding phase input end, and the source of the second switch is coupled to the corresponding phase output end.
Blasko teaches (see figures 1-5) the source of the first switch (figure 3B, part 42; source) is coupled to the corresponding phase output end (figure 2, part phase output end at right side of 22), and the source of the second switch (figure 3B, part 44; source) is coupled to the corresponding phase input end (figure 2, part phase input end at left side of 22).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the mosfet transistors as taught by Blasko in the power semiconductor switch of Briesen and obtain the polarity half cycle is the negative half cycle, the source of the first switch is coupled to the corresponding phase output end, and the source of the second switch is coupled to the corresponding phase input end, because it provides more efficient switching performance with conduction losses reduction (column 4; lines 22-35).
Regarding claim 13, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 14, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, claim 8 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, Briesen discloses everything claimed as applied above (see claim 1). Further, Briesen discloses (see figures 1-9) the detection unit (figure 8, part detection unit that input Uuv-Uwu to 22/24) (column 12; lines 16-18; The measured phase-to-phase voltages UUV, UVW and UWU of the matrix converter 2 are each applied to the devices 22 and 24). However, Briesen does not expressly disclose the detection unit is coupled to the three phase output ends.
Blasko teaches (see figures 1-5) the detection unit (figure 5, part 62) is coupled to the three phase output ends (figures 2 and 5, part three phase output ends at Vabc) (column 5; lines 37-41; The output voltage (vabc) of matrix converter 22 is sampled by magnitude block 62).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detection unit of Briesen with the detection unit features as taught by Blasko and obtain the detection unit is coupled to the three phase output ends, because it provides another efficient option for detecting the operation status of the system.
Claims 9-11 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Briesen et al. (US 6,603,647), hereinafter Briesen, in view of Inomata et al. (US 9,112,414), hereinafter Inomata.
Regarding claim 9, Briesen discloses everything claimed as applied above (see claim 5). Further, Briesen discloses (see figures 1-9) the power semiconductor switch is a transistor (figure 3, parts S1P-S3P and S1N-S3N), the first switch (figure 3, parts S1N-S3N) and the second switch respectively (figure 3, parts S1P-S3P) and a corresponding phase input end (figures 1 and 3, parts U-W) and a corresponding phase output end (figures 1 and 3, parts X-Z), and the gate of the first switch (figure 3, parts S1N-S3N) and the gate of the second switch (figure 3, parts S1P-S3P) are coupled to the control unit (figure 8, part control unit generated by 18-30). However, Briesen does not expressly disclose a metal-oxide-semiconductor field-effect transistor, the first switch and the second switch respectively have a source, a gate, and a drain, the source of the first switch is coupled to the source of the second switch, the drain of the first switch and the drain of the second switch are respectively coupled to a corresponding phase input end and a corresponding phase output end.
Inomata teaches (see figures 1-29) the power semiconductor switch (figure 2C, parts Sio and Soi) is a metal-oxide-semiconductor field-effect transistor switch (figure 2C, parts Sio and Soi [as mosfet]) (column 5; lines 43-61; the unidirectional switches Sio and Soi are a semiconductor switching element such as a metal-oxide-semiconductor field-effect transistor (MOSFET)), the first switch and the second switch respectively have a source, a gate, and a drain (figure 2C, parts Soi and Sio [as mosfet]; a source, a gate, and a drain), the source of the first switch (figure 2C, parts Soi [as mosfet]; source) is coupled to the source of the second switch (figure 2C, parts Sio [as mosfet]; source), the drain of the first switch (figure 2C, parts Soi [as mosfet]; drain) and the drain of the second switch (figure 2C, parts Sio [as mosfet]; drain) are respectively coupled to a corresponding phase input end (figure 2C, part phase input end at Vi) and a corresponding phase output end (figure 2C, part phase input end at Vo), and the gate of the first switch (figure 2C, parts Soi [as mosfet]; gate) and the gate of the second switch (figure 2C, parts Sio [as mosfet]; gate) are coupled to the control unit (figure 2, part 14).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the mosfet transistors features as taught by Inomata in the power semiconductor switch of Briesen and obtain the power semiconductor switch is a metal-oxide-semiconductor field-effect transistor, the first switch and the second switch respectively have a source, a gate, and a drain, the source of the first switch is coupled to the source of the second switch, the drain of the first switch and the drain of the second switch are respectively coupled to a corresponding phase input end and a corresponding phase output end, and the gate of the first switch and the gate of the second switch are coupled to the control unit, because it provides efficient switching control with fast switching speed.
Regarding claim 10, Briesen and Inomata teach everything claimed as applied above (see claim 9). Further, Briesen discloses (see figures 1-9) the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]) is the positive half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a positive half cycle at region 6 [5π/2]), the right terminal of the first switch (figure 3, parts S1N-S3N; right terminal) is coupled to the corresponding phase output end (figures 1 and 3, parts X-Z), and the left terminal of the second switch (figure 3, parts S1P-S3P; left terminal) is coupled to the corresponding phase input end (figures 1 and 3, parts U-W). However, Briesen does not expressly disclose the drain of the first switch is coupled to the corresponding phase output end, and the drain of the second switch is coupled to the corresponding phase input end.
Inomata teaches (see figures 1-29) the drain of the first switch (figure 2C, parts Soi [as mosfet]; drain) is coupled to the corresponding phase output end (figure 2C, part phase input end at Vo), and the drain of the second switch (figure 2C, parts Sio [as mosfet]; drain) is coupled to the corresponding phase input end (figure 2C, part phase input end at Vi).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the mosfet transistors features as taught by Inomata in the power semiconductor switch of Briesen and obtain the polarity half cycle is the positive half cycle, the drain of the first switch is coupled to the corresponding phase output end, and the drain of the second switch is coupled to the corresponding phase input end, because it provides efficient switching control with fast switching speed.
Regarding claim 11, Briesen and Inomata teach everything claimed as applied above (see claim 9). Further, Briesen discloses (see figures 1-9) the polarity half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a polarity of half cycle at region 6 [5π/2] and 12 [11π/6]) is the negative half cycle (figures 4 and 8, part Uvw; difference between Uv and Uw is within a negative of half cycle at 12 [11π/6]), the right terminal of the first switch (figure 3, parts S1N-S3N; right terminal) is coupled to the corresponding phase input end (figures 1 and 3, parts X-Z), and the left terminal of the second switch (figure 3, parts S1P-S3P; left terminal) is coupled to the corresponding phase output end (figures 1 and 3, parts U-W). However, Briesen does not expressly disclose the drain of the first switch is coupled to the corresponding phase input end, and the drain of the second switch is coupled to the corresponding phase output end.
Inomata teaches (see figures 1-29) the drain of the first switch (figure 2C, parts Soi [as mosfet]; drain) is coupled to the corresponding phase input end (figure 2C, part phase input end at Vo), and the drain of the second switch (figure 2C, parts Sio [as mosfet]; drain) is coupled to the corresponding phase output end (figure 2C, part phase output end at Vi).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the mosfet transistors features as taught by Inomata in the power semiconductor switch of Briesen and obtain the polarity half cycle is the negative half cycle, the drain of the first switch is coupled to the corresponding phase input end, and the drain of the second switch is coupled to the corresponding phase output end, because it provides efficient switching control with fast switching speed.
Regarding claim 16, claim 9 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 17, claim 10 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 18, claim 11 has the same limitations, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838