DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1 – 11, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable Zhou et al. (2024/0274052; hereinafter Zhou; claiming benefit of CN 202211021909.6 filed 24 August 2022) and Hu et al. (2025/0087142; hereinafter Hu; claiming benefit of CN 202211090325.4 filed 7 September 2022) in view of Son (2020/0160788; this combination of references hereinafter referred to as ZHS).
Regarding claim 1, Zhou discloses a light emitting display ([0047]; Figure 4) apparatus, comprising:
a light emitting display panel (Comprising 100) provided with a pixel (Comprising 2) including a pixel driving circuit (Figure 3) and a light emitting device (Comprising D); and
a gate driver (Figure 4: Comprising 9, 10) configured to supply gate signals [0059] to the pixel driving circuit (Comprising 2), wherein the pixel driving circuit comprises a switching transistor (Figure 3: Comprising M5) and a first light emitting transistor (Comprising M7), the first light emitting transistor (Comprising M7) is connected between an anode of the light emitting device (Comprising D) and a first node (Comprising N3), the switching transistor (Comprising M5) is connected between a data line (Comprising Data) provided in the light emitting display panel and the first node (Comprising N3), during the use of the light emitting display apparatus,
the gate driver is configured to turn on the first light emitting transistor (Comprising M7) M times per second (With EM1) and to turn on the switching transistor (Comprising M5) S times (With S3) and more than one time per second (Shared scanning signal operates at third frequency [0154] greater than a second frequency [0138] operating at 1Hz [0053]),
one second ([0035]: t2 = one second) is divided into a refresh period (Figure 18: S3 transmission during WF_L; [0153]) and an anode reset period (S6 transmission during HF; [0154]), and the switching transistor (Figure 3: Comprising M5) is configured to be turned on (By S3) at least once during the anode reset period (Figure 18: Overlap of S3, S6 during HF; [0154]: S3, S6 may be one in the same).
Zhou does not make an outright statement of the apparatus being provided wherein M is a natural number of 3 or more, and S is a natural number of 2 or more. However, please consider the following.
Figures 1 and 18 illustrate operation at a second frequency (f2) of 1Hz and resulting 1 second cycle (t2; [0035]). Waveforms driving respective ones of the pixel’s (Figure 3) equivalent switching (M5, receiving S3) and first light emitting (M7, receiving EM11) transistors are respectively illustrated to comprise the shown four pulses applied in a cycle comprising writing (WF_L) and holding (HF) periods. The application of (at least) said four pulses – turning on respective ones of the aforementioned transistors – in a 1 second cycle, is an indirect teaching of the claimed apparatus wherein M is a natural number of 3 or more, and S is a natural number of 2 or more.
It would be within the purview of Artisan before the filing date of the claimed invention that Zhou provides an indirect teaching of the apparatus wherein M is a natural number of 3 or more, and S is a natural number of 2 or more, as claimed, in view of the reasoning above.
Zhou does not explicitly disclose the apparatus wherein S times is smaller than M times.
In the same field of endeavor, Hu discloses a display [0002] whose pixel circuitry (Figure 20) may be operated (Figure 24) with a light emission control signal (Comprising EMIT) whose pulse number (e.g. at least 8) numbers greater than pulses of the scan control signal (Comprising SP2). This is among measures implemented to improve refresh frequency switching flexibility [0083].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein S times is smaller than M times, in view of the teaching of Hu, to improve refresh frequency switching flexibility.
Zhou in view of Hu does not explicitly disclose the apparatus wherein when the switching transistor is configured to be turned on during the anode reset period, a compensation voltage is supplied to the anode of the light emitting device through the data line, the switching transistor, and the first light emitting transistor.
In the same field of endeavor, Son discloses a display [0002] wherein when the switching transistor (Figure 8: Comprising T1) is configured to be turned (SCAN2 is high) on during the anode reset period ([0102]: Holding interval), a compensation voltage ([0117], [0147]: Vrst) is supplied to the anode of the light emitting device (Comprising EL) through the data line (Comprising DL), the switching transistor (Comprising T1), and the first light emitting transistor (Comprising T4). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein when the switching transistor is configured to be turned on during the anode reset period, a compensation voltage is supplied to the anode of the light emitting device through the data line, the switching transistor, and the first light emitting transistor, in view of the teaching of Son, to reduce the visibility of flicker.
Regarding claim 2, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein during the refresh period, a data voltage is supplied (Figure 18: S3 transmission during WF_L; [0153]) through the data line (Figure 3: Comprising Data) and the switching transistor (Comprising M5), and light is output from the light emitting device on the basis of the size of the data voltage [0127], and during the anode reset period, the first light emitting transistor is repeatedly turned on and off, and thus, light is output from the light emitting device (HF light emitting sub-period t4’ [0192] when implemented in circuitry of Figure 3, instead using bias voltage transmitted on data line according to timing of S3 [0154], illustrated in Figure 18 to overlap with pulse of EM3).
The relied upon embodiment of Zhou does not expressly state the apparatus being provided wherein the data voltage is supplied to the first node.
However, Son discloses a display [0002] wherein the data voltage (Figure 6: Comprising Vdata) is supplied to the first node (Comprising N3). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the data voltage is supplied to the first node, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 3, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein the switching transistor (Figure 3: Comprising M5) is configured to be turned on (By S3) once during the refresh period (e.g., Figure 18: Single S3 pulse during WF_L) and is turned on S-1 times during the anode reset period (Three S3 pulses during HF).
Regarding claim 4, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein the first light emitting transistor (Figure 3: Comprising M7) is configured to be turned on (By EM1) once during the refresh period (e.g., Figure 18: Single EM3 pulse during WF_L) and is turned on M-1 times during the anode reset period (Three EM3 pulses during HF).
Regarding claim 5, ZHS discloses the light emitting display apparatus of claim 1.
Zhou does not make an outright statement of the apparatus being provided wherein the anode reset period is longer than the refresh period.
Zhou does however, disclose (Figure 1) the equivalent refresh period (Comprising WF_L) and each individual anode reset period (Comprising HF) with a duration of 1/120 seconds, and a frame duration of 1 second when operating at 1Hz [0035]. The difference of the frame length (1 second) and the refresh period (1/120 seconds) may be relied upon to calculate the duration of the full reset period (119/120 seconds). 119/120 seconds is indeed longer than 1/120 seconds.
It would be within the purview of Artisan before the filing date of the claimed invention that Zhou provides an indirect teaching of the apparatus wherein the anode reset period is longer than the refresh period, as claimed, in view of the reasoning above.
Regarding claim 6, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein the compensation voltage different from the data voltage is supplied to the data line during the anode reset period ([0108]: V.sub.Data+V.sub.th during HF).
Regarding claim 7, ZHS discloses the light emitting display apparatus of claim 6. Zhou discloses the apparatus wherein the compensation voltage is set to a value which does not affect the luminance of light output from the light emitting device or a value that has a minimal effect on the luminance of light output from the light emitting device ([0042]: Bias reduces brightness difference between holding periods and low-frequency driving mode).
Regarding claim 8, ZHS discloses the light emitting display apparatus of claim 6. Zhou discloses the apparatus wherein the compensation voltage is supplied to the data line and supplied just before the light is output from the light emitting device (Initializing performed before emission [0151] by signal reused [0152] to conduct bias on data line [0154]).
The relied upon embodiment of Zhou does not expressly state the apparatus being provided wherein the compensation voltage is supplied to the first node.
However, Son discloses a display [0002] wherein the compensation voltage (Figure 8: Comprising Vrst) is supplied to the first node (Comprising N3). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the compensation voltage is supplied to the first node, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 9, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus (Figure 3) being provided wherein the switching transistor (Comprising M5) is configured to be turned on (By S3) in the anode reset period (Comprising HF).
The relied upon embodiment of Zhou does not expressly state the apparatus being provided wherein the switching transistor is turned on in a period where the first light emitting transistor is turned off.
However, Son discloses a display [0002] wherein the switching transistor (Figure 6: Comprising T5) is turned on (SCAN2 is high) in a period where the first light emitting transistor (Comprising T4) is turned off (EM1 is low). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the switching transistor is turned on in a period where the first light emitting transistor is turned off, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 10, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein the pixel driving circuit (Figure 3) further comprises a driving transistor (Comprising M0), a first voltage (Comprising PVDD) is supplied to a first electrode of the driving transistor (Comprising one of source, drain of M0), a second electrode of the driving transistor (Comprising other one of source, drain of M0) is connected to the first node (Comprising N3), and the driving transistor is configured to control the size of the current supplied to the light emitting device [0042].
Regarding claim 11, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus (Figure 3) wherein the first light emitting transistor (Comprising M7) is a P-type transistor [0166].
Zhou does not explicitly disclose the apparatus wherein the switching transistor is an N-type transistor.
However, Son discloses a display [0002] wherein the switching transistor (Figure 2: Comprising T1) is an N-type transistor [0059]. This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the switching transistor is an N-type transistor, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 19, ZHS discloses the light emitting display apparatus of claim 1.
Zhou does not explicitly disclose the apparatus wherein the number of times that the switching transistor is configured to be turned on during the anode reset period is less than the number of times that the first light emitting transistor is turned on during the anode reset period.
In the same field of endeavor, Hu discloses a display [0002] whose pixel circuitry (Figure 20) may be operated (Figure 24) with a light emission control signal (Comprising EMIT) whose pulse number (e.g. 3) during an ineffective frame (Comprising Ti2) numbers greater than pulses of the scan control signal (Comprising SP; e.g. 1) during said ineffective frame. This is among measures implemented to improve refresh frequency switching flexibility [0083].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the number of times that the switching transistor is configured to be turned on during the anode reset period is less than the number of times that the first light emitting transistor is turned on during the anode reset period, in view of the teaching of Hu, to improve refresh frequency switching flexibility.
Regarding claim 20, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein S is set based on the characteristics and power consumption of the light emitting display apparatus [0044].
ii. Claims 12 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over ZHS, as applied to claim 1 above, and further in view of Tanaka (2023/0034225; this combination of references hereinafter referred to as ZHST).
Regarding claim 12, ZHS discloses the light emitting display apparatus of claim 1. Zhou discloses the apparatus wherein the pixel driving circuit (Figure 3) further comprises: a driving transistor (Comprising M0) configured to control the size of the current supplied to the light emitting device [0042], a first voltage (Comprising PVDD) being supplied to a first electrode of the driving transistor (Comprising one of source, drain of M0), and a second electrode of the driving transistor (Comprising other one of source, drain of M0) being connected to the first node (Comprising N3); a second light emitting transistor (Comprising M8), a first electrode of the second light emitting transistor (Comprising one of source, drain of M8) being connected to a first voltage line to which the first voltage (Comprising PVDD) is supplied, and a second electrode of the second light emitting transistor (Comprising other one of source, drain of M8) being connected to the first electrode of the driving transistor (Comprising one of source, drain of M0); a scan transistor (Comprising M6) configured to be controlled by a first scan signal (Comprising S4), a first electrode of the scan transistor (Comprising one of source, drain of M6) being connected to a gate of the driving transistor (Comprising gate of M0), and a second electrode of the scan transistor (Comprising other one of source, drain of M6) being connected to the first electrode of the driving transistor (Comprising one of source, drain of M0); an initialization transistor (Comprising M4), a first electrode of the initialization transistor (Comprising one of source, drain of M4) being connected to the anode of the light emitting device (Comprising D), a second electrode of the initialization transistor (Comprising other one of source, drain of M4) being connected to an initialization line to which an initialization voltage (Comprising Ref2_2) being supplied, and a storage capacitor (Comprising Cst) connected to the gate of the driving transistor (Comprising M0).
The relied upon embodiment of Zhou does not expressly state the apparatus being provided wherein the storage capacitor is connected between the gate of the driving transistor and the anode of the light emitting device.
However, Son discloses a display [0002] wherein the storage capacitor (Figure 2) is connected between the gate of the driving transistor (Comprising T2) and the anode of the light emitting device (Comprising EL). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the storage capacitor is connected between the gate of the driving transistor and the anode of the light emitting device, in view of the teaching of Son, to further reduce the visibility of flicker.
ZHS does not explicitly disclose the apparatus wherein a gate of the initialization transistor being connected to a gate of the first light emitting transistor.
However, Tanaka discloses a display [0001] pixel (Figure 14) wherein a gate of the initialization transistor (Comprising M7) being connected to a gate of the first light emitting transistor (Comprising OL). This is among measures by which power consumption may be reduced in association with both scanning and driving side circuitry [0009].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein a gate of the initialization transistor being connected to a gate of the first light emitting transistor, in view of the teaching of Tanaka, to expand the benefit of reducing power consumption.
Regarding claim 13, ZHST discloses the light emitting display apparatus of claim 12. Zhou discloses the apparatus (Figure 3) wherein the switching transistor (Comprising M5) is configured to be turned on (By S3) in a period where the first light emitting transistor (Comprising M7) is turned on (By EM1) during the anode reset period (Comprising HF).
The relied upon embodiment of Zhou does not expressly state the apparatus being provided wherein the switching transistor is turned on in a period where the second light emitting transistor is turned off.
However, Son discloses a display [0002] wherein the switching transistor (Figure 6: Comprising T1) is turned on (SCAN2 is high) in a period where the second light emitting transistor (Comprising T5) is turned off (EM2 is low). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the switching transistor is turned on in a period where the second light emitting transistor is turned off, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 14, ZHST discloses the light emitting display apparatus of claim 12. Zhou discloses the apparatus (Figure 3) wherein the first light emitting transistor (Comprising M7) is a P-type transistor [0166].
Zhou does not explicitly disclose the apparatus wherein the initialization transistor is an N-type transistor.
However, Son discloses a display [0002] wherein the initialization transistor (Figure 2: Comprising T6) is an N-type transistor [0059]. This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the initialization transistor is an N-type transistor, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 15, ZHST discloses the light emitting display apparatus of claim 14. Zhou discloses the apparatus (Figure 3) wherein the first light emitting transistor (Comprising M7) and the second light emitting transistor (Comprising M8) are P-type thin film transistors [0166], and the scan transistor (Comprising M6) is an N-type thin film transistor [0166].
ZHT does not expressly state the apparatus being provided wherein the switching transistor, the driving transistor and the initialization transistor are N-type thin film transistors.
However, Son discloses a display [0002] wherein the switching transistor (Figure 2: Comprising T1), the driving transistor (Comprising T2) and the initialization transistor (Comprising T6) are N-type thin film transistors [0059]. This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the switching transistor, the driving transistor and the initialization transistor are N-type thin film transistors, in view of the teaching of Son, to further reduce the visibility of flicker.
Regarding claim 16, ZHST discloses the light emitting display apparatus of claim 12. Zhou discloses the apparatus (Figure 3) wherein the driving transistor (Comprising M0) and the scan transistor (Comprising M6) are oxide thin film transistors using an oxide semiconductor [0166], and the switching transistor (Comprising M5), the second light emitting transistor (Comprising M8), first light emitting transistor (Comprising M7) and the initialization transistor (Comprising M4) are low temperature polysilicon thin film transistors using a polycrystalline semiconductor [0166].
Regarding claim 17, ZHST discloses the light emitting display apparatus of claim 12. Zhou discloses the apparatus (Figure 3) wherein a first light emitting control signal (Comprising EM1) input to the gate of the first light emitting transistor (Comprising M7) and a second light emitting control signal (Comprising EM2) input to a gate of the second light emitting transistor (Comprising M8) are different signals (Figure 8: Note respectively illustrated waveforms for each).
Regarding claim 18, ZHST discloses the light emitting display apparatus of claim 12. Zhou discloses the apparatus (Figure 3) wherein the second light emitting transistor (Comprising M8) is configured to be turned on (By EM2) in the anode reset period (Figure 18: Comprising HF).
The relied upon embodiment of Zhou does not expressly state the apparatus being provided wherein the second light emitting transistor is turned on after the first light emitting transistor is turned on.
However, Son discloses a display [0002] wherein the second light emitting transistor (Figure 6: Comprising T5) is turned on (EM2 is high) after the first light emitting transistor (Comprising T4) is turned on (EM1 is high). This is among measures implemented to further reduce the visibility of flicker [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Zhou to be modified wherein the second light emitting transistor is turned on after the first light emitting transistor is turned on, in view of the teaching of Son, to further reduce the visibility of flicker.
Inquiries
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AARON MIDKIFF/
Patent Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 Timing diagram illustrates emitting control signal EM3, not elsewhere found in the drawings or text of the disclosure. In light of said timing diagram’s applicability to the circuit of Figure 3 [0025] whose emitting control signals (EM1, EM2) elsewhere share identical waveforms (Figures 8, 11) that may be a single signal reused [0176], the illustration of EM3 in Figure 18 is interpreted as said reused signal, applied in place of separate instances of EM1, EM2.
2 [0080]: Multiple scan control signals comprising same timing are represented by single waveform of SP.