DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This communication is in response to the amendment filed on 04/08/2026. The Examiner has acknowledged the amended Claims 1, 2, 4, 7-9, 11-13, 15, 18 and 20. Claim 16 has been cancelled, and new Claim 21 has been added. Claims 1-15 and 17-21 are pending and Claims 1-7, 11-15, 17-18 and 20-21 are rejected. Claims 8-10 and 19 are objected to (Please see the allowable subject matter).
Response to Arguments
3. Applicant's arguments (Remarks: Pages: 10-13) filed on 04/08/2026 have been
fully considered and they are persuasive. However, applicant’s arguments are now moot in view of a new reference applied (Jeong et al. US 2020/0051601 Al), and the applicant’s amendment necessitated a new ground of rejection.
4. The rejection of Claims 1-15 and 17-20 under 35 U.S.C 112 (b) has been withdrawn in view of the amended corrections. Claim 16 has been cancelled.
5. Applicant’s arguments (Remarks: Pages: 11-13) with respect to 35 U.S.C. 103 have been fully considered but they are persuasive. Applicant’s arguments are based on the applicant’s amendment and are now moot in view of a new reference applied (Jeong et al. US 2020/0051601 Al). Please see the 35 USC 103 rejection below.
Further, applicant’s arguments with respect to remaining independent claims and the dependent claims are based on applicant’s arguments with respect to Claim 1 and their dependency, and therefore, are now moot in view of a new reference applied (Jeong et al. US 2020/0051601 Al). Applicant's amendment necessitated a new ground of rejection.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. Claims 1-7, 11-15, 17-18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over YAGI et al. ( US 2022/0365730 Al, hereinafter Yagi) [As disclosed in IDS] in view of GOKITA (US 2019/0018797 Al, hereinafter Gokita) [As disclosed in IDS] and further in view of JEONG et al. (US 2020/0051601 Al, hereinafter Jeong).
Regarding Claim 1,
Yagi discloses a data access method comprising (Yagi: ¶ [0091] schematic diagrams for illustrating a second example of an access restricting method in a control device 100b according to the first embodiment. In an exemplary hardware configuration of control device 100b shown in FIG. 5, ¶¶ [0078, 0105]):
obtaining a data access request for M storage devices, M being an integer greater than or equal to 2 (Yagi: ¶ [0050] control device 100 includes a plurality of microcontroller units (MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively…, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, ¶ [0084] Safety core 1162 and standard core 1164 can each access the physical address of RAM 115 by accessing a virtual address assigned in conversion table 600, ¶¶ [0085, 0086], Fig. 5 –115, 125);
determining a target access mode for the M storage devices based on the data access request (Yagi: ¶ [0093] as a mode indicative of a state of processor 116, a privileged mode and a user
mode are provided for each of safety core 1162 and standard core 1164…, privileged
mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the
user mode is one example of a "second mode.", ¶¶ [0019, 0050, 0094-0095, 0099-0104]);
performing data access on the M storage devices based on access control signals matching the target access mode for the M storage devices (Yagi: ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set, ¶ [0098] when safety core 1162 accesses RAM 115 based on a prescribed instruction in application 1162p, safety core 1162 is able to access both safety storage area 1152 and standard storage area 1154 as shown in FIG. 6, whereas when standard core 1164 accesses RAM 115 based on the same prescribed instruction in application
1164p, standard core 1164 is able to access standard storage area 1154 but is restricted from accessing safety storage area 1152 as shown in FIG. 6, ¶¶ [0093, 0095, 0099]);
wherein: the target access mode is selected from a first access mode and a second access mode (Yagi: ¶ [0093] as a mode indicative of a state of processor 116, a privileged mode and a user mode are provided for each of safety core 1162 and standard core 1164…, privileged
mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the
user mode is one example of a "second mode.", ¶ [0090] permission or
prohibition of access to each address range corresponding to the physical address may be set for each of a safety core and a standard core, ¶¶ [0007, 0093]); and
access security and/or access speed generated when the data access is performed on the M storage devices in the first access mode is different from access security and/or access speed generated in the second access mode (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a
storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set. ¶¶ [0095-0100]); and
when the target access mode is the first access mode and the M storage devices include a first storage device and a second storage device (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0050] control device 100 includes a plurality of microcontroller units(MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively…, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, Fig. 5 –115, 125), an access control signal matching the first access mode for the first storage device and an access control signal matching the first access mode for the second storage device have different signal time sequences.
Yagi does not explicitly disclose:
access security and/or access speed generated when the data access is performed on the M storage devices in the first access mode is different from access security and/or access speed generated in the second access mode.
However, Gokita from the same field of endeavor as the claimed invention discloses an information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first memory is configured to store data and has a first access speed. The second memory is configured to store data and has a second
access speed different from the first access speed (Gokita: [Abstract]), The DRAM 12 is an example of a first memory that stores first data and is a volatile storage device that may store
data in a readable and writable manner…, The NAND flash memory 13 is an example of a
second memory that stores second data and is a nonvolatile storage device that may store data in a readable and writable manner (Gokita: ¶ [0076-0077]), and an access speed of the DRAM 12 is higher than that of the NAND flash memory 13 (Gokita: ¶[0078]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gokita in the teachings of Yagi. A person having ordinary skill in the art would have been motivated to do so because respective storage destinations of first data stored in the first memory and second data stored in the second memory from among the first memory and the second memory based on a first access probability and a first latency of the first data and a second access probability and a second latency of the second data (Gokita: ¶ [0018]), therefore, frequently accessed data can be stored in faster memory and rarely accessed data can be stored in slower memory improving the system performance.
The combination of Yagi and Gokita does not explicitly disclose:
when the target access mode is the first access mode and the M storage devices include a first storage device and a second storage device, an access control signal matching the first access mode for the first storage device and an access control signal matching the first access mode for the second storage device have different signal time sequences.
However, Jeong from the same field of endeavor as the claimed invention discloses that the first storage device 2200 may determine the access mode of the second storage device 2300 with reference to the command CMD (Jeong: ¶ [0092]), the first storage device 2200 may determine whether a mode to access the second storage device 2300 is a high-speed mode. If the mode to access the second storage device 2300 is the high-speed mode (i.e., Yes) (Jeong: ¶ [0094]), the first storage device 2200 may bypass the reference clock RCK_l provided by the operation processor device 2100 to the second storage device 2300 and/or may transmit the reference clock RCK_2, which is generated by tuning the reference clock RCK_l, to the second storage device 2300…, the reference clock RCK_2 may be a delayed version of the reference clock RCK_l (Jeong: ¶ [0095]), and generate the clock signal CKl by using the reference clock RCK_l transmitted from the operation processor device 3100. The clock control logic 3220 may generate a clock signal for use in data exchanges with the operation processor device 3100 and/or the second storage device 3300 by using the reference clock RCK_l…, the first storage device 3200 may continue to exchange data with the second storage device 3300 in the high-speed serial interfacing manner (Jeong: ¶ [0101]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeong in the teachings of Yagi. A person having ordinary skill in the art would have been motivated to do so as the clock tuner 2227 may adjust parameters of the reference clock RCK_l, such as a voltage level, a frequency, an amplitude, a slew rate, a duty ratio, a driving strength, etc., to be suitable for desired requirements
of the second storage device 2300. That is, the reference clock tuner 2227 may generate the reference clock RCK_2 by tuning the reference clock RCK_l with reference to a waveform control signal Waveform CNTL based on various desired parameters, such as the desired parameters of the
second storage device 2300 (Jeong: ¶ [0088]) and to control the timing of data transfer to other storage devices.
Regarding Claim 2,
Claim 2 is dependent on Claim 1, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 1. Yagi further discloses wherein the access security of the first access mode is higher than the access security of the second access mode (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set, ¶¶ [0095-0100, 0134-137]).
Regarding Claim 3,
Claim 3 is dependent on Claim 2, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 2. Yagi further discloses wherein data accessed based on the first access control signal for the first storage device is the same as data accessed based on the second access control signal for the second storage device (Yagi: ¶ [0098] when safety core 1162 accesses
RAM 115 based on a prescribed instruction in application 1162p, safety core 1162 is able to access both safety storage area 1152 and standard storage area 1154 as shown in FIG. 6, whereas when standard core 1164 accesses RAM 115 based on the same prescribed instruction in application 1164p, standard core 1164 is able to access standard storage
area 1154 but is restricted from accessing safety storage area 1152 as shown in FIG. 6, ¶ [0102] When safety core 1262 accesses RAM 125 based on a prescribed instruction in an application 1262p, safety core 1262 is able to access both safety storage area 1252 and
standard storage area 1254 as shown in FIG. 6, whereas when standard core 1264 accesses RAM 125 based on the same prescribed instruction in an application 1264p, standard
core 1264 is able to access standard storage area 1254 but is restricted from accessing safety storage area 1252 as shown in FIG. 6, ¶¶ [0134-0137, 0050-0052]).
Regarding Claim 4,
Claim 4 is dependent on Claim 1, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 1. Yagi further discloses wherein: the target access mode is the second access mode, and the M storage devices include a first storage device and a second storage device (Yagi: ¶ [0021] control device further includes a monitoring processor, as a coprocessor configured to assist a processor including the processor core configured to perform the standard control and the processor core configured to perform the safety control, the monitoring processor monitoring access from the processor to the first storage area and the second storage area, ¶¶ [0022, 0050-0052]); and
a third access control signal matching the second access mode for the first storage device, is the same as a fourth access control signal matching the second access mode for the second storage device (Yagi: ¶ [0098] whereas when standard core 1164 accesses RAM 115 based on the same prescribed instruction in application 1164p, standard core 1164 is able to access standard storage area 1154 but is restricted from accessing safety storage area 1152 as shown in FIG. 6, ¶ [0102] whereas when standard core 1264 accesses RAM 125 based on the same prescribed instruction in an application 1264p, standard core 1264 is able to access standard storage area 1254 but is restricted from accessing safety storage area 1252 as shown in FIG. 6, ¶¶ [0134-0137, 0050-0052See Fig. 5), the access speed of the second access mode being higher than the access speed of the first access mode.
Yagi does not explicitly disclose:
a third access control signal matching the second access mode for the first storage device, is the same as a fourth access control signal matching the second access mode for the second storage device, the access speed of the second access mode being higher than the access speed of the first access mode.
Gokita further discloses an information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first memory is configured to store data and has a first access speed. The second memory is configured to store data and has a second access speed different from the first access speed (Gokita: [Abstract]), The DRAM 12 is an example of a first memory that stores first data and is a volatile storage device that may store data in a readable and writable manner…, The NAND flash memory 13 is an example of a second memory that stores second data and is a nonvolatile storage device that may store data in a readable and writable manner (Gokita: ¶ [0076-0077]), and an access speed of the DRAM 12 is higher than that of the NAND flash memory 13 (Gokita: ¶[0078], also see ¶¶ [0138-0139]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gokita in the teachings of Yagi. A person having ordinary skill in the art would have been motivated to do so because respective storage destinations of first data stored in the first memory and second data stored in the second memory from among the first memory and the second memory based on a first access probability and a first latency of the first data and a second access probability and a second latency of the second data (Gokita: ¶ [0018]), therefore, frequently accessed data can be stored in faster memory and rarely accessed data can be stored in slower memory improving the system performance.
Regarding Claim 5,
Claim 5 is dependent on Claim 4, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 4. Yagi further discloses wherein data accessed based on the third access control signal for the first storage device is different from data accessed based on the fourth access control signal for the second storage device (Yagi: ¶ [0098] when safety core 1162 accesses RAM 115 based on a prescribed instruction in application 1162p, safety core 1162 is able to access both safety storage area 1152 and standard storage area 1154 as shown in FIG. 6, ¶ [0102] whereas when standard core 1264 accesses RAM 125 based on the same prescribed instruction in an application 1264p, standard core 1264 is able to access standard storage area 1254 but is restricted from accessing safety storage area 1252 as shown in FIG. 6).
Regarding Claim 6,
Claim 6 is dependent on Claim 1, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 1. Yagi further discloses wherein: the data access request includes access addresses for the M storage devices (Yagi: ¶ [0015] the control device includes a data table that defines permission and prohibition of access to memory addresses of the storage unit, ¶¶[0050-0052], Figs. 1, 6); and
determining the target access mode for the M storage devices based on the data access request includes determining the target access mode for the M storage devices based on attributes of the access addresses (Yagi: ¶ [0081] Conversion table 600 is one example of a "data table," and includes, as shown in FIG. 4, attribute information for determining the type of a core between safety core 1162 and standard core 1164, and a virtual address that is converted to a physical address of RAM 115, ¶ [0082] the physical address of RAM 115 is divided into a physical address range 1 for system (for example, 0000 to 3FFF), a physical address range 2 for safety control (for example, 4000 to 4FFF), a physical address range 3 for standard control (for example, 5000 to 5FFF), a physical address range 4 for safety control (for example, 6000 to 6FFF), ¶¶ [0050-0052, 0083-0086]).
Regarding Claim 7,
Claim 7 is dependent on Claim 6, and the combination of Ya Yagi, Gokita and Jeong discloses all the limitations of Claim 6. Yagi further discloses wherein: the attributes of the access addresses are determined by dividing storage regions of the M storage devices into at least two types (Yagi: ¶¶ [0050-0052, 0081-0086], See Fig. 5 RAM 115—1152,1154 and RAM 125—1252, 1254, Fig. 6); and
a first type storage region corresponds to the first access mode, and a second type storage region corresponds to a second access mode (Yagi: ¶ [0093] as a mode indicative of a state of processor 116, a privileged mode and a user mode are provided for each of safety core 1162 and standard core 1164…, privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.").
Regarding Claim 11,
Claim 11 is dependent on Claim 1, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 1. Yagi further discloses obtaining a monitoring result for performing the data access on the M storage devices (Yagi: ¶ [0022] monitoring processor that monitors access from the processor including the first operating unit and the second operating unit to the first storage area and the second storage area, ¶ [0140] when it is detected by monitoring processor 219 that standard cores 2262 and 2264 are trying to access safety storage area 2152, exception handling is performed); and
determining whether to generate a second warning signal based on the monitoring result (Yagi: ¶ [0140] when it is detected by monitoring processor 219 that standard cores 2262 and 2264 are trying to access safety storage area 2152, exception handling is performed (i.e. exception handling set flags or signals), ¶ [0076]).
Regarding Claim 12,
Yagi discloses a data access device comprising (Yagi: ¶ [0050] control device 100 includes a plurality of microcontroller units (MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively. In the present embodiment, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, ¶¶ [0051-0052]), one or more processors (Yagi: ¶ [0050-0052]), one or more memories communicatively connected to the one or more processors and storing an instruction that, when executed by the one or more processors, causes the one or more processors to (Yagi: ¶¶ [0050-0052, 0074-0075, 0080]), and discloses all the limitations of Claim 12, in combination with Gokita and Jeong, as discussed in Claim 1. Therefore, Claim 12 is rejected using the same rationales as discussed in Claim 1.
Regarding Claim 13,
Claim 13 is dependent on Claim 12, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 12. The combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 13 as discussed in Claim 2. Therefore, Claim 13 is rejected using the same rationales as discussed in Claim 2.
Regarding Claim 14,
Claim 14 is dependent on Claim 13, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 13. The combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 14 as discussed in Claim 3. Therefore, Claim 14 is rejected using the same rationales as discussed in Claim 3.
Regarding Claim 15,
Claim 15 is dependent on Claim 12, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 12. The combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 15 as discussed in Claim 4. Therefore, Claim 15 is rejected using the same rationales as discussed in Claim 4.
Regarding Claim 17,
Claim 17 is dependent on Claim 12, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 12. The combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 17 as discussed in Claim 6. Therefore, Claim 17 is rejected using the same rationales as discussed in Claim 6.
Regarding Claim 18,
Claim 18 is dependent on Claim 17, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 17. The combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 18 as discussed in Claim 7. Therefore, Claim 18 is rejected using the same rationales as discussed in Claim 7.
Regarding Claim 20,
Yagi discloses a non-transitory computer-readable storage medium storing an instruction that, when executed by one or more processors, causes the one or more processors to (Yagi: ¶ [0075] Safety core 1262 of processor 126 implements the safety control by reading safety system program 1222 stored in safety ROM 122, and developing and executing the
program in the storage area in RAM 125. Likewise, standard core 1264 of processor 126 implements the standard control by reading standard system program 1242 stored in standard ROM 124, and developing and executing the program in the storage area in RAM 125, ¶ [0050] control device 100 includes a plurality of microcontroller units (MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively. In the present embodiment, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, ¶¶ [0051-0052, 0080]), and discloses all the limitations of Claim 20, in combination with Gokita and Jeong, as discussed in Claim 1. Therefore, Claim 20 is rejected using the same rationales as discussed in Claim 1.
Regarding Claim 21,
Claim 21 is dependent on Claim 1, and the combination of Yagi, Gokita and Jeong discloses all the limitations of Claim 1. The combination of Yagi and Gokita does not explicitly disclose wherein access control signals for each of the M storage devices include a chip selection signal and a clock signal.
Jeong further discloses the removable storage device 1300a may be implemented in the form
of a card, a stick, a chip package, etc., and may be mounted in or detached from the slot 1401(Jeong: ¶[0048], also see ¶ [0054]), the first storage device 2200 receives a command CMD and/or a query from the operation processor device 2100 (Jeong: ¶[0091]), the first storage device 2200 may determine the access mode of the second storage device 2300 with reference to the command CMD …, the first storage device 2200 may decode the command CMD and/or the query and may determine whether an access of the operation processor device 2100 to the second storage device 2300 is present and/or the access mode based on the decoding result (Jeong: ¶ [0092]), transmit the reference clock RCK_2, which is generated by tuning the reference clock RCK_l, to the second storage device 2300 (Jeong: ¶ [0095]), and generate the clock signal CKl by using the reference clock RCK_l transmitted from the operation processor device 3100. The clock control logic 3220 may generate a clock signal for use in data exchanges with the operation processor device 3100 and/or the second storage device 3300 by using the reference clock RCK_l…, the first storage device 3200 may continue to exchange data with the second storage device 3300 in the high-speed serial interfacing manner (Jeong: ¶ [0101]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jeong in the teachings of Yagi. A person having ordinary skill in the art would have been motivated to do so as the clock tuner 2227 may adjust parameters of the reference clock RCK_l, such as a voltage level, a frequency, an amplitude, a slew rate, a duty ratio, a driving strength, etc., to be suitable for desired requirements
of the second storage device 2300. That is, the reference clock tuner 2227 may generate the reference clock RCK_2 by tuning the reference clock RCK_l with reference to a waveform control signal Waveform CNTL based on various desired parameters, such as the desired parameters of the
second storage device 2300 (Jeong: ¶ [0088]) and to control the timing of data transfer of the storage devices.
Allowable Subject Matter
10. Claims 8-10 and 19 would be allowable if rewritten in independent form including all the limitations of the base claims and any intervening claims.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US-20050114616-A1
US-20140122820-A1
US-20210232510-A1
US-20140283141-A1
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMEERA WICKRAMASURIYA whose telephone number is (571)272-1507. The examiner can normally be reached on M-F 9:45am - 6:15pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jung W. Kim can be reached on 571-272-3804. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMEERA WICKRAMASURIYA/
Examiner, Art Unit 2494
/JUNG W KIM/Supervisory Patent Examiner, Art Unit 2494
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