DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement(s) (IDS) submitted on 02/07/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is being considered by the examiner.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
5. Claim 1 recites in a limitation “obtaining a data access request for M storage devices, M being an integer greater than or equal to 2” (emphasis added). Another limitation recites “performing data access on the storage devices based on access control signals matching the target access mode for the storage devices” (emphasis added). It is unclear whether the applicant is trying to refer to the same “M storage devices” recited in the first limitation or different “storage devices”, therefore, failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 9, 12 and 20 suffer similar deficiencies and rejected using the same rationale.
Dependent Claims 2-11 and 13-19 are rejected based upon their respective dependence from independent Claims 1 and 12.
Claim 20 recites in the preamble “A non-transitory computer-readable storage medium storing an instruction…” (i.e. a manufacture). However, the claim body recite “a determination unit configured to… and an access unit configured to….” which are structural components of a system or device. Therefore, it is unclear whether the claim is directed to a storage medium or to a device/system comprising structural units, and the inclusion of structural components within the computer-readable storage medium renders the scope of the claim unclear. Accordingly, Claim 20 fails to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. Claims 1-7, 11-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over YAGI et al. ( US 2022/0365730 Al, hereinafter Yagi) [As disclosed in IDS] in view of GOKITA (US 2019/0018797 Al, hereinafter Gokita) [As disclosed in IDS].
Regarding Claim 1,
Yagi discloses a data access method comprising (Yagi: ¶ [0091] schematic diagrams for illustrating a second example of an access restricting method in a control device 100b according to the first embodiment. In an exemplary hardware configuration of control device 100b shown in FIG. 5, ¶¶ [0078, 0105]):
obtaining a data access request for M storage devices, M being an integer greater than or equal to 2 (Yagi: ¶ [0050] control device 100 includes a plurality of microcontroller units (MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively…, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, ¶ [0084] Safety core 1162 and standard core 1164 can each access the physical address of RAM 115 by accessing a virtual address assigned in conversion table 600, ¶¶ [0085, 0086], Fig. 5 –115, 125);
determining a target access mode for the M storage devices based on the data access request (Yagi: ¶ [0093] as a mode indicative of a state of processor 116, a privileged mode and a user
mode are provided for each of safety core 1162 and standard core 1164…, privileged
mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the
user mode is one example of a "second mode.", ¶¶ [0019, 0050, 0094-0095, 0099-0104]);
performing data access on the storage devices based on access control signals matching the target access mode for the storage devices (Yagi: ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set, ¶ [0098] when safety core 1162 accesses RAM 115 based on a prescribed instruction in application 1162p, safety core 1162 is able to access both safety storage area 1152 and standard storage area 1154 as shown in FIG. 6, whereas when standard core 1164 accesses RAM 115 based on the same prescribed instruction in application
1164p, standard core 1164 is able to access standard storage area 1154 but is restricted from accessing safety storage area 1152 as shown in FIG. 6, ¶¶ [0093, 0095, 0099]);
wherein: the target access mode includes a first access mode and a second access mode (Yagi: ¶ [0093] as a mode indicative of a state of processor 116, a privileged mode and a user
mode are provided for each of safety core 1162 and standard core 1164…, privileged
mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the
user mode is one example of a "second mode.", ¶ [0007]); and
access security and/or access speed generated when the data access is performed on the storage devices in the first access mode is different from access security and/or access speed generated in the second access mode (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a
storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set. ¶¶ [0095-0100]).
Yagi does not explicitly disclose:
access security and/or access speed generated when the data access is performed on the storage devices in the first access mode is different from access security and/or access speed generated in the second access mode.
However, Gokita from the same field of endeavor as the claimed invention discloses an information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first memory is configured to store data and has a first access speed. The second memory is configured to store data and has a second
access speed different from the first access speed (Gokita: [Abstract]), The DRAM 12 is an example of a first memory that stores first data and is a volatile storage device that may store
data in a readable and writable manner…, The NAND flash memory 13 is an example of a
second memory that stores second data and is a nonvolatile storage device that may store data in a readable and writable manner (Gokita: ¶ [0076-0077]), and an access speed of the DRAM 12 is higher than that of the NAND flash memory 13 (Gokita: ¶[0078]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gokita in the teachings of Yagi. A person having ordinary skill in the art would have been motivated to do so because respective storage destinations of first data stored in the first memory and second data stored in the second memory from among the first memory and the second memory based on a first access probability and a first latency of the first data and a second access probability and a second latency of the second data (Gokita: ¶ [0018]), therefore, frequently accessed data can be stored in faster memory and rarely accessed data can be stored in slower memory improving the system performance.
Regarding Claim 2,
Claim 2 is dependent on Claim 1, and the combination of Yagi and Gokita discloses all the limitations of Claim 1. Yagi further discloses wherein: the target access mode is the first access mode, and the storage devices include a first storage device and a second storage device (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0050] control device 100 includes a plurality of microcontroller units(MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively…, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, Fig. 5 –115, 125);
a first access control signal matching the first access mode for the first storage device is different from a second access control signal matching the first access mode for the second storage device (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set, ¶¶ [0095-0104]); and
the access security of the first access mode is higher than the access security of the second access mode (Yagi: ¶ [0093] a privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.", ¶ [0094] When each of safety core 1162 and standard core 1164 is set to the user mode, and a prescribed instruction in applications 1162p and 1164p is executed, access to a storage area specified in the privileged mode is prohibited. In other words, access is more restricted when the user mode is set, than when the privileged mode is set, ¶¶ [0095-0100, 0134-137]).
Regarding Claim 3,
Claim 3 is dependent on Claim 2, and the combination of Yagi and Gokita discloses all the limitations of Claim 2. Yagi further discloses wherein data accessed based on the first access control signal for the first storage device is the same as data accessed based on the second access control signal for the second storage device (Yagi: ¶ [0098] when safety core 1162 accesses
RAM 115 based on a prescribed instruction in application 1162p, safety core 1162 is able to access both safety storage area 1152 and standard storage area 1154 as shown in FIG. 6, whereas when standard core 1164 accesses RAM 115 based on the same prescribed instruction in application 1164p, standard core 1164 is able to access standard storage
area 1154 but is restricted from accessing safety storage area 1152 as shown in FIG. 6, ¶ [0102] When safety core 1262 accesses RAM 125 based on a prescribed instruction in an application 1262p, safety core 1262 is able to access both safety storage area 1252 and
standard storage area 1254 as shown in FIG. 6, whereas when standard core 1264 accesses RAM 125 based on the same prescribed instruction in an application 1264p, standard
core 1264 is able to access standard storage area 1254 but is restricted from accessing safety storage area 1252 as shown in FIG. 6, ¶¶ [0134-0137, 0050-0052]).
Regarding Claim 4,
Claim 4 is dependent on Claim 1, and the combination of Yagi and Gokita discloses all the limitations of Claim 1. Yagi further discloses wherein: the target access mode is the second access mode, and the storage devices include a first storage device and a second storage device (Yagi: ¶ [0021] control device further includes a monitoring processor, as a coprocessor configured
to assist a processor including the processor core configured to perform the standard control and the processor core configured to perform the safety control, the monitoring processor monitoring access from the processor to the first storage area and the second storage area, ¶¶ [0022, 0050-0052]); and
a third access control signal matching the second access mode for the first storage device, is the same as a fourth access control signal matching the second access mode for the second storage device (Yagi: ¶ [0098] whereas when standard core 1164 accesses RAM 115 based on the same prescribed instruction in application 1164p, standard core 1164 is able to access standard storage area 1154 but is restricted from accessing safety storage area 1152 as shown in FIG. 6, ¶ [0102] whereas when standard core 1264 accesses RAM 125 based on the same prescribed instruction in an application 1264p, standard core 1264 is able to access standard storage area 1254 but is restricted from accessing safety storage area 1252 as shown in FIG. 6, ¶¶ [0134-0137, 0050-0052See Fig. 5), the access speed of the second access mode being higher than the access speed of the first access mode.
Yagi does not explicitly disclose:
a third access control signal matching the second access mode for the first storage device, is the same as a fourth access control signal matching the second access mode for the second storage device, the access speed of the second access mode being higher than the access speed of the first access mode.
Gokita further discloses an information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first memory is configured to store data and has a first access speed. The second memory is configured to store data and has a second access speed different from the first access speed (Gokita: [Abstract]), The DRAM 12 is an example of a first memory that stores first data and is a volatile storage device that may store data in a readable and writable manner…, The NAND flash memory 13 is an example of a second memory that stores second data and is a nonvolatile storage device that may store data in a readable and writable manner (Gokita: ¶ [0076-0077]), and an access speed of the DRAM 12 is higher than that of the NAND flash memory 13 (Gokita: ¶[0078], also see ¶¶ [0138-0139]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Gokita in the teachings of Yagi. A person having ordinary skill in the art would have been motivated to do so because respective storage destinations of first data stored in the first memory and second data stored in the second memory from among the first memory and the second memory based on a first access probability and a first latency of the first data and a second access probability and a second latency of the second data (Gokita: ¶ [0018]), therefore, frequently accessed data can be stored in faster memory and rarely accessed data can be stored in slower memory improving the system performance.
Regarding Claim 5,
Claim 5 is dependent on Claim 4, and the combination of Yagi and Gokita discloses all the limitations of Claim 4. Yagi further discloses wherein data accessed based on the third access control signal for the first storage device is different from data accessed based on the fourth access control signal for the second storage device (Yagi: ¶ [0098] when safety core 1162 accesses RAM 115 based on a prescribed instruction in application 1162p, safety core 1162 is able to access both safety storage area 1152 and standard storage area 1154 as shown in FIG. 6, ¶ [0102] whereas when standard core 1264 accesses RAM 125 based on the same prescribed instruction in an application 1264p, standard core 1264 is able to access standard storage area 1254 but is restricted from accessing safety storage area 1252 as shown in FIG. 6).
Regarding Claim 6,
Claim 6 is dependent on Claim 1, and the combination of Yagi and Gokita discloses all the limitations of Claim 1. Yagi further discloses wherein: the data access request includes access addresses for the M storage devices (Yagi: ¶ [0015] the control device includes a data table that defines permission and prohibition of access to memory addresses of the storage unit, ¶¶[0050-0052], Figs. 1, 6); and
determining the target access mode for the M storage devices based on the data access request includes determining the target access mode for the M storage devices based on attributes of the access addresses (Yagi: ¶ [0081] Conversion table 600 is one example of a "data table," and includes, as shown in FIG. 4, attribute information for determining the type of a core between safety core 1162 and standard core 1164, and a virtual address that is converted to a physical address of RAM 115, ¶ [0082] the physical address of RAM 115 is divided into a physical address range 1 for system (for example, 0000 to 3FFF), a physical address range 2 for safety control (for example, 4000 to 4FFF), a physical address range 3 for standard control (for example, 5000 to 5FFF), a physical address range 4 for safety control (for example, 6000 to 6FFF), ¶¶ [0050-0052, 0083-0086]).
Regarding Claim 7,
Claim 7 is dependent on Claim 6, and the combination of Yagi and Gokita discloses all the limitations of Claim 6. Yagi further discloses wherein: the attributes of the access addresses are determined by dividing storage regions of the storage devices into at least two types (Yagi: ¶¶ [0050-0052, 0081-0086], See Fig. 5 RAM 115—1152,1154 and RAM 125—1252, 1254, Fig. 6); and
a first type storage region corresponds to the first access mode, and a second type storage region corresponds to a second access mode (Yagi: ¶ [0093] as a mode indicative of a state of processor 116, a privileged mode and a user mode are provided for each of safety core 1162 and standard core 1164…, privileged mode and a user mode are specified for each of safety storage area 1152 and standard storage area 1154. The privileged mode is one example of a "first mode," and the user mode is one example of a "second mode.").
Regarding Claim 11,
Claim 11 is dependent on Claim 1, and the combination of Yagi and Gokita discloses all the limitations of Claim 1. Yagi further discloses obtaining a monitoring result for performing the data access on the storage devices (Yagi: ¶ [0022] monitoring processor that monitors access from the processor including the first operating unit and the second operating unit to the first storage area and the second storage area, ¶ [0140] when it is detected by monitoring processor 219 that standard cores 2262 and 2264 are trying to access safety storage area 2152, exception handling is performed); and
determining whether to generate a second warning signal based on the monitoring result (Yagi: ¶ [0140] when it is detected by monitoring processor 219 that standard cores 2262 and 2264 are trying to access safety storage area 2152, exception handling is performed (i.e. exception handling set flags or signals), ¶ [0076]).
Regarding Claim 12,
Yagi discloses a data access device comprising (Yagi: ¶ [0050] control device 100 includes a plurality of microcontroller units (MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively. In the present embodiment, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, ¶¶ [0051-0052]), one or more processors (Yagi: ¶ [0050-0052]), one or more memories communicatively connected to the one or more processors and storing an instruction that, when executed by the one or more processors, causes the one or more processors to (Yagi: ¶¶ [0050-0052, 0074-0075, 0080]), and discloses all the limitations of Claim 12, in combination with Gokita, as discussed in Claim 1. Therefore, Claim 12 is rejected using the same rationales as discussed in Claim 1.
Regarding Claim 13,
Claim 13 is dependent on Claim 12, and the combination of Yagi and Gokita discloses all the limitations of Claim 12. The combination of Yagi and Gokita discloses all the limitations of Claim 13 as discussed in Claim 2. Therefore, Claim 13 is rejected using the same rationales as discussed in Claim 2.
Regarding Claim 14,
Claim 14 is dependent on Claim 13, and the combination of Yagi and Gokita discloses all the limitations of Claim 13. The combination of Yagi and Gokita discloses all the limitations of Claim 14 as discussed in Claim 3. Therefore, Claim 14 is rejected using the same rationales as discussed in Claim 3.
Regarding Claim 15,
Claim 15 is dependent on Claim 12, and the combination of Yagi and Gokita discloses all the limitations of Claim 12. The combination of Yagi and Gokita discloses all the limitations of Claim 15 as discussed in Claim 4. Therefore, Claim 15 is rejected using the same rationales as discussed in Claim 4.
Regarding Claim 16,
Claim 16 is dependent on Claim 15, and the combination of Yagi and Gokita discloses all the limitations of Claim 15. The combination of Yagi and Gokita discloses all the limitations of Claim 16 as discussed in Claim 5. Therefore, Claim 16 is rejected using the same rationales as discussed in Claim 5.
Regarding Claim 17,
Claim 17 is dependent on Claim 12, and the combination of Yagi and Gokita discloses all the limitations of Claim 12. The combination of Yagi and Gokita discloses all the limitations of Claim 17 as discussed in Claim 6. Therefore, Claim 17 is rejected using the same rationales as discussed in Claim 6.
Regarding Claim 18,
Claim 18 is dependent on Claim 17, and the combination of Yagi and Gokita discloses all the limitations of Claim 17. The combination of Yagi and Gokita discloses all the limitations of Claim 18 as discussed in Claim 7. Therefore, Claim 18 is rejected using the same rationales as discussed in Claim 7.
Regarding Claim 20,
Yagi discloses a non-transitory computer-readable storage medium storing an instruction that, when executed by one or more processors, causes the one or more processors to (Yagi: ¶ [0075] Safety core 1262 of processor 126 implements the safety control by reading safety system program 1222 stored in safety ROM 122, and developing and executing the
program in the storage area in RAM 125. Likewise, standard core 1264 of processor 126 implements the standard control by reading standard system program 1242 stored in standard ROM 124, and developing and executing the program in the storage area in RAM 125, ¶ [0050] control device 100 includes a plurality of microcontroller units (MCUs), and a plurality of RAMs (Random access memories) corresponding to the plurality of MCUs, respectively. In the present embodiment, control device 100 includes an MCU 110 and an MCU 120, a RAM 115 corresponding to MCU 110, and a RAM 125 corresponding to MCU 120. The number of MCUs and RAMs is not limited to two, and three or more MCUs and RAMs may be provided, ¶¶ [0051-0052, 0080]), a determination unit (Yagi: ¶ [0079] an MMU (Memory Management Unit) 117 connected to processor 116. MMU 117 has a memory
protecting function, and prevents each core in processor 116 from accessing a storage area not assigned to the core.¶¶ [0021-0022, 0080-0086]), an access unit (Yagi: ¶ [0075] Safety core 1262 of processor 126 implements the safety control by reading safety system program 1222 stored in safety ROM 122, and developing and executing the program in the storage area in RAM 125. Likewise, standard core 1264 of processor 126 implements the standard control
by reading standard system program 1242 stored in standard ROM 124, and developing and executing the program in the storage area in RAM 125, ¶¶ [0074, 0076), and discloses all the limitations of Claim 20, in combination with Gokita, as discussed in Claim 1. Therefore, Claim 20 is rejected using the same rationales as discussed in Claim 1.
Allowable Subject Matter
11. Claims 8-10 and 19 would be allowable if rewritten to overcome the 35 U.S.C. 112(b) set forth in this rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US-20050114616-A1
US-20140122820-A1
US-20210232510-A1
US-20140283141-A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMEERA WICKRAMASURIYA whose telephone number is (571)272-1507. The examiner can normally be reached on MON-FRI 8AM-4:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUNG W. KIM can be reached on (571)272-3804. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMEERA WICKRAMASURIYA/
Examiner, Art Unit 2494
/JUNG W KIM/Supervisory Patent Examiner, Art Unit 2494