DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 30th, 2025 has been entered.
Claim Status
Claims 1, 12 and 20 have been amended. No new claims have been added or cancelled. Claims 1-20 remain pending and are ready for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 25th, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 10-16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakutsu et al. (US Publication No. 2024/0094923 -- "Wakutsu") in view of Kirchner (US Publication No. 2017/0052734 – “Kirchner”).
Regarding claim 1, Wakutsu teaches A memory system, comprising: a memory, wherein a physical space of the memory is divided into a user space … and a hidden space; (Wakutsu Fig. 1; Wakutsu paragraph [0092], As illustrated in FIG. 6, the NAND memory 200 includes: an SLC buffer area 220 composed only of blocks BLK set to be used in the first mode (here, the SLC mode); a first SLC/TLC buffer area 221 that can include blocks BLK set to be used in the second mode (here, the TLC mode) in addition to blocks BLK set to be used in the first mode; and a TLC user data area 222 composed only of blocks BLK set to be used in the second mode. The physical memory can be divided into at least two separate spaces) and a memory controller coupled with the memory and configured to: set a first block of the user space as a write booster buffer, (Wakutsu Fig. 7; Wakutsu paragraph [0111], Accordingly, in the first embodiment, further, the capacity of the first SLC/TLC buffer area 221 is configured to be variable. When there are enough available blocks BLK, that is, free blocks in the TLC user data area 222, some of them are added to the first SLC/TLC buffer area 221 as TLC blocks or SLC blocks. Therefore, when there are many available blocks BLK in the TLC user data area 222, the capacity of the first SLC/TLC buffer area 221 can be increased, thereby preventing the transcription write amount in the first transcription process. A block (or plurality of blocks) from the user data area can be assigned as an SLC buffer block, which functions as a write booster buffer by providing increased access speed, see Wakutsu paragraph [0095], The SLC mode completes a write operation faster than the TLC mode. Therefore, in order to improve the throughput of the memory system 1 viewed from the host device 2, the controller 100 writes host data to open blocks in the SLC buffer area 220 or the first SLC/TLC buffer area 221) wherein the first block is of a first level cell mode, and the write booster buffer is configured to buffer data; (Wakutsu paragraph [0111], Accordingly, in the first embodiment, further, the capacity of the first SLC/TLC buffer area 221 is configured to be variable. When there are enough available blocks BLK, that is, free blocks in the TLC user data area 222, some of them are added to the first SLC/TLC buffer area 221 as TLC blocks or SLC blocks. Therefore, when there are many available blocks BLK in the TLC user data area 222, the capacity of the first SLC/TLC buffer area 221 can be increased, thereby preventing the transcription write amount in the first transcription process. The block(s) selected for the write boost buffer are configured to operate in SLC buffer mode) and set a free block of the hidden space (The hidden space may be the SLC/TLC buffer area (see Fig. 6; Ref #221), which may be hidden with respect to the TLC user data area which is where user data received from the host is preferentially stored and used to determine all valid read data when changing storage mode, see Wakutsu paragraph [0182], The user data area 240 is an area in which the user data received from the host device 2 is stored and Wakutsu paragraph [0194], when the user data area 240 is initialized by changing the storage mode, the host device 2 reads all the necessary data in the user data area 240 and then instructs to change the storage mode by the second setting command, as seen in Wakutsu Fig. 16; S502) as the write booster buffer, wherein the free block is of the first level cell mode (Wakutsu paragraph [0182], The user data area 240 is an area in which the user data received from the host device 2 is stored. Wakutsu paragraph [0112], A block BLK added to the first SLC/TLC buffer area 221 as an SLC block transitions to an open block and then undergoes a host write process in the SLC mode. A block BLK added to the first SLC/TLC buffer area 221 as a TLC block transitions to an open block and then undergoes a host write process in the TLC mode. When the first SLC/TLC buffer area 221 includes both blocks BLK added as SLC blocks and blocks BLK added as TLC blocks, the controller 100 preferentially transitions the block BLK added as an SLC block to an open block. Blocks contained in the storage area (see Fig. 2; Ref #221) can also be assigned as an SLC buffer block).
Wakutsu does not teach a user space configured to store data and a hidden space configured to store parameter and state information.
However, Kirchner teaches a user space configured to store data and a hidden space configured to store parameter and state information (Kirchner Fig. 4 (see Ref #471 and #472 for user and hidden spaces); also see Kirchner paragraph [0086], As such, the user section 371 may be formed of the more compact NAND-type flash, while the much smaller spare section 372 may be formed of the more flexible NOR-type flash. Consequently, the user section 371 and the spare section 372 may also be physically separated from each other, wherein corresponding sections of the address decoder 351 and the data I/O circuit 354 may be provided. As will be discussed in detail below, the spare section 372 may be provided with such a size that a direct mapping between the memory elements of the spare section 372 and the erase units of the user section 371 exists. Such a mapping may even be implemented in hardware by connecting corresponding word and bit lines to corresponding erase units and memory elements. The size, and possibly dimensions, of the spare section 372 may be chosen such that it allows storing erase status information for each of the erase units of the user section 371. If erase status information shall be stored in the form of PPAs, sufficient memory of the spare section 372 may be provided to allow for a sufficient buffering functionality. The nonvolatile memory cells of the user section 371 are dedicated to the bulk storage of actual user data, such as images, videos, audio files, text files or the like, while the spare section 372 is dedicated to the storage of metadata in the form of erase status information. User space may store data, while a hidden space may store state information and various other metadata).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Wakutsu with those of Kirchner. Kirchner teaches dividing a memory into a user and hidden storage space which can allow for more efficient memory usage such as resource re-allocation such as by using the hidden space to determine address information or as a backup buffer (i.e., see Kirchner paragraph [0089], Each of the two blocks 474-1 and 474-2 shall have a size sufficient to store erase status information for all erase units of the user section 471, in particular, in the form of an erase unit map, wherein each of the erase units of the user section 471 is mapped to a memory element, possibly comprising multiple nonvolatile memory cells, of the block. It shall be understood that multiple blocks may be provided for the storage of such an erase unit map, if needed due to the size of the user section 471. Furthermore, more than one duplicate may be provided to implement a higher redundancy. For the sake of simplicity, in the following, a structure is assumed, wherein two blocks 474-1 and 474-2 are provided to store the erase unit map and its update in a copy-over and erase operation).
Claims 12 and 20 are the corresponding method and computer readable medium claims to system claim 1. They are rejected with the same references and rationale.
Regarding claim 2, Wakutsu in view of Kirchner teaches The memory system of claim 1, wherein the hidden space comprises an over provisioning subspace configured for garbage collection; (Wakutsu paragraph [0037], The controller 100 further executes a transcription process to transcribe data in the NAND memory 200. The transcription process may also be referred to as a garbage collection (also referred to as a compaction). The storage space can include a space configured for garbage collection/compaction) and the memory controller is configured to: set a free block of the over provisioning subspace as the write booster buffer (see Wakutsu Fig. 7; Ref #221, free block section; also see Wakutsu paragraph [0080], The active block may transition to a free block by the transcription process. The transcription process is a process of transcribing valid data stored in an active block to an open block and invalidating all data stored in the active block which is a transcription source. As a result, the active block which is the transcription source transitions to a free block. That is, the transcription process can be considered as a process of generating a free block. It should be noted that transcription may also be referred to as transfer, relocation, or move. The free block can be used to facilitate a compaction operation, or set as an SLC buffer mode block).
Claim 13 is the corresponding method claim to system claim 2. It is rejected with the same references and rationale.
Regarding claim 3, Wakutsu in view of Kirchner teaches The memory system of claim 2, wherein the memory controller is further configured to: when the hidden space requires use of the free block of the over provisioning subspace, return the free block occupied by the write booster buffer to the over provisioning subspace (see Wakutsu Fig. 7; Ref #221, free block section; also see Wakutsu paragraph [0080], The active block may transition to a free block by the transcription process. The transcription process is a process of transcribing valid data stored in an active block to an open block and invalidating all data stored in the active block which is a transcription source. As a result, the active block which is the transcription source transitions to a free block. That is, the transcription process can be considered as a process of generating a free block. It should be noted that transcription may also be referred to as transfer, relocation, or move. The free block can be used to facilitate a compaction operation, or set as an SLC buffer mode block).
Claim 14 is the corresponding method claim to system claim 3. It is rejected with the same references and rationale.
Regarding claim 4, Wakutsu in view of Kirchner teaches The memory system of claim 3, wherein the memory controller is configured to: write data buffered in the free block occupied by the write booster buffer to a second block of the user space, wherein the second block is of a second level cell mode, (Wakutsu paragraph [0118], When the capacity of the first SLC/TLC buffer area 221 is greater than the second threshold value (S102: Yes), the processor 101 transcribes a part or all of the data in the first SLC/TLC buffer area 221 to the TLC user data area 222 by the first transcription process (S103). Then, the processor 101 assigns some blocks in the group of the blocks BLK constituting the first SLC/TLC buffer area 221 to the TLC user data area 222, thereby reducing the capacity of the first SLC/TLC buffer area 221 to the second threshold value (S104). The data can be transferred from the SLC buffer block to the TLC block in the user data area) and a number of bits stored in a memory cell of the second level cell mode is greater than a number of bits stored in a memory cell of the first level cell mode; (Wakutsu paragraph [0027], In general, according to at least one embodiment, a memory system is connectable to a host device. The memory system includes a non-volatile memory including a plurality of blocks and a controller electrically connected to the non-volatile memory. Each of the plurality of blocks includes a plurality of memory cells, and data can be written in a first mode and a second mode. The first mode is a mode in which data of a first number of bits is written in each memory cell. The second mode is a mode in which data of a second number of bits larger than the first number is written in each memory cell. The controller assigns a first plurality of blocks among the plurality of blocks to a first area. The number of bits per cell is greater in the second level cell mode) and after writing the data buffered in the free block to the second block, erase the free block so that the free block is returned to the over provisioning subspace (Wakutsu Fig. 5; see group of active blocks and group of free blocks, also see Wakutsu paragraph [0080], The active block may transition to a free block by the transcription process. The transcription process is a process of transcribing valid data stored in an active block to an open block and invalidating all data stored in the active block which is a transcription source. As a result, the active block which is the transcription source transitions to a free block. That is, the transcription process can be considered as a process of generating a free block. It should be noted that transcription may also be referred to as transfer, relocation, or move. After the data is written/moved (i.e. compacted) it may be transferred to the original location as a free block).
Claim 15 is the corresponding method claim to system claim 4. It is rejected with the same references and rationale.
Regarding claim 5, Wakutsu in view of Kirchner teaches The memory system of claim 2, wherein scenarios where the hidden space requires the use of the free block of the over provisioning subspace comprise at least one of the following: an available capacity of the hidden space being less than or equal to a preset capacity, and garbage collection (Wakutsu paragraph [0117], When the number of free blocks among the TLC blocks constituting the TLC user data area 222 is equal to or smaller than the first threshold value (S101: Yes), the processor 101 determines whether the capacity of the first SLC/TLC buffer area 221 is greater than a second threshold value (S102). Similar to the first threshold value, the second threshold value is a threshold value for determining whether to return a block already added to the first SLC/TLC buffer area 221 to the TLC user data area 222, and can be determined in any manner. Here, it is assumed that the capacity of the first SLC/TLC buffer area 221 is controlled not to fall below the set minimum value. In response to the capacity being below a threshold, a free block may be allocated from TLC to the SLC buffer, also see Wakutsu paragraph [0118], When the capacity of the first SLC/TLC buffer area 221 is greater than the second threshold value (S102: Yes), the processor 101 transcribes a part or all of the data in the first SLC/TLC buffer area 221 to the TLC user data area 222 by the first transcription process (S103)).
Regarding claim 6, Wakutsu in view of Kirchner teaches The memory system of claim 1, wherein the memory controller is further configured to: when an erase count of the free block of the hidden space is greater than or equal to a preset value, stop setting the free block of the hidden space as the write booster buffer (Wakutsu paragraph [0088], Further, as the number of P/E cycles increases, the threshold voltage of a memory cell tends to fluctuate and there is a limit to the correction capability of the error correction function of the controller 100. Therefore, an upper limit is set on the number of P/E cycles to ensure that correct data is obtained by the error correction function. When the number of P/E cycles of a memory cell reaches the upper limit, the memory cell is considered unusable because a required level of reliability is not guaranteed. The P/E count may be used to determine when a block is no longer usable, and may instead buffer/store the data to a block from the user data area (as seen in claim 1)).
Claim 16 is the corresponding method claim to system claim 6. It is rejected with the same references and rationale.
Regarding claim 10, Wakutsu in view of Kirchner teaches The memory system of claim 1, wherein the memory controller is further configured to: set the first block of the user space to the first level cell mode; (Wakutsu paragraph [0111], Accordingly, in the first embodiment, further, the capacity of the first SLC/TLC buffer area 221 is configured to be variable. When there are enough available blocks BLK, that is, free blocks in the TLC user data area 222, some of them are added to the first SLC/TLC buffer area 221 as TLC blocks or SLC blocks. Therefore, when there are many available blocks BLK in the TLC user data area 222, the capacity of the first SLC/TLC buffer area 221 can be increased, thereby preventing the transcription write amount in the first transcription process. The block(s) selected for the write boost buffer are configured to operate in SLC buffer mode) set a block of the hidden space to the first level cell mode; (Wakutsu paragraph [0112], A block BLK added to the first SLC/TLC buffer area 221 as an SLC block transitions to an open block and then undergoes a host write process in the SLC mode. A block BLK added to the first SLC/TLC buffer area 221 as a TLC block transitions to an open block and then undergoes a host write process in the TLC mode. When the first SLC/TLC buffer area 221 includes both blocks BLK added as SLC blocks and blocks BLK added as TLC blocks, the controller 100 preferentially transitions the block BLK added as an SLC block to an open block. Blocks contained in the storage area (see Fig. 2; Ref #221) can also be assigned as an SLC buffer block) and set a second block of the user space to a second level cell mode, wherein the second block is configured to store the data (Wakutsu paragraph [0111], Accordingly, in the first embodiment, further, the capacity of the first SLC/TLC buffer area 221 is configured to be variable. When there are enough available blocks BLK, that is, free blocks in the TLC user data area 222, some of them are added to the first SLC/TLC buffer area 221 as TLC blocks or SLC blocks. Therefore, when there are many available blocks BLK in the TLC user data area 222, the capacity of the first SLC/TLC buffer area 221 can be increased, thereby preventing the transcription write amount in the first transcription process. The block(s) selected for the write boost buffer are configured to operate in SLC buffer mode, however, the default function can be the TLC write blocks in TLC user data area 222).
Claim 19 is the corresponding method claim to system claim 10. It is rejected with the same references and rationale.
Regarding claim 11, Wakutsu in view of Kirchner teaches The memory system of claim 1, wherein the memory system comprises: a solid state drive, an embedded multi-media card, and a universal flash storage (Wakutsu paragraph [0030], The memory system 1 is connected to a host device 2 via a communication interface 3. The host device 2 is, for example, a processor provided in an information processing device. The information processing device is, for example, a computer such as a personal computer, a mobile phone, a smart phone, a portable music player, an imaging device, and the like. The memory system 1 is, for example, a universal flash storage (UFS) device or a solid state drive (SSD). The standard of the communication interface 3 is not limited to a specific standard).
Claim(s) 7-9 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakutsu in view of Kirchner as applied to claim 1 and 12 above, and further in view of Kashyap et al. (US Publication No. 2019/0354478 – “Kashyap”).
Regarding claim 7, Wakutsu in view of Kirchner in further view of Kashyap teaches The memory system of claim 1, wherein the memory controller is further configured to: when an erase count of the free block of the hidden space is greater than or equal to a preset value, (Wakutsu paragraph [0088], Further, as the number of P/E cycles increases, the threshold voltage of a memory cell tends to fluctuate and there is a limit to the correction capability of the error correction function of the controller 100. Therefore, an upper limit is set on the number of P/E cycles to ensure that correct data is obtained by the error correction function. When the number of P/E cycles of a memory cell reaches the upper limit, the memory cell is considered unusable because a required level of reliability is not guaranteed. The P/E count may be used to determine when a block is no longer usable, and may instead buffer the data to a block from the user data area (as seen in claim 1)) buffer data to be buffered to the free block to the first block (Kashyap paragraph [0065], FIG. 5 is a simplified block diagram illustrating non-volatile memory 134 in accordance with some embodiments. Non-volatile memory 134 includes one or more three-dimensional memory dies, of which just one is shown in FIG. 5. For example, each of the three-dimensional memory dies includes multiple individually erasable blocks that are arranged in two memory planes, plane 0 and plane 1, each having three SLC blocks (e.g., SLC1, SLC2, and SLC3), at least one MLC block (e.g., MLC1), and die-level controller 320. In some embodiments, each memory die includes a much larger number of MLC blocks than SLC blocks, for example at least five times, or ten times as many MLC blocks as SLC blocks. In some embodiments, each memory die includes three or six SLC blocks, where each set of three SLC blocks is used as a write buffer, and two (or more) different sets of SLC blocks are used in alternating or rotating fashion, so that data is written to one set of SLC blocks as an on-chip copy operation (OCC) is performed on the data written to another set of SLC blocks. Kashyap explicitly discloses the concept of using SLC-SLC buffer block rotation, and can allow for dynamic reallocation of buffered data).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Wakutsu and Kirchner with those of Kashyap. Kashyap is added to teach the concept of buffering data to be buffered into an SLC block to a separate SLC block area. This can be done based on a wear count or in rotating fashion, in order to maximize the lifespan of the SLC buffer blocks (see Kashyap paragraph [0065], FIG. 5 is a simplified block diagram illustrating non-volatile memory 134 in accordance with some embodiments. Non-volatile memory 134 includes one or more three-dimensional memory dies, of which just one is shown in FIG. 5. For example, each of the three-dimensional memory dies includes multiple individually erasable blocks that are arranged in two memory planes, plane 0 and plane 1, each having three SLC blocks (e.g., SLC1, SLC2, and SLC3), at least one MLC block (e.g., MLC1), and die-level controller 320. In some embodiments, each memory die includes a much larger number of MLC blocks than SLC blocks, for example at least five times, or ten times as many MLC blocks as SLC blocks. In some embodiments, each memory die includes three or six SLC blocks, where each set of three SLC blocks is used as a write buffer, and two (or more) different sets of SLC blocks are used in alternating or rotating fashion, so that data is written to one set of SLC blocks as an on-chip copy operation (OCC) is performed on the data written to another set of SLC blocks. Kashyap explicitly discloses the concept of using SLC-SLC buffer block rotation, and can allow for dynamic reallocation of buffered data).
Claim 17 is the corresponding method claim to system claim 7. It is rejected with the same references and rationale.
Regarding claim 8, Wakutsu in view of Kirchner in further view of Kashyap teaches The memory system of claim 7, wherein the memory controller is configured to: exchange a physical address of the free block and a physical address of the first block (Wakutsu paragraph [0181], The SLC system area 230 stores the firmware program and management information of the memory system 1a. The management information includes, for example, a logical-to-physical address conversion table that records the mappings between LBAs and locations in the NAND memory 200. That is, the SLC system area 230 is a dedicated area for storing data necessary for the operation of the memory system 1a, that is, system data, and does not store user data. When system data is lost from the memory system 1a, it may be impossible for the memory system 1a to operate properly. Therefore, the SLC system area 230 includes blocks BLK used in the SLC mode, which is the storage mode with the highest reliability. When required, a L2P address conversion table may be used to exchange physical addresses between blocks).
Claim 18 is the corresponding method claim to system claim 8. It is rejected with the same references and rationale.
Regarding claim 9, Wakutsu in view of Kirchner in further view of Kashyap teaches The memory system of claim 7, wherein the memory controller is further configured to: write the data buffered in the first block to a second block of the user space, wherein the second block is of a second level cell mode, (Wakutsu paragraph [0118], When the capacity of the first SLC/TLC buffer area 221 is greater than the second threshold value (S102: Yes), the processor 101 transcribes a part or all of the data in the first SLC/TLC buffer area 221 to the TLC user data area 222 by the first transcription process (S103). Then, the processor 101 assigns some blocks in the group of the blocks BLK constituting the first SLC/TLC buffer area 221 to the TLC user data area 222, thereby reducing the capacity of the first SLC/TLC buffer area 221 to the second threshold value (S104). The data can be transferred from the SLC buffer block to the TLC block in the user data area) and a number of bits stored in a memory cell of the second level cell mode is greater than a number of bits stored in a memory cell of the first level cell mode; (Wakutsu paragraph [0027], In general, according to at least one embodiment, a memory system is connectable to a host device. The memory system includes a non-volatile memory including a plurality of blocks and a controller electrically connected to the non-volatile memory. Each of the plurality of blocks includes a plurality of memory cells, and data can be written in a first mode and a second mode. The first mode is a mode in which data of a first number of bits is written in each memory cell. The second mode is a mode in which data of a second number of bits larger than the first number is written in each memory cell. The controller assigns a first plurality of blocks among the plurality of blocks to a first area. The number of bits per cell is greater in the second level cell mode) and after writing the data buffered in the first block to the second block, erase the first block (Wakutsu Fig. 5; see group of active blocks and group of free blocks, also see Wakutsu paragraph [0080], The active block may transition to a free block by the transcription process. The transcription process is a process of transcribing valid data stored in an active block to an open block and invalidating all data stored in the active block which is a transcription source. As a result, the active block which is the transcription source transitions to a free block. That is, the transcription process can be considered as a process of generating a free block. It should be noted that transcription may also be referred to as transfer, relocation, or move. After the data is written/moved (i.e. compacted) it may be transferred to the original location as a free block).
Response to Arguments
Applicant’s arguments, see pages 1-2 (numbered pages 7-8), filed December 11th, 2025, with respect to the rejection(s) of claim(s) 1, 12 and 20 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wakutsu et al. (US Publication No. 2024/0094923 -- "Wakutsu") in view of Kirchner (US Publication No. 2017/0052734 – “Kirchner”).
In response to the applicant’s amendments to independent claims 1, 12 and 20, the Kirchner reference has been added to disclose the details regarding the user space and hidden space of the memory device, as described in further detail above. In light of the newly added reference, the 35 USC 103 Rejection has been added.
Conclusion
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/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133