DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS's) submitted comply with the provisions of 37 CFR 1.97. Accordingly, the examiner has considered the information disclosure statement; please see attached forms PTO-1449.
Drawings
The drawings submitted have been reviewed and determined to facilitate understanding of the invention. The drawings are accepted as submitted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 describes, “a first doping region of the plurality of doping regions is positioned the first strip and the second strip,” at lines 5-6. As written, it is not possible to tell what relationship is claimed regarding the first doping region and the first and second strip.
Claims 18-20 depend from Claim 17 and fail to remedy the defect.
For examination purposes, the relevant portion of Claim 17 shall be considered to read, “a first doping region of the plurality of doping regions is positioned between the first strip and the second strip,” based on Applicant’s disclosure (see Applicant’s Fig 3 and Specification at [0046] and [0047]).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication 2002/0094186 to Wu (hereinafter “US1”).
Regarding Claim 1, US1 describes a photonic integrated circuit (see Figs 1A-3C and 8A-8F) comprising:
a substrate (16);
a first cladding layer (24B) supported by the substrate;
a waveguide layer (24A) positioned on the first cladding layer; and
a PIN phase shifter, wherein:
the waveguide layer shaped to define a rib waveguide (32), the rib waveguide comprising a strip (26) extending from a slab waveguide (defined by 34A and 34B);
the slab waveguide comprises a first set of doping regions (40) positioned on one or both sides of the strip (at 36B, 36C as shown in Figs 8A-8F;n see [0044, 0047]-[0048], [0070]);
the strip comprises a second set of doping regions (40 at 36A), such that the first set of doping regions has a different conductivity type than the second set of doping regions (see [0056]-[0061], [0070])); and
the PIN phase shifter comprises a PIN diode formed by the first set of doping regions, the second set of doping regions, and an undoped portion of the rib waveguide (see [0070]).
Regarding Claim 2, US1 describes the second set of doping regions extending at least partially through the strip from a top surface of the strip (see Figs 8A-8F).
Regarding Claim 3, US1 describes the second set of doping regions comprising a doping region that extends across an entire width of the strip (see Figs 8A-8F).
Regarding Claim 4, US1 describes the first set of doping regions comprising a first doping region positioned on a first side of the rib waveguide and a second doping region positioned on a second side of the rib waveguide (see Figs 8A-8F).
Regarding Claim 5, US1 describes each of the first set of doping regions forms an n-type region; and each of the second set of doping regions forms a p-type region (see [0070]).
Regarding Claim 17, US1 describes a photonic integrated circuit (see Figs 8A-8F and 9E-9F and [0076], describing a component with multiple waveguides each comprising an attenuator) comprising:
a first waveguide (12, see Figs 9E-9F) comprising a first strip that extends from a slab waveguide;
a second waveguide (12, see Figs 9E-9F) comprising a second strip that extends from the slab waveguide;
a plurality of doping regions (40 at 36B and/or 36C) positioned in the slab waveguide having a first conductivity type, wherein a first doping region of the plurality of doping regions is positioned between the first strip and the second strip (in a configuration where each of the waveguides of Fig 9 include an attenuator as described at [0076]);
a first set of doping regions (40 at 36A) positioned in the first strip and having a second conductivity type;
a second set of doping regions (40 at 36A in a configuration where each of the waveguides of Fig 9 include an attenuator as described at [0076]) positioned in the second strip and having the second conductivity type;
a first PIN phase shifter comprising a first PIN diode formed from an undoped portion of the first waveguide, the first set of doping regions, and the first doping region of the plurality of doping regions (see [0069]-[0073] and [0078-[0079]); and
a second PIN phase shifter comprising a second PIN diode formed from an undoped portion of the second waveguide, the second set of doping regions, and the first doping region of the plurality of doping regions (see [0069]-[0073] and [0078-[0079], where each of the waveguides of Fig 9 include an attenuator as described at [0076]).
Regarding Claim 18, US1 describes the plurality of doping regions comprising a second doping region (40 at 36B and/or 36C), wherein the first waveguide is positioned between the first doping region and the second doping region of the plurality of doping regions (where each of the waveguides of Fig 9 include an attenuator as described at [0076]).
Regarding Claim 19, US1 describes the plurality of doping regions comprises a third doping region (40 at the 36 located on the further side of the second waveguide shown in Figs 9E-9F where each of the waveguides of Fig 9 include an attenuator as described at [0076]), wherein the second waveguide is positioned between the first doping region and the third doping region of the plurality of doping regions.
Claims 1, 4, and 6-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Patent Application Publication 2023/0152662 to Doerr (hereinafter “US2”).
Regarding Claim 1, US2 describes a photonic integrated circuit (100, 200) comprising:
a substrate (206);
a first cladding layer (208) supported by the substrate;
a waveguide layer (210) positioned on the first cladding layer; and
a PIN phase shifter (see [0023]-[0024], [0031]), wherein:
the waveguide layer shaped to define a rib waveguide (202, 204), the rib waveguide comprising a strip extending from a slab waveguide (see Fig 2);
the slab waveguide comprises a first set of doping regions (40) positioned on one or both sides of the strip (238, 222, 240, 242);
the strip comprises a second set of doping regions (230, 232, 234, 236), such that the first set of doping regions has a different conductivity type than the second set of doping regions (see [0035]); and
the PIN phase shifter comprises a PIN diode formed by the first set of doping regions, the second set of doping regions, and an undoped portion of the rib waveguide (see [0031]).
Regarding Claim 4, US2 describes the first set of doping regions comprising a first doping region (238) positioned on a first side of the rib waveguide and a second doping region (240, 242) positioned on a second side of the rib waveguide (see Fig 2).
Regarding Claim 6, US2 describes a first set of conductive traces (114) electrically connecting the first set of doping regions to a control circuit (see Fig 1 and [0023]); and a second set of conductive traces (118) electrically connecting the second set of doping regions to the control circuit (see Fig 1 and [0027]).
Regarding Claim 7, US2 describes a set of conductive vias (216, 218, 228) electrically connecting the second set of doping regions to the second set of conductive traces.
Regarding Claim 8, US2 describes some or all of the set of conductive vias are positioned off-center with respect to the strip (see Fig 2).
Regarding Claim 9, US2 describes the set of conductive vias comprises a first conductive via (216) and a second conductive via (218 or 228); the first conductive and the second conductive via are positioned side-by-side along a width of the strip (see Figs 1-2).
Regarding Claim 10, US2 describes a barrier layer (portions identified as “p++” and “n++” as shown in Fig 2) electrically connecting the set of conductive vias and the second set of doping regions, wherein the barrier layer and conductive vias are formed from different materials (the vias as described as metal electrodes at [0032], while the p++ and n++ portions are part of a semiconductor diode, see [0031]-[0033]).
Regarding Claim 11, US2 describes the barrier layer having a smaller height than each of the set of conductive vias (see Fig 2).
Regarding Claim 12, US2 describes the barrier layer wider than each of the set of conductive vias (see Fig 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7, 10-12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US1 as applied to Claim 1 above, and further in view of US2
Regarding Claim 6, US1 describes that the doping regions may be electrically connected to conductors (38) for application of a potential between index changing elements (see [0043]). US1 does not describe conductive traces. US2 describes a photonic integrated (see above in relation to Claim 1). US2 further describes a first set of conductive traces (114) electrically connecting a first set of doping regions to a control circuit; and a second set of conductive traces (118) electrically connecting a second set of doping regions to the control circuit. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the electrode via, insulating layer, and conductive trace structure of US2 with the photonic integrated circuit of US1. The motivation for doing so would have been to allow for more efficient packaging and robust design.
Regarding Claim 7, US2 describes a set of conductive vias (216, 218, 228) electrically connecting the second set of doping regions to the second set of conductive traces.
Regarding Claim 10, US1 describes a barrier layer (36A) electrically connecting the set of conductive vias and the second set of doping regions, wherein the barrier layer and conductive vias are formed from different materials (see US1 at [0036] and US2 at [0032]).
Regarding Claim 11, the combination of US1 and US2 describes the barrier layer having a smaller height than each of the set of conductive vias (see US1 at Figs 8A-8F and US2 at Fig 2).
Regarding Claim 12, the combination of US1 and US2 describes the barrier layer wider than each of the set of conductive vias (see US1 at Figs 8A-8F and US2 at Fig 2).
Regarding Claim 20, US1 describes that the doping regions may be electrically connected to conductors (38) for application of a potential between index changing elements (see [0043]). US1 does not describe conductive traces or conductive vias. US2 describes a photonic integrated (see above in relation to Claim 1). US2 further describes a first set of conductive traces (114) electrically connecting a first set of doping regions to a control circuit; and a second set of conductive traces (118) electrically connecting a second set of doping regions to the control circuit, where each of the plurality of doping regions is electrically connected to the set of conductive traces via a corresponding set of conductive vias (216, 218, 228). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the electrode via, insulating layer, and conductive trace structure of US2 with the photonic integrated circuit of US1. The motivation for doing so would have been to allow for more efficient packaging and robust design.
Allowable Subject Matter
Claim 16 is allowed.
Claims 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-14 describe the second set of doping regions comprising a plurality of doping regions.
Claims 15 and 16 describe the strip comprising a first strip extending from the slab waveguide and a second strip extending from a top surface of the first strip.
These limitations represent subject matter not described or reasonably suggested, in conjunction with the further limitations of the present claims, by the prior art of record.
Conclusion
The prior art cited in the attached form PTO-892 are made of record and considered pertinent to applicant's disclosure. The cited prior art describes various photonic integrated circuits including rib waveguides and/or PIN phase shifters.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY RAHLL whose telephone number is (571)272-2356. The examiner can normally be reached M-F 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERRY RAHLL/Primary Examiner, Art Unit 2874