DETAILED ACTION
This action is responsive to the communication filed 14 July 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Group I embodiment in the reply filed on 14 July 2026 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Objections
Claims 3 and 15 are objected to because of the following informalities:
Claim 3 contains a typo and should read: “a spacer between the sidewall of the bit line and the filling pattern”;
Claim 15 contains a typo and should read: “the semiconductor device according to claim 11 [[2]]”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014)).
Regarding claim 4: Claim 4 recites the limitation "the third contacts.” There is insufficient antecedent basis for this limitation in the claim
Regarding claim 16: Claim 16 recites the limitation "the third contacts.” There is insufficient antecedent basis for this limitation in the claim.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication No. 2022/0085026 (published Mar. 17, 2022) (hereinafter “Kim”).
Regarding independent claim 1, Kim discloses: A semiconductor device comprising:
an active pattern array including active patterns (FIGS. 1/2, active patterns 105 forming an array, [0019]) on a substrate (FIGS. 1/2, substrate 100, [0016]);
a first contact on a central portion of each of the active patterns (FIGS. 1/2/9, conductive patterns 215/245 on a central portion of the active patterns 105, [0025]);
a bit line on the first contact (FIGS. 1/2, bit line structure 325, [0025]);
a second contact (FIGS. 1/2, lower contact plug 425, [0039]) on an end portion of each of the active patterns (FIGS. 1/2, depicting wherein the lower contact plug 425 is on an end portion of the active patterns 105);
a third contact on the second contact (FIGS. 1/2, upper contact plug 475 on the lower contact plug 425, [0039]);
a filling pattern between the bit line and the third contact (FIGS. 1/2, spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445 between the bit line structure 325 and the upper contact plug 475, [0035]), the filling pattern including a void therein (FIGS. 1/2, [0035]: “In some embodiments, the air spacer 397 may not include a liquid or solid material therein and may be a void or cavity”); and
a capacitor electrically connected to the third contact (FIGS. 1/2, capacitor 550 electrically connected to the upper contact plug 475, [0017]),
wherein
the active pattern array includes active pattern rows spaced apart from each other in a first direction parallel to an upper surface of the substrate (FIGS. 1/2, depicting wherein the active patterns 105 forming an array include rows spaced apart from each other in a first direction parallel to an upper surface of the substrate 100, e.g., a vertical direction),
each of the active pattern rows includes a plurality of active patterns spaced apart from each other in a second direction parallel to the upper surface of the substrate and orthogonal to the first direction (FIGS. 1/2, depicting wherein the rows of active patterns 105 include a plurality of active patterns 105 spaced apart from each other in a second direction parallel to the upper surface of the substrate 100 and orthogonal to the first direction, e.g., a horizontal direction),
each of the active patterns extends in a third direction forming an acute angle with the first direction and the second direction (FIGS. 1/2, depicting wherein the active patterns 105 extend in a third direction forming an acute angle with the vertical and horizontal directions), and
the plurality of active patterns in each row of the active pattern rows are aligned with each other in the second direction (FIGS. 1/2, depicting wherein the active patterns 105 are aligned with each other in the horizontal direction).
Regarding claim 2, Kim further discloses wherein the bit line extends in the first direction (FIGS. 1/2, depicting wherein the bit line structure 325 and the upper contact plug 475 extends in the vertical direction), and wherein the filling pattern is between a sidewall of the bit line that extends in the first direction and a sidewall of the third contact that extends in the first direction (FIGS. 1/2, depicting wherein the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445is disposed between sidewalls of the bit line structure 325 and the upper contact plug 475 extending in the vertical direction, shown in, e.g., cross-section A-A’).
Regarding claim 3, Kim further discloses a spacer between the sidewall the bit line and the filling pattern (FIGS. 1/2, e.g., spacer 385 between the sidewall of the bit line structure 325 and the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445, [0031]), the spacer including a nitride (FIGS. 1/2, [0035]: “In example embodiments, the first upper spacer 385 may include a material different from that of the first lower spacer 335, e.g., a nitride such as silicon nitride.”).
Regarding claim 4, Kim further discloses a fence pattern extending in the second direction on the substrate (FIGS. 1/2, insulating interlayer 500, [0017]), the fence pattern separating the third contacts from each other (FIGS. 1/2, depicting wherein the insulating interlayer 500 separates the upper contact plugs 375).
Regarding claim 5, Kim further discloses wherein the filling pattern includes an oxide (FIGS. 1/2/19/20, depicting wherein spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445 is formed from, e.g., silicon oxide; [0035]: “The fourth upper spacer 445 may include a nitride, e.g., silicon nitride, or an oxide, e.g., silicon oxide.”).
Regarding claim 6, Kim further discloses wherein the third contact includes a metal (FIGS. 1/2, [0046]: “The upper contact plug 475 may include a low resistance metal, e.g., tungsten, aluminum, copper, etc.”), and wherein the semiconductor device further comprises a barrier pattern covering a lower surface of the third contact (FIGS. 1/2, barrier layer 460 covering a lower surface of the upper contact plug 475, [0043]) and including a metal nitride (FIGS. 1/2, [0045]: “The barrier layer 460 may include a metal nitride, e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.”).
Regarding claim 7, Kim further discloses wherein the barrier pattern contacts a lower surface of the filling pattern (FIGS. 1/2, depicting wherein the barrier layer 460 contacts a lower surface of the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445, e.g., the lowest portion of the rightmost sidewall of the upper spacer 445).
Regarding claim 8, Kim further discloses wherein the barrier pattern contacts a lower sidewall of the filling pattern (FIGS. 1/2, depicting wherein the barrier layer 460 contacts a lower surface of the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445, e.g., the lowest portion of the rightmost sidewall of the upper spacer 445).
Regarding claim 9, Kim further discloses an ohmic contact pattern between the second contact and the barrier pattern (FIGS. 1/2, ohmic contact pattern 455, [0039]), the ohmic contact pattern including a metal silicide (FIGS. 1/2, [0042]: “The ohmic contact pattern 455 may include, e.g., cobalt silicide, nickel silicide, etc.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of U.S. Patent Publication No. 2019/0304982 (filed Apr. 2, 2018) (hereinafter “Sharma”).
Regarding claim 10, Kim does not specifically disclose a fourth contact contacting an upper surface of the third contact and an upper surface of the filling pattern, the fourth contact including a metal.
In the same field of endeavor, Sharma discloses a semiconductor device including a fourth contact (FIG. 3, landing pad 303a, [0021]) contacting an upper surface of a third contact (FIG. 3, landing pad contacts 307, [0021]), the fourth contact including a metal (FIG. 3, [0027]: “Referring to FIG. 4G, after one or more operations that result in the cross sections shown in FIG. 4F, the etch selective material at the bottom of the trenches formed between the bitline structures 421 a-421 d is removed to form vias. Thereafter, metal material is formed in the vias and on the top surfaces of the etch selective material. The metal material is then patterned to form capacitor landing pads 425 as shown in FIG. 4G.”). Regarding the landing pad configuration, in [0003], Sharma states: “Any misalignment in double patterning of these two features can result in shorting. Previous approaches to forming the bitline and capacitor via to have different heights are inadequate as they do not address patterning shorting risks.” Sharma further states in [0020]: “In the approach of FIG. 2, the capacitor via is formed using a separate mask that is aligned to the thin film transistor. In contrast, in embodiments of the instant disclosure, the capacitor via is formed using a self-aligned process. As such, the approach of embodiments is less complex and costly than the approach that is described with reference to FIG. 2. In addition to the shorting risks described above, the FIG. 2 approach yields memory cells that exhibit increased parasitic capacitance which can cause cross-talk and noise.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of Kim by adding the landing pad of Sharma in order to eliminate a risk of shorting and reduce cost and complexity of manufacturing. See Sharma [0003], [0020].
Moreover, addition of the landing pad of Sharma would result in a configuration wherein the landing pad, disposed on the upper contact plug 475 of Kim, would contact an upper surface of the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445.
Regarding independent claim 11, Kim discloses: A semiconductor device comprising:
an active pattern (FIGS. 1/2, active pattern 105, [0019]) on a substrate (FIGS. 1/2, substrate 100, [0016]);
a first contact on a central portion of the active pattern (FIGS. 1/2/9, conductive patterns 215/245 on a central portion of the active pattern 105, [0025]);
a bit line on the first contact (FIGS. 1/2, bit line structure 325, [0025]);
a second contact (FIGS. 1/2, lower contact plug 425, [0039]) on an end portion of the active pattern (FIGS. 1/2, depicting wherein the lower contact plug 425 is on an end portion of the active pattern 105);
a third contact on the second contact (FIGS. 1/2, upper contact plug 475 on the lower contact plug 425, [0039]);
a filling pattern between the bit line and the third contact (FIGS. 1/2, spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445 between the bit line structure 325 and the upper contact plug 475, [0035]), the filling pattern including a void therein (FIGS. 1/2, [0035]: “In some embodiments, the air spacer 397 may not include a liquid or solid material therein and may be a void or cavity”);
a barrier pattern on the second contact (FIGS. 1/2, barrier layer 460, [0043]), the barrier pattern covering a lower surface of the third contact and a lower surface of the filling pattern (FIGS. 1/2, barrier layer 460 covering a lower surface of the upper contact plug 475 and a lower surface of the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445); and a capacitor (FIGS. 1/2, capacitor 550, [0017]).
Kim does not specifically disclose a fourth contact contacting an upper surface of the third contact and an upper surface of the filling pattern; and wherein the capacitor is electrically connected to the fourth contact.
In the same field of endeavor, Sharma discloses a semiconductor device including a fourth contact (FIG. 3, landing pad 303a, [0021]) contacting an upper surface of a third contact (FIG. 3, landing pad contacts 307, [0021]). Regarding the landing pad configuration, in [0003], Sharma states: “Any misalignment in double patterning of these two features can result in shorting. Previous approaches to forming the bitline and capacitor via to have different heights are inadequate as they do not address patterning shorting risks.” Sharma further states in [0020]: “In the approach of FIG. 2, the capacitor via is formed using a separate mask that is aligned to the thin film transistor. In contrast, in embodiments of the instant disclosure, the capacitor via is formed using a self-aligned process. As such, the approach of embodiments is less complex and costly than the approach that is described with reference to FIG. 2. In addition to the shorting risks described above, the FIG. 2 approach yields memory cells that exhibit increased parasitic capacitance which can cause cross-talk and noise.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of Kim by adding the landing pad of Sharma in order to eliminate a risk of shorting and reduce cost and complexity of manufacturing. See Sharma [0003], [0020].
Moreover, addition of the landing pad of Sharma would result in a configuration wherein the landing pad, disposed on the upper contact plug 475 of Kim, would contact an upper surface of the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445, and the capacitor 550 is electrically connected to the landing pad.
Regarding claim 12, Kim in view of Sharma further discloses wherein an uppermost surface of the barrier pattern is higher than a lowermost surface of the third contact (FIGS. 1/2, depicting wherein an uppermost surface of the barrier layer 460 is higher than a lowermost surface of the upper contact plug 475).
Regarding claim 14, Kim in view of Sharma further discloses wherein the bit line extends in a first direction (FIGS. 1/2, depicting wherein the bit line structure 325 and the upper contact plug 475 extends in the vertical direction), and wherein the filling pattern is between a sidewall of the bit line that extends in the first direction and a sidewall of the third contact that extends in the first direction (FIGS. 1/2, depicting wherein the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445 is disposed between sidewalls of the bit line structure 325 and the upper contact plug 475 extending in the vertical direction, shown in, e.g., cross-section A-A’).
Regarding claim 15, Kim in view of Sharma further discloses a spacer between the sidewall of the bit line and the filling pattern (FIGS. 1/2, e.g., spacer 385 between the sidewall of the bit line structure 325 and the spacer configuration including air spacer 397, upper spacer 405, and upper spacer 445, [0031]), the spacer including a nitride (FIGS. 1/2, [0035]: “In example embodiments, the first upper spacer 385 may include a material different from that of the first lower spacer 335, e.g., a nitride such as silicon nitride.”).
Regarding claim 16, Kim in view of Sharma further discloses a fence pattern extending in a second direction on the substrate (FIGS. 1/2, insulating interlayer 500, [0017]), the fence pattern separating the third contacts from each other, the second direction being orthogonal to the first direction (FIGS. 1/2, depicting wherein the insulating interlayer 500 separates the upper contact plugs 375).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13: the cited prior art does not anticipate or make obvious wherein an uppermost surface of the barrier pattern is coplanar with a lowermost surface of the filling pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2015/0255466 (filed Oct. 3, 2014) (disclosing a semiconductor device containing a plurality of spacers and contacts); 2022/0181329 (published June 9, 2022) (disclosing a semiconductor device containing a plurality of spacers and contacts); 2022/0181326 (published June 9, 2022) (disclosing a landing pad contact configuration); .
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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