DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/29/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chong et al. [US 2021/0184010 A1], “Chong”.
Regarding claim 1, Chong disclose HEMT transistor (Fig. 23, 18) comprising:
a first semiconductor layer (120, ¶[0095]);
a gate (200) on a first face (as shown) of the first semiconductor layer (120);
a first passivating layer (410) of a first dielectric material (¶[0098] teaches Al2O3) which extends over the first face (as shown) of the first semiconductor layer (120), first and second sides of the gate (200), and at least a peripheral portion of a face of the gate opposite with respect to the first semiconductor layer along a first direction (as shown);
a gate metallization (300) on the gate (200), the first passivating layer (410) having a first sidewall abutting (as shown) the gate metallization (300);
a second passivating layer (430a +430b) of a second dielectric material (¶[0142] teaches SiO2) extends (as shown) between the face of the gate (200) and the first passivating layer (410), the first and second sides of the gate being free of the second passivating layer (as shown), the second passivating layer having a uniform thickness along the first direction in a first region between the first side of the gate and the gate metallization and a second region between the gate metallization and the second side of the gate (as shown),
wherein the second passivating layer (430a +430b) has a second sidewall abutting the gate metallization, the second sidewall being coplanar with the first sidewall of the first passivating layer (as shown),
wherein the gate metallization (300) has a first portion (310) extending through the first (410) and second passivating layers(430a and 430b) onto the gate (200) and a second portion (330) aligned with the first and second passivating layers along the first direction (as shown);
an insulating layer (420) between the second portion of the gate metallization (330) and the first (410) and second passivating (430a and 430b) layers along the first direction (as shown), the insulating layer having a third sidewall abutting the gate metallization (as shown), the third sidewall being coplanar with the first sidewall of the first passivating layer and the second sidewall of the second passivating layer (as shown).
Regarding claim 2, Chong discloses claim 1, Chong discloses the first semiconductor layer (Fig. 23, 120) is a gallium-nitride-based layer (¶[0095] teaches AlGaN).
Regarding claim 3, Chong discloses claim 2, Chong discloses the first semiconductor layer (Fig. 23, 120) is aluminum gallium nitride (¶[0095] teaches AlGaN).
Regarding claim 4, Chong discloses claim 1, Chong discloses the first passivating layer (Fig. 23, 410) is aluminum oxide (¶[0098] teaches Al2O3).
Regarding claim 7, Chong discloses claim 1, Chong discloses the second passivating layer (Fig. 23, 430a +430b) includes at least one of aluminum oxide and silicon dioxide (¶[0142] teaches SiO2).
Regarding claim 8, Chong discloses claim 1, Chong discloses a second semiconductor layer (Fig. 23, 110) that contacts a second face (as shown) of the first semiconductor layer (Fig. 120), on a second face opposite to the first face.
Regarding claim 9, Chong discloses claim 8, Chong discloses the second semiconductor layer (Fig. 23, 110) is gallium nitride (¶[0094]).
Regarding claim 10, Chong discloses claim 1, Chong discloses a source-contacting metallization (Fig. 23, 510) and a drain-contacting metallization (520), on either side of the gate (200), respectively.
Regarding claim 11, Chong discloses a method for manufacturing a HEMT transistor (Fig. 1-23, specifically Fig. 23), comprising:
forming a first semiconductor layer (Fig. 23, 110);
forming a gate (200) on a first face (as shown) of the first semiconductor layer (120);
forming a first passivating layer (410) of a first dielectric material (¶[0098] teaches Al2O3) which extends over the first face of the first semiconductor layer, sides of the gate and at least a peripheral portion of a face of the gate opposite with respect to the first semiconductor layer, the first passivating layer having a first sidewall (as shown);
forming a second passivating layer (430a +430b) of a second dielectric material (¶[0142] teaches SiO2) extending between the first face of the gate and the first passivating layer, the sides of the gate being free of the said second passivating layer, the second passivating layer having a second sidewall coplanar with the first sidewall of the first passivating layer (as shown);
forming an insulating layer (420) on the first passivating layer (410) and on the second passivating layer (430a +430b), the insulating layer having a third sidewall coplanar with the first sidewall of the first passivating layer and the second sidewall of the second passivating layer (as shown); and
forming a gate contact metallization (300) extending through the first and second passivating layers and the insulating layer along a first direction (as shown), the insulating layer (420) being directly between a portion of the gate contact metallization (300) and the first passivating layer (410) along the first direction (as shown).
Regarding claim 12, Chong discloses claim 11, Chong discloses locally etching through an etching mask, the insulating layer, the first passivating layer, and the second passivating layer (¶[0178] teaches the opening to the gate can be formed using an etching mask).
Regarding claim 13, Chong discloses a device (Fig. 23, 18), comprising:
a semiconductor stack (Fig. 23, substrate, 110 and 120, ¶[0109] and ¶[0095]), the semiconductor stack having a first face (as shown, top surface of layer 110);
a gate layer (200) being on top of the semiconductor stack on the first face, the gate layer having a second face (as shown, top surface of the gate), the second face opposite from the first face of the semiconductor stack along a first direction (as shown);
a first passivation layer (430a + 430b) on the second face (as shown) of the gate layer (200), the first passivation layer having a first surface on the gate layer (200) and a second surface opposite the first surface along the first direction (as shown), the first passivation layer having a uniform thickness between the first and second surfaces (as shown), the first passivation layer including a first gap on the gate layer (as shown) and first and second sidewalls on opposite sides of the first gap (as shown);
a second passivation layer (410) covering the first passivation layer (430a + 430b) and the first face of the semiconductor stack (110 and 120), the second passivation layer including a second gap aligned with the first gap and first and second sidewalls on opposite sides of the second gap, the first sidewall being coplanar with the first sidewall of the first passivation layer and the second sidewall being coplanar with the second sidewall of the second passivation layer (as shown in Fig. 23);
a gate contact metallization (300) extending through (as shown) the first and second gaps onto the gate layer (200), the gate contact metallization having a first surface coplanar with the first surface of the first passivation layer (as shown); and
an insulating layer (420) on the second passivation layer (410) over the first face of the semiconductor stack (110 and 120) and over the first passivation layer (430a + 430b), the insulating layer (420) being between (as shown) a portion (330) of the gate contact metallization (300) and the first (430a + 430b) and second passivation (410) layers along the first direction (as shown(, the insulating layer including a third gap and first and second sidewalls on opposite sides of the third gap, the first sidewall being coplanar with the first sidewalls of the first and second passivation layers and the second sidewall being coplanar with the second sidewalls of the first and second passivation layers (as shown).
Regarding claim 14, Chong discloses claim 13, Chong further discloses the first passivation layer (430a + 430b) and the second passivation (410) layer covers the second face except that of the first and second gaps (as shown in Fig. 23).
Regarding claim 15, Chong discloses claim 13, Chong further discloses the semiconductor stack (Fig. 23, substrate, 110 and 120) includes: a substrate (not shown (¶[0109])); a conductive layer (120) on top of the substrate (as shown); and a semiconductor layer (120) on top of the conductive layer, wherein the semiconductor stack is configured to form a two-dimensional electron gas (130, ¶[0111]) between the conductive layer (110) and the semiconductor layer (120).
Regarding claim 16, Chong discloses claim 15, Chong discloses the semiconductor layer (Fig. 23, 120) is made of aluminum-gallium nitride (¶[0095] teaches AlGaN).
Regarding claim 17, Chong discloses claim 16, Chong discloses the conductive layer (110) is of gallium nitride (¶[0094]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chong et al. [US 2021/0184010 A1], “Chong” as applied in claim 1 and further in view of Banerjee et al. [US 10,818,787 B1], “Banerjee”.
Regarding claim 5, Chong discloses claim 1, Chong does not disclose the second passivating layer (Fig. 23, 430a +430b) is nitride.
However, Banerjee discloses a HEMT device with a lower dielectric film (242) on the gate structure (Fig. 7, 124). The lower dielectric film (242) can include Si3N4, SiOKNi, where k<l, AlN, AlOrNs, where r<s, or another nitrogen-containing dielectric material suitable to produce a negatively charged film which can be utilized to improve the device quality (Col. 7 lines 5-35).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative dielectric material such as SiN as taught in Banerjee in the device of Chong because using a nitride dielectric with produce a negatively charged film which can be optimized to improve the sheet resistance of the device (Col. 7 lines 5-35 of Banerjee). Further, a suitable alternative material and the selection of a known material based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07).
Regarding claim 6, Chong as modified discloses claim 5, Chong as modified by Banerjee discloses the second passivating layer includes at least one of silicon nitride, silicon carbonitride, and aluminum nitride (the modification teaches SiN – see claim 5).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chong et al. [US 2021/0184010 A1], “Chong” as applied in claim 15 and further in view of Yang et al. [US 2022/0376100 A1], “Yang’00”.
Regarding claim 18, Chong discloses claim 15, Chong discloses the first passivation layer (430a +430b) is SiO2 (¶[0142]). Chong does not disclose the first passivation layer is of aluminum oxide.
However, Yang’00 discloses a HEMT device with the spacer (Fig. 5, 108c) may include a dielectric material, such as aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiN), silicon oxide (SiO2) (¶0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative material, aluminum oxide, as taught in Yang’00 in the device of Chong such that the first passivation layer is aluminum oxide because the dielectric material will provide protection of the gate material during the etching process (¶[0031] of Yang’00) . Further, the selection of a suitable alternative material and the selection of a known material based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07).
Regarding claim 19, Chong discloses claim 18, Chong discloses the second passivation layer (Fig. 23, 410) includes one of aluminum oxide and silicon dioxide (¶[0098] teaches Al2O3).
Regarding claim 20, Chong discloses claim 18, Chong discloses the second passivation layer includes one of silicon nitride, silicon carbonitride, and aluminum nitride (¶[0098] teaches SixNy).
Response to Arguments
Applicants’ arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection required by Applicant’s amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Coppens et al. [US 2022/0052163 A1] discloses a HEMT with a dielectric material may be included between edge portions of a HEMT gate and gate field plates in contact with a HEMT gate electrode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897
