DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Newly amended claim 1 recites the limitation “the second passivating layer having a uniform thickness along the first direction in a region between the first side of the gate and the gate” in lines 11-12, however, it is unclear how the second passivating layer can be “the sides of the gate being free of the said second passivating layer” yet the claim requires the second passivating layer to also be between the first side of the gate and the gate. As currently written the location of the second passivating layer is unclear. In an effort of compact prosecution the Examiner will interpret the language to mean, “the second passivating layer having a uniform thickness along the first direction in a first region between the first side of the gate and the gate metallization and a second region between the gate metallization and the second side of the gate.
Claim 1 recites the limitation "the sides of the gates" in line 10. There is insufficient antecedent basis for this limitation in the claim. The limitation should read, “ the first and second sides of the gate”.
Claims 2-10 are rejected by virtue of their dependency on claim 1.
Claim 13 recites the limitation "the passivation layer" in line 14-15. There is insufficient antecedent basis for this limitation in the claim.
Claims 14-20 are rejected by virtue of their dependency on claim 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chong et al. [US 2022/0310824 A1], “Chong”.
Regarding claim 11, Chong discloses a method for manufacturing a HEMT transistor (Fig. 1-14, 23), comprising:
forming a first semiconductor layer (Fig. 2, 120 and ¶[0095] teaches channel supply layer (120) can be AlGaN);
forming a gate (Fig. 2, 200) on a first face of the first semiconductor layer (120);
forming a first passivating layer (Fig. 3, 410) of a first dielectric material (¶[0098] teaches the first passivation film (410) may include at least one selected from the group consisting of SiO2, Al2O3, and SixNy) which extends over the first face of the first semiconductor layer, sides of the gate and at least a peripheral portion of a face of the gate opposite with respect to the first semiconductor layer (as shown in Fig. 3);
forming a second passivating layer (Fig. 11 with the result of Fig. 23 and , 430 a/b/432) of a second dielectric material (¶[0142] teaches the first passivation pattern 430a and the second passivation pattern 430b may include an oxide) extending between the first face of the gate and the first passivating layer, the sides of the gate being free of the said second passivating layer (as Fig. 11 and Fig. 12);
forming an insulating layer (Fig. 9, 420) on the first passivating layer (410) and on the second passivating layer (430 a/b/432); and
forming a gate contact metallization (Fig. 10, 302) extending through the first and second passivating layers and the insulating layer (as shown in the Fig. 23) along a first direction (as shown in Fig. 10), the insulating layer (420) being directly between a portion of the gate contact metallization (302) and the first passivating layer (410) along the first direction.
Regarding claim 12, Chong discloses claim 11, Chong future disclose
locally etching through an etching mask, the insulating layer, the first passivating layer and the second passivating layer (¶[0147] and ¶[0178] and ¶[0191]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 8, 9 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang [US 2022/0310824 A1] in view of Otake et al. [US 2022/0209001 A1],”Otake”.
Regarding claim 1, Yang discloses a HEMT transistor (see Fig. 13) comprising:
a first semiconductor layer (206 and ¶[0016] teaches the material of the barrier layer may include aluminum gallium nitride (AlGaN));
a gate (208) on a first face of the first semiconductor layer (206);
a first passivating layer (226 and ¶0023] teaches the material of the insulation layer may include aluminum oxide (Al2O3)) of a first dielectric material which extends over the first face of the first semiconductor layer, first (left side of gate) and second (right side of gate) sides of the gate, and at least a peripheral portion of a face of the gate opposite with respect to the first semiconductor layer (as shown) along a first direction (from left to right);
a gate metallization (232) on the gate (208):
a second passivating layer (224) of a second dielectric material (claim 3 teaches SiN) extends between the said face of the gate and the first passivating layer, the sides of the gate being free of the said second passivating layer (as shown), the second passivating layer having a thickness along the first direction in a region between the first side of the gate and the gate (as shown);
wherein the gate metallization (232) has a first portion (lower portion) extending through the first (226) and second passivating (224) layers onto the gate (208) and a second portion (upper portion) aligned with the first (226) and second (224) passivating layers along the first direction; and
an insulating layer (228) between the second portion (upper portion) of the gate metallization (232) and the first (226) and second (224) passivating layers along the first direction (as shown).
Yang does not disclose the second passivating layer having a uniform thickness along the first direction in a region between the first side of the gate and the gate.
However, Otake discloses semiconductor device with first dielectric films (24 ) on the upper surface of the gate structure (Fig. 1, 211). The dielectric films (24) has a uniform thickness in the first direction. Managing the shape and thickness of the dielectric films helps to suppress the gate leak current from the gate electrode (¶[0070]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a dielectric layer with a uniform thickness as taught by Otake in the device of Yang such that the second passivating layer having a uniform thickness along the first direction because managing the shape and thickness of the dielectric films helps to suppress the gate leak current from the gate electrode (¶[0070]). Further, change in shape has been held a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed device was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP 2144.04).
Regarding claim 2, Yang as modified disclose claim 1, Yang further discloses the first semiconductor layer (Fig. 13, 206) is a gallium-nitride-based layer (¶[0016] teaches the material of the barrier layer may include aluminum gallium nitride (AlGaN)).
Regarding claim 3, Yang as modified disclose claim 1, Yang further discloses the first semiconductor layer (Fig. 13, 206) is aluminum gallium nitride (¶[0016] teaches the material of the barrier layer may include aluminum gallium nitride (AlGaN)).
Regarding claim 4, Yang as modified disclose claim 1, Yang further discloses the first passivating layer (Fig. 13, 226) is aluminum oxide (¶0023] teaches the material of the insulation layer may include aluminum oxide (Al2O3))
Regarding claim 5, Yang as modified disclose claim 1, Yang further discloses the second passivating layer (Fig. 13, 224) is nitride (claim 3 teaches SiN).
Regarding claim 6, Yang as modified disclose claim 5, Yang further discloses second passivating layer (Fig. 13, 224) includes at least one of silicon nitride, silicon carbonitride, and aluminum nitride (claim 3 teaches SiN).
Regarding claim 8, Yang as modified disclose claim 1, Yang further discloses a second semiconductor layer (Fig. 13, 204) that contacts a second face of the first semiconductor layer (206), on a second face opposite to the first face (as shown).
Regarding claim 9, Yang as modified disclose claim 8, Yang further discloses the second semiconductor layer (204) is gallium nitride (¶[0016] teaches material of the channel layer may include gallium nitride (GaN)).
Regarding claim 13, Yang disclose a device (see Fig. 13), comprising:
a semiconductor stack (206/204), the semiconductor stack having a first face (as shown);
a gate layer (208) being on top of the semiconductor stack (206/204) on the first face, the gate layer having a second face, the second face opposite from the first face of the semiconductor stack (as shown) along a first direction;
a first passivation layer (224 and claim 3 teaches SiN) on the second face of the gate layer (as shown), the first passivation layer having a first surface on the gate layer (as shown) and a second surface opposite the first surface along the first direction, the first passivation layer having a thickness between the first and second surfaces, the first passivation layer including a first gap on the gate layer ( as shown in Fig. 13).
a second passivation layer (226 and ¶0023] teaches the material of the insulation layer may include aluminum oxide (Al2O3)) covering the first passivation layer and the first face of the semiconductor stack, the second passivation layer including a second gap aligned with the first gap (as shown);
a gate contact metallization (232) extending through (as shown) the first and second gaps onto the gate layer (208), the gate contact metallization having a first surface coplanar with the first surface of the passivation layer (as shown); and
an insulating layer (228) on the second passivation layer (226) over the first face of the semiconductor stack and over the first passivation layer (224), the insulating layer being between a portion of the gate contact metallization and the first and second passivation layers along the first direction (as shown).
Yang does not disclose the first passivation layer having a uniform thickness between the first and second surfaces.
However, Otake discloses semiconductor device with first dielectric films (24 ) on the upper surface of the gate structure (Fig. 1, 211). The dielectric films (24) has a uniform thickness in the first direction. Managing the shape and thickness of the dielectric films helps to suppress the gate leak current from the gate electrode (¶[0070]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a dielectric layer with a uniform thickness as taught by Otake in the device of Yang such that the second passivating layer having a uniform thickness along the first direction because managing the shape and thickness of the dielectric films helps to suppress the gate leak current from the gate electrode (¶[0070]). Further, change in shape has been held a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed device was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP 2144.04).
Regarding claim 14, Yang as modified disclose claim 13, Yang discloses the first passivation layer (224) and the second passivation layer (226) cover the second face except that of the first and second gaps (as shown).
Regarding claim 15, Yang as modified disclose claim 13, Yang discloses a substrate (202); a conductive layer on top of the substrate (204); and a semiconductor layer (206) on top of the conductive layer (204), wherein the semiconductor stack is configured to form a two-dimensional electron gas (209 and ¶[0028]) between the conductive layer (204) and the semiconductor layer (206).
Regarding claim 16, Yang as modified disclose claim 15, Yang discloses the semiconductor layer (Fig. 13, 206) is made of aluminum-gallium nitride (¶[0016] teaches the material of the barrier layer may include aluminum gallium nitride (AlGaN));
Regarding claim 17, Yang as modified disclose claim 16, Yang discloses the conductive layer (Fig. 13, 204) is of gallium nitride (¶[0016] teaches material of the channel layer may include gallium nitride (GaN)).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang [US 2022/0310824 A1] and Otake et al. [US 2022/0209001 A1],”Otake” as applied to claim 1 above, and further in view of Jones et al. [US 2021/0111254 A1], “Jones”.
Regarding claim 7, Yang as modified disclose claim 1, and the spacer can be SiN (claim 3 teaches SiN). Yang does not explicitly disclose the second passivating layer includes at least one of aluminum oxide and silicon dioxide.
However, Jones discloses the spacer layers (Fig. 1, 26, 27, 28) of the spacer insulator layer may be dielectric material, such as silicon nitride, aluminum nitride, silicon dioxide, and/or other suitable material (¶[0072]). The sidewall spacers (25s) may likewise be a dielectric or other insulator layer (e.g., a silicon nitride or silicon oxide layer) (¶0075]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative material, silicon dioxide, as taught in Jones in the device of Yang as modified such that the second passivating layer is silicon dioxide because the dielectric material will provide the isolation between the source/drain and gate. Further, the selection of a suitable alternative material and the selection of a known material based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang [US 2022/0310824 A1] and Otake et al. [US 2022/0209001 A1],”Otake” as applied to claim 1 above, and further in view of Chong et al. [US 2021/0184010 A1], “Chong”.
Regarding claim 10, Yang as modified disclose claim 1, Yang does not disclose a source-contacting metallization and a drain-contacting metallization, on either side of the gate, respectively.
However, Chong discloses a HEMT semiconductor device (Fig. 11, 10) may include a channel layer (110), a channel supply layer (120), a channel separation pattern (200), a first passivation film (410), a conductive material gate pattern (300), a second passivation film (420), a source electrode pattern (510), a drain electrode pattern (520), an additional electric-field relaxation film (610), and a first auxiliary drain electrode pattern (700).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a source-contacting metallization and a drain-contacting metallization, on either side of the gate as taught in Chong in the device of Yang as modified because forming the source and drain contacts allows for electrical contacts to be made to HEMT device in order to improve the electrical characteristics of the semiconductor device (¶[0107] of Chong).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang [US 2022/0310824 A1] in view of Otake et al. [US 2022/0209001 A1],”Otake” as applied to claim 15 above, and further in view of Yang et al. [US 2022/0376100 A1], “Yang’00”.
Regarding claim 18, Yang as modified disclose claim 15, Yang discloses the first passivation layer is SiN not aluminum oxide.
However, a HEMT device with the spacer (Fig. 5, 108c) may include a dielectric material, such as aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiN), silicon oxide (SiO2) (¶0031]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative material, aluminum oxide, as taught in Jones in the device of Yang as modified such that the first passivation layer is aluminum oxide because the dielectric material will provide protection of the gate material during the etching process (¶[0031] of Yang’00) . Further, the selection of a suitable alternative material and the selection of a known material based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07).
Regarding claim 19, Yang as modified disclose claim 18, Yang discloses the second passivation layer (Fig. 13, 226) includes one of aluminum oxide and silicon dioxide (¶0023] teaches the material of the insulation layer may include aluminum oxide (Al2O3)).
Regarding claim 20, Yang as modified disclose claim 18, Yang discloses the second passivation layer (226) includes one of silicon nitride, silicon carbonitride, and aluminum nitride (¶[0023] teaches The insulating (126) include a dielectric material, such as aluminum nitride (AlN)).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection required by Applicant’s amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Coppens et al. [US 2022/0052163 A1] discloses a HEMT with a dielectric material may be included between edge portions of a HEMT gate and gate field plates in contact with a HEMT gate electrode.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/P.M.R/Examiner, Art Unit 2897
/MARK W TORNOW/Primary Examiner, Art Unit 2891
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