Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 3/5/2026 in response to the Office action dated 12/5/2025. Claims 1, 2, 4, 10-11, 13, 19, and 20 have been amended. Claims 5 and 14 have been cancelled. New claims 21-22 have been added. Claims 1-4, 6-13, and 15-22 are pending in this application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention
Claims 1-4, 9-13, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lam et al. (US 20210342267 A1), hereinafter Lam.
Regarding claim 1, Lam teaches an apparatus, comprising: one or more controllers associated with a memory system (Paragraph 40; Fig. 1, memory subsystem controller 115),
wherein the one or more controllers are configured to cause the apparatus to: store data associated with each write command of a plurality of write commands to a cache of the memory system (Paragraphs 48, 53-54, 70, 72; Figs. 1A, 1B and 4, write metadata [data] is stored (in response to write requests from a host 120) in zone map journal data structure 166A and zone map data structure 201, which are mapping structures 126 located within tightly coupled memory (TCM) 160 [cache]);
write a subset of the data stored to the cache to a non-volatile memory of the memory system based at least in part on storing the data associated with each of the plurality of write commands to the cache (Paragraph 70; Fig. 4, flushing [writing] only zone map journal data structure 201 (subset of zone map journal data structure 166A and zone map data structure 201) from TCM 160 [cache] to a non-volatile memory device),
wherein each respective data of the subset of the data is associated with a respective identifier, of a plurality of identifiers, that is sequentially assigned based at least in part on writing the respective data to the non-volatile memory (Paragraphs 81, 84-85, last written page LWP values [identifiers] are created based on writing pages [respective data] to the non-volatile memory device and are stored in order in the non-volatile memory device));
transition power states, by the memory system, based at least in part on writing the subset of the data to the non-volatile memory (Paragraph 70; Fig. 4, flushing [writing] zone map data structure 201 to a non-volatile memory device in response to an asynchronous power loss (APL));
determine, after transitioning power states, whether the subset of the data was written to the non-volatile memory based at least in part on the plurality of identifiers (Paragraphs 106, 109; Fig. 8, operation 815, verifying [determining] that zone map data structure 201 was successfully recovered [written to non-volatile memory] based on the index values [identifiers] following an APL);
and write the subset of the data stored to the non-volatile memory to the cache based at least in part on determining that the subset of the data was written to the non-volatile memory (Paragraph 100-101; Fig. 7, operation 705, writing mapping data structures 126 [including the subset] back from nonvolatile memory to the TCM 160 [cache] after a power loss).
Regarding claim 2, Lam teaches the apparatus of claim 1, wherein a second subset of the data stored to the cache is associated with a second plurality of identifiers (Paragraph 72; Fig. 4, element 201, zone write data [second subset] is associated with metadata including zone write pointers [identifiers]),
and the one or more controllers are further configured to cause the apparatus to: determine, after transitioning power states (Paragraph 106; Fig. 8, reboot process in response to an asynchronous power loss (APL)),
that the second subset of the data was not written to the non-volatile memory based at least in part on a first identifier of the second plurality of identifiers associated with the second subset of the data (Paragraph 110, Fig. 8, operation 825, write pointers [identifiers] of the data are verified; a write pointer [first identifier] can be incorrect due to an incomplete write operation).
Regarding claim 3, Lam teaches the apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: receive, by the memory system, a command prior to transitioning power states (Paragraphs 68, 70, flush command is issued during an asynchronous power loss event prior to the memory system completely losing power);
and store an indication of the data written to the non-volatile memory based at least in part on receiving the command (Paragraph 69; Fig. 4, element 166A, journal data structure entry [indication] logs the flush transitions of metadata),
wherein the indication is based at least in part on a second identifier of the plurality of identifiers (Paragraph 69; Fig. 3, journal data structure includes an index value [identifier] for each entry),
and wherein determining that the subset of the data was written to the non-volatile memory is based at least in part on storing the indication (Paragraphs 75-76; Fig. 4, utilizing zone map journal data structure 166A to verify written data [subset] by comparing associated write pointers).
Regarding claim 4, Lam teaches the apparatus of claim 3, wherein the second identifier is associated with a last portion of the subset of the data that was written to the non-volatile memory (Paragraph 105; Fig. 7, operation 745, last journal entry [subset of data] is marked with a last version marker [identifier]).
Regarding claim 9, Lam teaches the apparatus of claim 1, wherein transitioning power states is configured to cause the apparatus to: transition, by the memory system, from a first power state to a second power state (Paragraph 21, memory device is operational [first power state] then loses power, triggering an asynchronous power loss (APL) [second power state]);
and transition, by the memory system, from the second power state to the first power state (Paragraph 100; Fig. 7, controller 115 performs recovery after a reboot [first power state] from an asynchronous power loss (APL) [second power state]).
Regarding claim 10, this is a computer readable medium version of the claimed apparatus discussed above (claim 1, respectively), in which Lam also teaches a non-transitory computer-readable medium (Paragraph 119; Fig. 9, machine-readable storage medium 924)
storing code comprising instructions (Paragraph 119; Fig. 9, instructions 926)
which are executed by a processor (Paragraph 119; Fig. 9, processing device 902). The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Regarding claim 11, this is a computer readable medium version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Regarding claim 12, this is a computer readable medium version of the claimed apparatus discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Regarding claim 13, this is a computer readable medium version of the claimed apparatus discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Regarding claim 18, this is a computer readable medium version of the claimed apparatus discussed above (claim 9, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Regarding claim 19, this is a method version of the claimed apparatus discussed above (claim 1, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Regarding claim 20, this is a method version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also anticipated by Lam.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Solihin et al. (US 20200081802 A1), hereinafter Solihin.
Regarding claim 6, Lam teaches the apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: store data associated with each write command of a plurality of second write commands to the cache (Paragraphs 47-48, 53-54; Figs. 1A, 1B, write metadata [data] is stored in a high frequency update table 162 located within tightly coupled memory (TCM) 160 [cache] in response to write requests from a host 120).
Lam does not explicitly teach to receive, by the memory system, a first type of command based at least in part on storing the data associated with each write command of the plurality of second write commands to the cache; maintain, for a first duration, the data in the cache based at least in part on receiving the first type of command; and write, after the first duration, the data to the non-volatile memory.
However, Solihin teaches to receive, by the memory system, a first type of command based at least in part on storing the data associated with each write command of the plurality of second write commands to the cache (Paragraphs 13-14, 73-74; Figs. 5A-5B, checksum calculation [first type of command] is added to the memory system as part of a Lazy Persistency implementation which creates metadata associated with written data in a region [interpreted as region of a cache since is data is transferred out via natural cache evictions]);
maintain, for a first duration, the data in the cache based at least in part on receiving the first type of command (Paragraph 105, with Lazy Persistency implementation, a dirty data block is held in the LLC [cache] for a max duration [maxvdur] of 101% of time compared to a base system)
and write, after the first duration, the data to the non-volatile memory (Paragraphs 6 and 105, dirty data block is evicted and written back to non-volatile main memory [NVMM] after the volatility duration [maxvdur] has elapsed).
Lam and Solihin are analogous art because they are in the same field of endeavor, that being writing/recovering cache data to/from non-volatile memory. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam to further include the maintaining data in the cache for a first duration according to the teachings of Solihin. The motivation for doing so would have been to achieve faster execution at the cost of slower recovery (Solihin, Paragraph 75).
Regarding claim 7, Lam teaches the apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: store data associated with each write command of a plurality of third write commands to the cache (Paragraphs 48, 53-54; Figs. 1A, 1B, write metadata [data] is stored in a high frequency update table 162 located within TCM 160 [cache] in response to write requests from a host 120).
Lam does not explicitly teach to receive, by the memory system, a second type of command based at least in part on storing the data associated with each write command of the plurality of third write commands to the cache; maintain, for a second duration, the data in the cache based at least in part on receiving the second type of command; and write, after the second duration, the data to the non-volatile memory.
However, Solihin teaches to receive, by the memory system, a second type of command based at least in part on storing the data associated with each write command of the plurality of third write commands to the cache (Paragraphs 24, 67 and 71; Fig. 2, a durable transaction [second type of command] issued to a memory system as part of an Eager Persistency implementation consists of explicitly flushing data in cache lines);
maintain, for a second duration, the data in the cache based at least in part on receiving the second type of command (Paragraph 105, with Eager Persistency implementation, a dirty data block is held in the LLC [cache] for a max duration [maxvdur] of 20% of time compared to a base system)
and write, after the second duration, the data to the non-volatile memory (Paragraphs 6 and 105, dirty data block is evicted and written back to non-volatile main memory [NVMM] after the volatility duration [maxvdur] has elapsed).
Lam and Solihin are analogous art because they are in the same field of endeavor, that being responding to cache failure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam to further include the maintaining data in the cache for a second duration according to the teachings of Solihin. The motivation for doing so would have been to achieve faster recovery at the cost of slower execution (Solihin, Paragraph 75).
Regarding claim 15, this is a computer readable medium version of the claimed apparatus discussed above (claim 6, respectively), in which Lam in view of Solihin also teaches a non-transitory computer-readable medium (Lam, Paragraph 119; Fig. 9, machine-readable storage medium 924)
storing code comprising instructions (Lam, Paragraph 119; Fig. 9, instructions 926)
which are executed by a processor (Lam, Paragraph 119; Fig. 9, processing device 902). The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Solihin.
Regarding claim 16, this is a computer readable medium version of the claimed apparatus discussed above (claim 7, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Solihin.
Claims 8, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Kazemi et al. (US 20160110251 A1), hereinafter Kazemi.
Regarding claim 8, Lam teaches the apparatus of claim 1, but does not explicitly teach wherein the one or more controllers are configured to store the data to the cache while the memory system is operating in a first mode, and the one or more controllers are further configured to cause the apparatus to: receive, from a host system, a command to enter the first mode of operation; transition, by the memory system, from a second mode of operation to the first mode of operation; and transmit, to the host system, an indication that the memory system has transitioned from the second mode of operation to the first mode of operation.
However, Kazemi teaches wherein the one or more controllers (Paragraph 24; Fig. 1, memory device controller 70 controls operations of cache device 60) are configured to store the data to the cache while the memory system is operating in a first mode (Paragraphs 20, 24-25; Fig. 1, in cached mode [first mode], I/O requests are directed to solid state memory 80 within cache device 60),
and the one or more controllers are further configured to cause the apparatus to: receive, from a host system, a command to enter the first mode of operation (Paragraph 58; Figs. 1 and 6, stage 614, cache management software 30 in host 10 sets the cache mode to cached);
transition, by the memory system, from a second mode of operation to the first mode of operation (Paragraph 58; Fig. 6, stage 614, cache management software sets the cache mode from uncached [second mode] to cached [first mode]; afterwards, I/O requests are then directed to the cache device [memory system]);
and transmit, to the host system, an indication that the memory system has transitioned from the second mode of operation to the first mode of operation (Paragraph 41; Figs. 1 and 3, I/O redirection module 330 [assumed to be a part of caching software 30 within host 10 under its broadest reasonable interpretation] is notified when the memory device status has changed from uncached [second mode] to cached [first mode]).
Lam and Kazemi are analogous art because they are in the same field of endeavor, that being responding to cache failure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam to further include the two modes of operation according to the teachings of Kazemi. The motivation for doing so would have been to continue caching operations without disruption in response to a device failure (Kazemi, Paragraph 51).
Regarding claim 17, this is a computer readable medium version of the claimed apparatus discussed above (claim 8, respectively), in which Lam in view of Kazemi also teaches a non-transitory computer-readable medium (Lam, Paragraph 119; Fig. 9, machine-readable storage medium 924)
storing code comprising instructions (Lam, Paragraph 119; Fig. 9, instructions 926)
which are executed by a processor (Lam, Paragraph 119; Fig. 9, processing device 902). The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Kazemi.
Regarding claim 21, Lam in view of Kazemi teaches the apparatus of claim 8, wherein, in the second mode of operation, the memory system determines whether to delay performance of a synchronize cache command received from the host system or delay performance of a force unit access command received from the host system (Paragraph 30; Fig. 2A, in uncached [second] mode, caching software 30 may fail and retry [delay performance of] I/O requests [access commands] from host 10).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Kanai et al. (US 20160283157 A1), hereinafter Kanai.
Regarding claim 22, Lam teaches the apparatus of claim 1, the one or more controllers (Paragraph 40; Fig. 1, memory subsystem controller 115),
and the plurality of identifiers (Paragraph 81, LWP values).
Lam does not explicitly teach wherein the one or more controllers are further configured to cause the apparatus to: identify that first data, associated with an identifier having a next sequential value after the plurality of identifiers, is unrecovered, wherein second data associated with any identifier beyond the identifier is considered invalid.
However, Kanai teaches wherein the one or more controllers are further configured to cause the apparatus to: identify that first data, associated with an identifier having a next sequential value after the plurality of identifiers, is unrecovered, wherein second data associated with any identifier beyond the identifier is considered invalid (Paragraph 87; Fig. 1, the memory controller 13 only starts write-back of data having the next epoch number [identifier] only when data with the current epoch number is successfully written-back (i.e. if data with the next epoch number is not successfully written-back [unrecovered], then data with subsequent epoch numbers are not written-back [considered invalid]).
Lam and Kanai are analogous art because they are in the same field of endeavor, that being data recovery. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam to further include the identifier recovery method according to the teachings of Kanai. The motivation for doing so would have been to ensure reliable write-backs (Kanai, Paragraph 87).
Response to Arguments
Applicant’s arguments (see pages 9-12 of the remarks) filed 3/5/2026, with respect to the rejections of claims 1-5, 9-14, and 18-20 under 35 U.S.C 102 have been fully considered, but are not persuasive.
Regarding claims 1, 10, and 19, the Applicant argues that Lam does not disclose the features: “wherein each respective data of the subset of the data is associated with a respective identifier, of a plurality of identifiers, that is sequentially assigned based at least in part on writing the respective data to the non-volatile memory” (emphasis added).
However, Lam teaches storing the last written page in non-volatile memory (Paragraph 81; Fig. 4, write tracker table 162B stores last written page LWP values in the NVM device), which keeps track of the sequence in which pages are written to the non-volatile memory (Paragraphs 84-85; Fig. 1, controller 115 verifies the write sequence of data using the order of the LWP values).
The Examiner argues that the newly cited areas of the Lam reference teach the amendments to claims 1, 10, and 19, and further notes any other arguments with respect to claims 1, 10, and 19 are consummate in scope with the argument above. Thus, the Examiner maintains the rejections set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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