Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/26/2026 has been entered.
Response to Amendment
This Office action is in response to Applicant' s communication filed 6/26/2026 in response to the Office action dated 3/27/2026. Claims 1-3, 10-12, and 19-20 have been amended. Claim 22 has been cancelled. New claim 23 has been added. Claims 1-4, 6-13, 15-21, and 23 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-13, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lam et al. (US 20210342267 A1), hereinafter Lam, in view of Dantkale et al. (US 20180284995 A1), hereinafter Dantkale.
Regarding claim 1, Lam teaches an apparatus, comprising: one or more controllers associated with a memory system (Paragraph 40; Fig. 1, memory subsystem controller 115),
wherein the one or more controllers are configured to cause the apparatus to: store data associated with each write command of a plurality of write commands to a cache of the memory system (Paragraphs 48, 53-54, 70, 72; Figs. 1A, 1B and 4, write metadata [data] is stored (in response to write requests from a host 120) in zone map journal data structure 166A and zone map data structure 201, which are mapping structures 126 located within tightly coupled memory (TCM) 160 [cache]);
write a subset of the data stored to the cache to a non-volatile memory of the memory system based at least in part on storing the data associated with each of the plurality of write commands to the cache (Paragraph 70; Fig. 4, flushing [writing] only zone map journal data structure 201 (subset of zone map journal data structure 166A and zone map data structure 201) from TCM 160 [cache] to a non-volatile memory device),
wherein each respective data of the subset of the data is associated with a respective consecutive identifier, of a plurality of identifiers, based at least in part on writing the respective data to the non-volatile memory (Paragraphs 67, 78, 81, 84-85; Figs. 3-4, last written page LWP values [identifiers] are created based on writing pages [respective data] to the non-volatile memory device and are stored in [consecutive] HFUT 362 entries Entry_0-Entry_N in the non-volatile memory device));
transition power states, by the memory system, based at least in part on writing the subset of the data to the non-volatile memory (Paragraph 70; Fig. 4, flushing [writing] zone map data structure 201 to a non-volatile memory device in response to an asynchronous power loss (APL));
determine, based at least in part on transitioning power states, whether the data is recoverable (Paragraphs 100, 102, 104; Fig. 7, operations 710, 725, determining whether journal data structure 166 is available to recover mapping data structures following an APL);
and write the subset of the data stored to the non-volatile memory to the cache based at least in part on determining that the subset of the data is recoverable (Paragraphs 101, 104; Fig. 7, operation 740, upon determining that journal data structure 166 is available [recoverable], writing mapping data structure 126 [subset of data] from the NVM device back to TCM 160 [cache]).
Lam does not explicitly teach wherein the subset of the data is recoverable and first data, associated with a first identifier having a next value after the respective consecutive identifiers associated with the subset of the data, is unrecoverable, and wherein data associated with any identifier beyond the first identifier is invalid based at least in part on the first data being unrecoverable.
However, Dantkale teaches wherein the subset of the data is recoverable and first data, associated with a first identifier having a next value after the respective consecutive identifiers associated with the subset of the data, is unrecoverable (Paragraphs 97-98, 121, 126-127; Fig. 5, replaying [recovering] updates to cache entries [subset of the data], such as consecutive cache entries 510A-B, where cache entries after commit pointer 510, such as cache entries 510C-F, are not replayed [unrecoverable]), and
wherein data associated with any identifier beyond the first identifier is invalid based at least in part on the first data being unrecoverable (Paragraph 127, cache entries after the commit pointer are considered invalid and are not replayed [unrecoverable]).
Lam and Dantkale are analogous art because they are in the same field of endeavor, that being cache data recovery. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam to further include the data recovery method with respect to the identifiers according to the teachings of Dantkale. The motivation for doing so would have been to improve recovery by ensuring the memory system returns the correct version of recovered data (Dantkale, Paragraph 93).
Regarding claim 2, Lam in view of Dantkale teaches the apparatus of claim 1, wherein a second subset of the data stored to the cache is associated with a second plurality of identifiers (Lam, Paragraph 72; Fig. 4, element 201, zone write data [second subset] is associated with metadata including zone write pointers [identifiers]),
and the one or more controllers are further configured to cause the apparatus to: determine, after transitioning power states (Lam, Paragraph 106; Fig. 8, reboot process in response to an asynchronous power loss (APL)),
that the second subset of the data was not written to the non-volatile memory based at least in part on an identifier of the second plurality of identifiers associated with the second subset of the data (Lam, Paragraph 110, Fig. 8, operation 825, write pointers [identifiers] of the data are verified; a write pointer [identifier] can be incorrect due to an incomplete write operation).
Regarding claim 3, Lam in view of Dantkale teaches the apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: receive, by the memory system, a command prior to transitioning power states (Lam, Paragraphs 68, 70, flush command is issued during an asynchronous power loss event prior to the memory system completely losing power);
and store an indication of the data written to the non-volatile memory based at least in part on receiving the command (Lam, Paragraph 69; Fig. 4, element 166A, journal data structure entry [indication] logs the flush transitions of metadata),
wherein the indication is based at least in part on a second identifier of the plurality of identifiers (Lam, Paragraph 69; Fig. 3, journal data structure includes an index value [identifier] for each entry),
and wherein determining that the subset of the data is recoverable based at least in part on storing the indication (Lam, Paragraphs 100, 102, 104; Fig. 7, operations 710, 725, determining whether journal data structure 166 is available [indication is stored] in order to recover mapping data structures).
Regarding claim 4, Lam in view of Dantkale teaches the apparatus of claim 3, wherein the second identifier is associated with a last portion of the subset of the data that was written to the non-volatile memory (Lam, Paragraph 105; Fig. 7, operation 745, last journal entry [subset of data] is marked with a last version marker [identifier]).
Regarding claim 9, Lam in view of Dantkale teaches the apparatus of claim 1, wherein transitioning power states is configured to cause the apparatus to: transition, by the memory system, from a first power state to a second power state (Lam, Paragraph 21, memory device is operational [first power state] then loses power, triggering an asynchronous power loss (APL) [second power state]);
and transition, by the memory system, from the second power state to the first power state (Lam, Paragraph 100; Fig. 7, controller 115 performs recovery after a reboot [first power state] from an asynchronous power loss (APL) [second power state]).
Regarding claim 10, this is a computer readable medium version of the claimed apparatus discussed above (claim 1, respectively), in which Lam in view of Dantkale also teaches a non-transitory computer-readable medium (Lam, Paragraph 119; Fig. 9, machine-readable storage medium 924)
storing code comprising instructions (Lam, Paragraph 119; Fig. 9, instructions 926)
which are executed by a processor (Lam, Paragraph 119; Fig. 9, processing device 902). The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Regarding claim 11, this is a computer readable medium version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Regarding claim 12, this is a computer readable medium version of the claimed apparatus discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Regarding claim 13, this is a computer readable medium version of the claimed apparatus discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Regarding claim 18, this is a computer readable medium version of the claimed apparatus discussed above (claim 9, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Regarding claim 19, this is a method version of the claimed apparatus discussed above (claim 1, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Regarding claim 20, this is a method version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale.
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Dantkale as applied to claims 1 and 10 above, and further in view of Solihin et al. (US 20200081802 A1), hereinafter Solihin.
Regarding claim 6, Lam in view of Dantkale teaches the apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: store data associated with each write command of a plurality of second write commands to the cache (Lam, Paragraphs 47-48, 53-54; Figs. 1A, 1B, write metadata [data] is stored in a high frequency update table 162 located within tightly coupled memory (TCM) 160 [cache] in response to write requests from a host 120).
Lam in view of Dantkale does not explicitly teach to receive, by the memory system, a first type of command based at least in part on storing the data associated with each write command of the plurality of second write commands to the cache; maintain, for a first duration, the data in the cache based at least in part on receiving the first type of command; and write, after the first duration, the data to the non-volatile memory.
However, Solihin teaches to receive, by the memory system, a first type of command based at least in part on storing the data associated with each write command of the plurality of second write commands to the cache (Paragraphs 13-14, 73-74; Figs. 5A-5B, checksum calculation [first type of command] is added to the memory system as part of a Lazy Persistency implementation which creates metadata associated with written data in a region [interpreted as region of a cache since is data is transferred out via natural cache evictions]);
maintain, for a first duration, the data in the cache based at least in part on receiving the first type of command (Paragraph 105, with Lazy Persistency implementation, a dirty data block is held in the LLC [cache] for a max duration [maxvdur] of 101% of time compared to a base system)
and write, after the first duration, the data to the non-volatile memory (Paragraphs 6 and 105, dirty data block is evicted and written back to non-volatile main memory [NVMM] after the volatility duration [maxvdur] has elapsed).
Lam, Dantkale, and Solihin are analogous art because they are in the same field of endeavor, that being cache data recovery. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam in view of Dantkale to further include the maintaining data in the cache for a first duration according to the teachings of Solihin. The motivation for doing so would have been to achieve faster execution at the cost of slower recovery (Solihin, Paragraph 75).
Regarding claim 7, Lam in view of Dantkale teaches the apparatus of claim 1, wherein the one or more controllers are further configured to cause the apparatus to: store data associated with each write command of a plurality of third write commands to the cache (Lam, Paragraphs 48, 53-54; Figs. 1A, 1B, write metadata [data] is stored in a high frequency update table 162 located within TCM 160 [cache] in response to write requests from a host 120).
Lam in view of Dantkale does not explicitly teach to receive, by the memory system, a second type of command based at least in part on storing the data associated with each write command of the plurality of third write commands to the cache; maintain, for a second duration, the data in the cache based at least in part on receiving the second type of command; and write, after the second duration, the data to the non-volatile memory.
However, Solihin teaches to receive, by the memory system, a second type of command based at least in part on storing the data associated with each write command of the plurality of third write commands to the cache (Paragraphs 24, 67 and 71; Fig. 2, a durable transaction [second type of command] issued to a memory system as part of an Eager Persistency implementation consists of explicitly flushing data in cache lines);
maintain, for a second duration, the data in the cache based at least in part on receiving the second type of command (Paragraph 105, with Eager Persistency implementation, a dirty data block is held in the LLC [cache] for a max duration [maxvdur] of 20% of time compared to a base system)
and write, after the second duration, the data to the non-volatile memory (Paragraphs 6 and 105, dirty data block is evicted and written back to non-volatile main memory [NVMM] after the volatility duration [maxvdur] has elapsed).
Lam, Dantkale, and Solihin are analogous art because they are in the same field of endeavor, that being cache data recovery. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam in view of Dantkale to further include the maintaining data in the cache for a second duration according to the teachings of Solihin. The motivation for doing so would have been to achieve faster recovery at the cost of slower execution (Solihin, Paragraph 75).
Regarding claim 15, this is a computer readable medium version of the claimed apparatus discussed above (claim 6, respectively), in which Lam in view of Dantkale, further in view of Solihin also teaches a non-transitory computer-readable medium (Lam, Paragraph 119; Fig. 9, machine-readable storage medium 924)
storing code comprising instructions (Lam, Paragraph 119; Fig. 9, instructions 926)
which are executed by a processor (Lam, Paragraph 119; Fig. 9, processing device 902). The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale, further in view of Solihin.
Regarding claim 16, this is a computer readable medium version of the claimed apparatus discussed above (claim 7, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale, further in view of Solihin.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Dantkale as applied to claims 1 and 10 above, and further in view of Kazemi et al. (US 20160110251 A1), hereinafter Kazemi.
Regarding claim 8, Lam in view of Dantkale teaches the apparatus of claim 1, but does not explicitly teach wherein the one or more controllers are configured to store the data to the cache while the memory system is operating in a first mode, and the one or more controllers are further configured to cause the apparatus to: receive, from a host system, a command to enter the first mode of operation; transition, by the memory system, from a second mode of operation to the first mode of operation; and transmit, to the host system, an indication that the memory system has transitioned from the second mode of operation to the first mode of operation.
However, Kazemi teaches wherein the one or more controllers (Paragraph 24; Fig. 1, memory device controller 70 controls operations of cache device 60) are configured to store the data to the cache while the memory system is operating in a first mode (Paragraphs 20, 24-25; Fig. 1, in cached mode [first mode], I/O requests are directed to solid state memory 80 within cache device 60),
and the one or more controllers are further configured to cause the apparatus to: receive, from a host system, a command to enter the first mode of operation (Paragraph 58; Figs. 1 and 6, stage 614, cache management software 30 in host 10 sets the cache mode to cached);
transition, by the memory system, from a second mode of operation to the first mode of operation (Paragraph 58; Fig. 6, stage 614, cache management software sets the cache mode from uncached [second mode] to cached [first mode]; afterwards, I/O requests are then directed to the cache device [memory system]);
and transmit, to the host system, an indication that the memory system has transitioned from the second mode of operation to the first mode of operation (Paragraph 41; Figs. 1 and 3, I/O redirection module 330 [assumed to be a part of caching software 30 within host 10 under its broadest reasonable interpretation] is notified when the memory device status has changed from uncached [second mode] to cached [first mode]).
Lam, Dantkale, and Kazemi are analogous art because they are in the same field of endeavor, that being cache management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam in view of Dantkale to further include the two modes of operation according to the teachings of Kazemi. The motivation for doing so would have been to continue caching operations without disruption in response to a device failure (Kazemi, Paragraph 51).
Regarding claim 17, this is a computer readable medium version of the claimed apparatus discussed above (claim 8, respectively), in which Lam in view of Dantkale, further in view of Kazemi also teaches a non-transitory computer-readable medium (Lam, Paragraph 119; Fig. 9, machine-readable storage medium 924)
storing code comprising instructions (Lam, Paragraph 119; Fig. 9, instructions 926)
which are executed by a processor (Lam, Paragraph 119; Fig. 9, processing device 902). The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Lam in view of Dantkale, further in view of Kazemi.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Dantkale, further in view of Kazemi as applied to claim 8 above, and further in view of Gabryjelski et al. (US 20060190510 A1), hereinafter Gabryjelski.
Regarding claim 21, Lam in view of Dantkale, further in view of Kazemi teaches the apparatus of claim 8, but does not explicitly teach wherein, in the second mode of operation, the memory system determines whether to delay performance of a synchronize cache command received from the host system or delay performance of a force unit access command received from the host system.
However, Gabryjelski teaches wherein, in the second mode of operation (Paragraph 51; Fig. 6, step 614, providing a method [mode of operation] that only sends a synch cache command only upon request]),
the memory system determines whether to delay performance of a synchronize cache command received from the host system or delay performance of a force unit access command received from the host system (Paragraphs 38, 58; Fig. 11, step 1100, delaying the sending of a synch cache command from an application [host system] until requested).
Lam, Dantkale, Kazemi, and Gabryjelski are analogous art because they are in the same field of endeavor, that being cache management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam in view of Dantkale, further in view of Kazemi to further include the delaying of a synchronize cache command according to the teachings of Gabryjelski. The motivation for doing so would have been mitigate the performance reduction incurred by multiple synchronize cache requests (Gabryjelski, Paragraphs 6-7).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Dantkale as applied to claim 1 above, and further in view of Gabryjelski.
Regarding claim 23, Lam in view of Dantkale teaches the apparatus of claim 1, and the one or more controllers (Lam, Paragraph 40; Fig. 1, memory subsystem controller 115).
Lam in view of Dantkale does not explicitly teach wherein the one or more controllers are further configured to cause the apparatus to: operate in a mode of operation based at least in part on a value of a flag of the apparatus, wherein: a first value of the flag indicates a first operation mode in which the apparatus honors synchronization commands associated with the cache; and a second value of the flag indicates a second operation mode in which the apparatus is allowed to determine to delay execution of a synchronization command associated with the cache and to execute one or more other commands based at least in part on the delaying, wherein the synchronization command is executed at a later time based at least in part on the delaying.
However, Gabryjelski teaches wherein the one or more controllers are further configured to cause the apparatus to: operate in a mode of operation based at least in part on a value of a flag of the apparatus (Paragraphs 45, 51-52; Fig. 6, steps 612-614, implementing a write barrier method [mode of operation] based on STATUS WriteBarrierWriteCompletion [value of a flag]), wherein:
a first value of the flag indicates a first operation mode in which the apparatus honors synchronization commands associated with the cache (Paragraphs 51-52, 57; Figs. 6 and 10, steps 612 and 1000, a STATUS indicating a first write barrier method allows synchronize cache commands to be sent immediately); and
a second value of the flag indicates a second operation mode in which the apparatus is allowed to determine to delay execution of a synchronization command associated with the cache (Paragraphs 51-52, 58; Figs. 6 and 11, steps 612 and 1100, a STATUS indicating a second write barrier method delays the sending [execution] of synch cache commands until requested (delaying until determining the apparatus has received the request)) and
to execute one or more other commands based at least in part on the delaying (Paragraphs 56, 58; Figs. 9 and 11, steps 900, 906, 1100-1102, during the collapsing [delaying] of the synch cache commands, processing [executing] outstanding write commands [one or more other commands] until the outstanding write counter reaches zero),
wherein the synchronization command is executed at a later time based at least in part on the delaying (Paragraph 58; Fig. 11, step 1100, delaying the sending [execution] of a synch cache command until it is requested).
Lam, Dantkale, and Gabryjelski are analogous art because they are in the same field of endeavor, that being cache data recovery. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Lam in view of Dantkale to further include the delaying of a synchronize cache command according to the teachings of Gabryjelski. The motivation for doing so would have been mitigate the performance reduction incurred by multiple synchronize cache requests (Gabryjelski, Paragraphs 6-7).
Response to Arguments
Applicant’s arguments (see page 11 of the remarks) filed 6/26/2026, with respect to the rejections of claims 1-4, 9-13, and 18-20 under 35 U.S.C 102 have been fully considered, but are not persuasive.
Regarding claims 1, 10, and 19, the Applicant argues that the last written page LWP values of Lam associated with the amended limitation “wherein each respective data of the subset of the data is associated with a respective consecutive identifier of a plurality of identifiers” are not indicated or suggested to be consecutive, nor being assigned to each data of a subset.
However, Lam teaches storing respective identifiers into consecutive entries of a table (Paragraphs 67, 78, 81; Figs. 3-4, storing last written page LWP values into write tracker table 162B, which is a high frequency update table HFUT 362 containing multiple consecutive entries HFUT Entry_0-N), wherein the respective identifiers correspond to respective subsets of data (Paragraphs 81, 84-85; Fig. 4, each HFUT entry of write tracker table 162B contains corresponding information of a page [subset of data] written to the NVM device).
The Examiner argues that the newly cited areas of the Lam reference teach the amended limitation of claims 1, 10, and 19, and further notes any other arguments with respect to the limitation of claims 1, 10, and 19 are consummate in scope with the argument above. Thus, the Examiner maintains the rejection with respect to the limitation as set forth above.
Applicant’s arguments (see pages 12-13 of the remarks) filed 6/26/2026, with respect to the rejections of claims 1-4, 9-13, and 18-20 under 35 U.S.C 102 have been fully considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lam and Dantkale.
Applicant’s arguments (see page 14 of the remarks) filed 6/26/2026, with respect to the rejection of claim 21 under 35 U.S.C 103 have been fully considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lam, Dantkale, Kazemi, and Gabryjelski.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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