DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention group I, species 1b shown in Fig. 9, and Species 2a shown in Fig. 5 in the reply filed on 01/26/2024 is acknowledged.
Claim 12 requires the memory block unit includes a plurality of units, each unit comprising two adjacent memory block and having the interdigitated shape which directs to non-elected species 1c and 1d disclosed in Fig. 10, Fig. 11, paragraph [0115]
Claim 13 requires a second memory block unit comprising two adjacent memory block and being vertically symmetrical with respect to the first memory block unit which directs to non-elected species 1d disclosed in Fig. 11, paragraph [0119].
Claims 14 and 15 requires connection lines which directs to non-elected species 2b disclosed in Fig. 7, paragraph [0101].
Accordingly, claims 12-15, 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR10-0230041560 filed on 01/06/2024. The foreign application is not in English. The certified copy of the foreign priority application KR10-0230041560 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application KR10-0230041560 that is not in English, an English translation of the non-English language foreign application KR10-0230041560 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-6, 11 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, claim 3 recites the limitation "the first staircase pattern of the first staircase portion”, “the first staircase pattern of the second staircase portion”, “the second staircase pattern of the first staircase portion” and “the second staircase pattern of the second staircase portion”, "the number of the first staircase pattern of the first staircase portion”, “the number of the first staircase pattern of the second staircase portion”, “the number of the second staircase pattern of the first staircase portion” and “the number of the second staircase pattern of the second staircase portion”. There is insufficient antecedent basis for these limitations in the claim.
Regarding claims 4 and 17, claim 4 and claim 17 each recites “the staircases”. There is insufficient antecedent basis for this limitation in the claim. It is unclear “the staircases” refers to which staircases: descending staircases or ascending staircases or another staircases. Besides, claim 1 and claim 16 does not define any staircases that constitute for both the first staircase pattern and the second staircase pattern.
Regarding claim 5, claim 5 recites the limitation “the staircases of the first and second staircase patterns”. There is insufficient antecedent basis for this limitation in the claim. In addition, the limitation of claim 5 is confusing. It is unclear what Applicant attempt to claim.
Regarding claim 11, claim 11 recites the limitation "the number of the first staircase pattern”, “the number of the second staircase pattern. There is insufficient antecedent basis for these limitations in the claim.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim (US Pub. 20210098472).
Regarding claim 1, Kim discloses in Fig. 22-Fig. 29 a memory device, comprising:
a plurality of memory blocks, each including a cell region [I] and a cell wiring region [II],
wherein at least one memory block of the plurality of memory blocks comprises:
a wordline pattern portion [250] provided in the cell region [I] and the cell wiring region [II] and including wordlines [250] spaced apart from each other and stacked in a first direction [vertical direction]; and
a channel structure [230] provided in the cell region [I] to extend in the first direction [vertical direction], wherein the wordline pattern portion [250] extends a second direction [first direction, horizontal direction], perpendicular to the first direction [vertical direction], when viewed from above, and has at least one staircase portion comprising a first staircase pattern, having sequentially descending staircases, and a second staircase pattern, having sequentially ascending staircases, and wherein the first staircase pattern and the second staircase pattern are provided in different numbers in the at least one memory block [the first staircase pattern and the second staircase pattern are provided in different numbers of steps].
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Regarding claim 2, Kim discloses in Fig. 22-Fig. 29
wherein the at least one staircase portion comprises a first staircase portion and a second staircase portion spaced apart from the first staircase portion in the second direction.
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Regarding claim 16, Kim discloses in Fig. 1-2, Fig. 22-Fig. 29, a memory device, comprising:
a first semiconductor layer [100] comprising a memory cell array [array formed in region I][paragraph [0027]]; and
a second semiconductor layer [600] comprising a peripheral circuit and bonded to the first semiconductor layer [paragraph [0022]-[0026]],
wherein the memory cell array comprises a plurality of memory blocks, each comprising a cell region [I] and a cell wiring region [II], and at least one memory block of the plurality of memory blocks comprises:
a wordline pattern portion [250] provided in the cell region [I] and the cell wiring region [II] and including wordlines [250] spaced apart from each other and stacked in a first direction [vertical direction]; and
a channel structure [230] provided in the cell region [I] to extend in the first direction [vertical direction], wherein the wordline pattern portion [250] extends a second direction [first direction, horizontal direction], perpendicular to the first direction [vertical direction], when viewed from above, and has at least one staircase portion comprising a first staircase pattern, having sequentially descending staircases, and a second staircase pattern, having sequentially ascending staircases, and wherein the first staircase pattern and the second staircase pattern are provided in different numbers in the at least one memory block [the first staircase pattern and the second staircase pattern are provided in different numbers of steps].
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Claims 1-2, 7-8, 10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kim et al. (US Pub. 20200075605).
Regarding claim 1, Kim et al. discloses in Fig. 5, Fig. 7, Fig. 10 a memory device, comprising:
a plurality of memory blocks [BLS1-BLS4], each including a cell region [CAR] and a cell wiring region [CNR1],
wherein at least one memory block [BLS1] of the plurality of memory blocks comprises:
a wordline pattern portion [10, 20, 30] provided in the cell region [CAR] and the cell wiring region [CNR1] and including wordlines [10e, 20e, 30e] spaced apart from each other and stacked in a first direction [Z direction][paragraph [0052]]; and
a channel structure [VS] provided in the cell region [CAR] to extend in the first direction [Zdirection], wherein the wordline pattern portion [10, 20, 30] extends a second direction [Y direction], perpendicular to the first direction [Z direction], when viewed from above, and has at least one staircase portion comprising a first staircase pattern [UP3-UP7], having sequentially descending staircases, and a second staircase pattern [40e], having sequentially ascending staircases, and wherein the first staircase pattern [UP3-UP7] and the second staircase pattern [40e] are provided in different numbers in the at least one memory block [the first staircase pattern [UP3-UP7] and the second staircase pattern [40e] are provided in different numbers of stair dividing patterns].
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Regarding claim 2, Kim discloses in Fig. 7
wherein the at least one staircase portion comprises a first staircase portion and a second staircase portion spaced apart from the first staircase portion in the second direction.
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Regarding claims 7-8, Kim discloses in Fig. 7
wherein: in the staircase portion, the first staircase pattern is provided in a first region and the second staircase pattern is provided in a second region adjacent to the first region in the second direction; and
the first staircase pattern comprises m first staircase patterns [2], the second staircase pattern comprises n second staircase patterns [1], m is a positive integer, and n is a positive integer different from m;
wherein when at least one of the first staircase pattern or the second staircase pattern includes a plurality of staircase patterns, the plurality of first staircase patterns or the plurality of second staircase patterns are arranged in a third direction, perpendicular to the first direction and the second direction.
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Regarding claim 10, Kim et al. discloses in Fig. 5
wherein when two adjacent memory blocks [BLS1 and BLS3] are a first memory block [BLS1] and a second memory block [BLS3], the first and second memory blocks have different widths depending on a disposition of the staircase portion in the first and second regions, and have an interdigitated shape.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20200075605) as applied to claim 8 above and further in view of Lee et al. (US Pub. 20190355737)
Regarding claim 9, Kim et al. discloses in Fig. 5
wherein the plurality of memory blocks are arranged in the third direction, and a trench [SR1] is provided between two adjacent memory blocks and has a bent portion when viewed from above.
Kim et al. fails to disclose
the bent portion comprises an inclined portion inclined in the second direction when viewed from above.
However, Kim et al. discloses in paragraph [0047] the block separation region SR1 may have a zigzag shape, when viewed in a plan view.
Lee et al. discloses in Fig. 3, paragraph [0055]
the bent portion of the trench [MS] has an inclined portion [MS2v] inclined in the second direction when viewed from above.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lee et al. into the method of Kim et al. to include the bent portion comprises an inclined portion inclined in the second direction when viewed from above. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable shape of the bent portion of the trench.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 20200075605) in view of Baek et al. (US Pub. 20190393241)
Regarding claim 16, Kim et al. discloses in Fig. 1, Fig. 2, Fig. 5, Fig. 7, Fig. 10 a memory device, comprising:
a first semiconductor layer comprising a memory cell array [Fig. 1, Fig. 2, paragraph [0028]-[0035]];
a second layer comprising a peripheral circuit and bonded to the first semiconductor layer;
wherein the memory cell array comprises a plurality of memory blocks [BLS1-BLS4], each including a cell region [CAR] and a cell wiring region [CNR1],
wherein at least one memory block [BLS1] of the plurality of memory blocks comprises:
a wordline pattern portion [10, 20, 30] provided in the cell region [CAR] and the cell wiring region [CNR1] and including wordlines [10e, 20e, 30e] spaced apart from each other and stacked in a first direction [Z direction][paragraph [0052]]; and
a channel structure [VS] provided in the cell region [CAR] to extend in the first direction [Zdirection], wherein the wordline pattern portion [10, 20, 30] extends a second direction [Y direction], perpendicular to the first direction [Z direction], when viewed from above, and has at least one staircase portion comprising a first staircase pattern [UP3-UP7], having sequentially descending staircases, and a second staircase pattern [40e], having sequentially ascending staircases, and wherein the first staircase pattern [UP3-UP7] and the second staircase pattern [40e] are provided in different numbers [2 vs. 1] in the at least one memory block [the first staircase pattern [UP3-UP7] and the second staircase pattern [40e] are provided in different numbers of stair dividing patterns].
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Kim et al. fails to disclose
the second layer comprises a second semiconductor layer.
Baek et al. discloses in Fig. 3, Fig. 6, paragraph [0062]
the second layer [PS] comprises a second semiconductor layer [10].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Baek et al. into the method of Kim et al. to include the second layer comprises a second semiconductor layer. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of providing suitable configuration of a layer comprising a peripheral circuit [paragraph [0062]-[0063] of Baek et al.]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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