Prosecution Insights
Last updated: July 17, 2026
Application No. 18/424,831

MULTI-CHIP RADIO FREQUENCY CIRCUIT

Non-Final OA §103
Filed
Jan 28, 2024
Priority
Dec 11, 2023 — TW 112148169
Examiner
CHOE, HENRY
Art Unit
Tech Center
Assignee
RichWave Technology Corp.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1258 granted / 1359 resolved
+32.6% vs TC avg
Minimal -1% lift
Without
With
+-1.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
24 currently pending
Career history
1371
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1359 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over [Franchini et al (Fig. 10); 8,465,432] in view of [Korden (Fig. 1); 7,804,365]. Regarding claim 1, Franchini et al discloses an amplifier circuit comprising a first port (the node between the elements 102 and 104), a second port (28a), a first amplifying circuit (98) coupled to the first port (the node between the elements 102 and 104), a transmission circuit (104) coupled to the second port (28a) and comprising at least one transmission switch (switch in 104), a first switch (switch in 102) coupled to the first amplifying circuit (98), wherein at least one transmission switch (switch in 104) and the first switch (switch in 102) are configured to select one of a first path (18, 104, 28a) and a second path (18, 102, 98, 100, 28a) between the first port (the node between the elements 102 and 104) and the second port (28a) and both of the first path (18, 104, 28a) and the second path (18, 102, 98, 100, 28a) pass through the transmission circuit (104) and the first amplifying circuit (98). As described above, Franchini et al discloses all the limitations in claim 1 except for that the first port being disposed in a first chip and the second port being disposed in a second chip and the first amplifying circuit being disposed in the first chip and the transmission circuit being disposed in the second chip and the both of the first path and the second path pass through the first chip and the second chip. Korden discloses an amplifier circuit comprising a first chip (IC) and a second chip (SW). Chips are well-known means for mounting and connecting electronic devices to form an Integrated Circuit (IC). Therefore, it would have been obvious to have integrated the first amplifying circuit and first port of Franchini et al in the first chip of Korden, and have integrated the transmission circuit and first switch and second port of Franchini et al in the second chip of Korden, such as taught by Korden in order to provide the advantageous benefit of stabilizing the temperature variations of the amplifier circuit. Also, such a modification would have considered a mere application of well-known conventional chip construction. Regarding claim 2, the limitations recited in claim 2 are obvious based on the well known in the amplifier art. Regarding claim 3, wherein the elements of the first chip (IC) comprise bipolar transistors (bipolar transistors in IC), and the second chip (SW) has a capability to comprise complementary metal oxide semiconductors. Regarding claim 4, wherein in a low power mode (switches in 102 and 100 are opened and the switch in 104 is closed), the multi-chip RF circuit (Fig. 1 of Korden) transmit a RF signal through the first path (18, 104, 28a), and in a high power mode (switches in 102 and 100 are closed and the switch in 104 is opened), the multi-chip RF circuit (Fig. 1 of Korden) transmit a RF signal through the second path (18, 102, 98, 100, 28a). Regarding claim 5, wherein a number (zero) of amplifiers passed by the first path (18, 104, 28a) is smaller than a number (one) of amplifiers passed by the second path (18, 102, 98, 100, 28a). Regarding claim 6, wherein the first switch (switch in 102) is disposed in the second chip (SW). Regarding claim 7, wherein all switches (switches in 102 and 104) included in the multi-chip RF circuit (Fig. 1 of Korden) are disposed in the second chip (SW). Regarding claim 8, wherein the first amplifying circuit (98) comprises a first amplifier and the first switch (switch in 102) is coupled between the first port (the node between the elements 102 and 104) and the first amplifier (98), and when the first path (18, 104, 28a) is selected, the first switch (switch in 102) is turned off (the switch 102 is opened) and when the second path (18, 102, 98, 100, 28a) is selected, the first switch (switch in 102) is turned on (the switch 102 is closed). Regarding claim 9, wherein the at least one transmission switch (switch in 104) of the transmission circuit (104) comprises a first transmission switch (switch in 104) having a first terminal (left terminal of the switch in 104) coupled between the first port (the node between the elements 102 and 104) and the first switch (the switch in 102) and a second terminal (right terminal of the switch in 104) coupled to the second port (28a), and when the first path (18, 104, 28a) is selected, the first transmission switch (the switch in 104) is turned on, and when the second path (18, 102, 98, 100, 28a) is selected, the first transmission switch (the switch in 104) is turned off. Claim(s) 12, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over [Franchini et al (Fig. 10); 8,465,432] in view of [Korden (Fig. 1); 7,804,365] in further view of [Pratt (Fig. 3); 8,970,296]. Regarding claims 12 and 13, Franchini et al in view of Korden discloses all the limitations in claim 12 except for that the first shunt circuit and wherein the first shunt circuit comprises a first reactance element and the first reactance element being a first capacitor. Pratt discloses an amplifier circuit comprising a first shunt circuit (246) and the first shunt circuit (246) being a first capacitor and a first terminal (upper terminal of the capacitor 246) of the first shunt circuit (246) is coupled to the first amplifying circuit (280) and a second terminal (lower terminal of the capacitor 246) of the first shunt circuit (246) is coupled to a reference voltage terminal (ground) and further comprising a first switch (240) and the first reactance element (246) is coupled between the first switch (240) and the reference voltage terminal (ground). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the first shunt circuit and the first switch at the input terminal side of the amplifying circuit of Franchini et al (Fig. 10), such as taught by Pratt (Fig. 3) in order to provide the advantageous benefit of stabilizing the variation of the gain of the amplifier circuit. Regarding claim 18, Franchini et al in view of Korden discloses all the limitations in claim 18 except for that the second shunt circuit and the second shunt circuit comprises a second reactance element and the second reactance element being a second inductor and a first terminal of the second shunt circuit is coupled between the first amplifying circuit and the and the second port and a second terminal of the second shunt circuit is coupled to the reference voltage terminal. Pratt discloses an amplifier circuit comprising a second shunt circuit (216) and the second shunt circuit (216) comprises a second reactance element and the second reactance element being a second inductor (216) and a first terminal (left terminal of 216) of the second shunt circuit (216) is coupled between the first amplifying circuit (280) and the and the second port (204) and a second terminal (right terminal of 216) of the second shunt circuit (216) is coupled to the reference voltage terminal (ground). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the second shunt circuit at the output terminal side of the amplifying circuit of Franchini et al (Fig. 10), such as taught by Pratt (Fig. 3) in order to provide the advantageous benefit of stabilizing the variation of the gain of the amplifier circuit. Allowable Subject Matter Claims 10, 11, 14-17, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HENRY CHOE/ Primary Examiner, Art Unit 2843 # 2970
Read full office action

Prosecution Timeline

Jan 28, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12671368
AMPLITUDE MODULATION-PHASE MODULATION (AM-PM) LINEARIZATION IN A POWER AMPLIFIER USING BIAS CIRCUITRY
4y 2m to grant Granted Jun 30, 2026
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Patent 12671375
ELECTRONIC CURRENT TUNING FOR QUIESCENT CURRENTS OF A GALLIUM NITRIDE BASED POWER AMPLIFIER
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
91%
With Interview (-1.2%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1359 resolved cases by this examiner. Grant probability derived from career allowance rate.

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