The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 14-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Filippini et al. (US 2019/0306625).
Regarding claim 1, Filippini discloses an audio restore circuit (see fig. 2, for example), comprising: an audio tracking circuit (e.g., level monitor 206”) configured to generate a first control signal according to a sampling rate of an audio sampled signal and a clock rate of an audio clock signal; a clock adjusting circuit (e.g., playback clock tuner 208) configured to adjust the clock rate of the audio clock signal according to the first control signal (see para. 0036, regarding “playback clock generator 210 can include a phase-locked loop (PLL) that is configured to generate the playback clock. This PLL can be adjusted by the playback clock tuner 208 such that the frequency of the playback clock better matches the rate at which source device 106 provides samples of the multi-channel audio to the distributor device 102a to prevent overflow or underflow of buffer 204”); and an audio generator circuit (e.g., application-level processor 214 and/or distribution transceiver 216) configured to output a plurality of audio output signals according to the audio sampled signal and the audio clock signal.
Regarding claim 14, the plurality of audio output signals corresponds to a plurality of audio channels. See para. 0031, regarding “center speaker 102a distributes the packets of multi-channel audio to the remaining speakers 102b-102e and subwoofer 104 via wireless links 112….” Regarding claim 15, Filippini discloses an audio restore circuit (see fig. 2, for example), comprising: an audio tracking circuit (e.g., level monitor 206) configured to generate a control signal according to a data amount of an audio sampled signal, a data water level upper limit, and a data water level lower limit (see para. 0036, regarding “to prevent buffer 204 from overflowing or under flowing due to the difference in the rate at which source device 106 provides samples of the multi-channel audio to distributor device 102a and the rate at which distributor device 102a renders or plays back at least one audio channel from the multi-channel audio, level monitor 206 can be used to measure the amount of data or audio samples in buffer 204 at specific points in time…”); a clock adjustment circuit (e.g., playback clock tuner 208) configured to adjust a clock rate of an audio clock signal according to the control signal (see para. 0036, regarding “playback clock generator 210 can include a phase-locked loop (PLL) that is configured to generate the playback clock. This PLL can be adjusted by the playback clock tuner 208 such that the frequency of the playback clock better matches the rate at which source device 106 provides samples of the multi-channel audio to the distributor device 102a to prevent overflow or underflow of buffer 204”); and an audio generator circuit (e.g., buffer 204, application-level processor 214, and/or distribution transceiver 216) configured to output a plurality of audio output signals according to the audio sampled signal and the audio clock signal, wherein the audio generator circuit comprises a storage circuit (e.g., buffer 204) configured to receive and store the audio sampled signal.
Regarding claim 16, the storage circuit (e.g., buffer 204) comprises a first-in first-out memory.
Regarding claim 17, the control signal comprises an enable signal. When the data amount is between the data water level upper limit and the data water level lower limit (e.g., buffer 204 is not overflowing or under flowing), the audio tracking circuit (e.g., level monitor 206) generates enable signal with a first logic value to maintain the clock rate of the audio clock signal. When the data amount is greater than the data water level upper limit or less than the data water level lower limit (e.g., buffer 204 is determined to be overflowing or under flowing), the audio tracking circuit (e.g., level monitor 206) generates the enable signal with a second logic value to adjust the clock rate of the audio clock signal. See para. 0036, regarding “playback clock generator 210 can include a phase-locked loop (PLL) that is configured to generate the playback clock. This PLL can be adjusted by the playback clock tuner 208 such that the frequency of the playback clock better matches the rate at which source device 106 provides samples of the multi-channel audio to the distributor device 102a to prevent overflow or underflow of buffer 204”.
Regarding claim 18, the control signal further includes a speed-up signal and a slow-down signal. When the data amount is greater than the data water level upper limit, the audio tracking circuit generates the speed-up signal to speed up the clock rate. When the data amount is less than the data water level lower limit, the audio tracking circuit generates the slow-down signal to slow down the clock rate. See para. 0036, regarding “playback clock generator 210 can include a phase-locked loop (PLL) that is configured to generate the playback clock. This PLL can be adjusted by the playback clock tuner 208 such that the frequency of the playback clock better matches the rate at which source device 106 provides samples of the multi-channel audio to the distributor device 102a to prevent overflow or underflow of buffer 204”.
Regarding claim 19, the plurality of audio output signals corresponds to a plurality of audio channels. See para. 0031, regarding “center speaker 102a distributes the packets of multi-channel audio to the remaining speakers 102b-102e and subwoofer 104 via wireless links 112….”
Claims 2-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references cited on the PTO-892 each disclose a clock circuit for an audio signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL W HUBER whose telephone number is (571)272-7588.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Duc Nguyen, can be reached at telephone number 571-272-7503. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL W HUBER/Primary Examiner, Art Unit 2691
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April 22, 2026
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