Detailed Action
The instant application having Application No. 18/425,079 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 3/23/26. Claims 1, 3-13 and 15-22 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 9, 11, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. (U.S. Patent Application Publication No. 2023/0325225), herein referred to as Agarwal et al. in view of Debendra Das Sharma, Compute Express Link (CXL): Enabling Heterogenous Data-Centric Computing with Heterogenous Memory Hierarchy, 2022, Intel Corporation, Theme Article HOT Interconnects 29, pages 99-109 (Year: 2022), herein referred to as Das Sharma.
Referring to claim 1, Agarwal et al. disclose as claimed, a compute express link (CXL) computing system, comprising: a host device including a CPU that supports CXL (see fig. 1, showing compute nodes with HOST OS on them, including CPUs coupled to a far memory system. See para. 20, where the far memory system is a compute express link based specification); and a CXL storage connected to a CXL root port of the CPU (see para. 26 and fig. 2, showing root ports connected to a CPU and a CXL storage system. Also see para. 33) based on the CXL interconnect and including a flash memory-based memory module (see para. 23, where the far memory system may include flash memory based modules) wherein the memory module is a host-managed device memory (HDM) and is mapped to a cacheable memory address space that is accessed by load/store instructions in the host device (see para. 27, where the memory modules are type 3 CXL devices that may use load and store instructions associated with any of the CPUs. CXL type 3 devices support host-managed device memory. Also see para. 39, where a host may make a read request using a cache line address, which using the CXL specification is then mapped to a far memory containing that data).
Agarwal et al. disclose the claimed invention except for where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory
However, Das Sharma discloses where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory (see page 103, fig. a, which shows a memory hierarchy with CXL cache included, which would be a cacheable memory address space in the host device and included in the memory hierarchy of the CPU cache. See page 99, where CXL supports a unified coherent memory space between the host processor, sharing memory resources coherently. Type 2 devices may be mapped in part to the cacheable memory system. See page 102, where CXL.cache enables a device to cache data from the host memory, employing a simple request and response protocol)
Agarwal et al. and Das Sharma are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Das Sharma, page 99, regarding CXL being an interconnect offering high bandwidth low latency connectivity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory, as taught by Das Sharma, in order to allow both the CPU and the CXL device to share memory resources coherently for higher performance (See Das Sharma, page 99).
As to claim 3, Agarwal et al. and Das Sharma also disclose the CXL computing system of claim 1, wherein the CXL storage is a type 3 CXL device that supports CXL.io protocol and CXL.mem protocol (see Agarwal et al., para. 27, where the memory modules are type 3 CXL devices supporting the CXL.io and CXL.mem protocols).
As to claim 4, Agarwal et al. and Das Sharma also disclose the CXL computing system of claim 1, wherein the CXL root port includes a packet transmission function of CXL protocol (see Agarwal et al., para. 27, where the memory modules are type 3 CXL devices supporting the CXL.io and CXL.mem protocols which would include packet transmission functions. Also see para. 34, where data is transmitted in flits).
As to claim 5, Agarwal et al. and Das Sharma also disclose the CXL computing system of claim 1, wherein the CXL storage includes a CXL controller, a flash memory controller, an internal memory, and the flash memory-based memory module (see Agarwal et al., fig. 2, showing flash memory controllers (FMC), flash memory modules coupled to each FMC and a CXL controller which would be fabric manager 280. See para. 27, where fabric manager 280 may be implemented as a CXL specification compliant fabric manager and data center control plane 290 may specify which slices of memory are allowed to any particular compute node at a given time).
As to claim 6, Agarwal et al. and Das Sharma also disclose the CXL computing system of claim 5, wherein the CXL controller includes a read/write interface of CXL.mem protocol (See Agarwal et al., para. 27, where fabric manager 280 may be implemented as a CXL specification compliant fabric manager and includes the specification of CXL.mem protocol for a read/write interface).
As to claim 9, Agarwal et al. and Das Sharma also disclose the CXL computing system of claim 1, wherein the host device accesses a host-managed device memory (HDM) through the CPU cache, and when a cache miss occurs, converts a memory request into a CXL flit and transmits the CXL flit to the CXL storage (see Agarwal et al., para. 39, where a host may make a read request to a cache line and if there is a cache miss, the request for the cache line would go to the CXL root port and is transmitted to the CXL storage. See fig. 3a and para. 35, showing the read request being sent to the CXL storage. See para. 34, where data is transported in flits).
Referring to claim 11, Agarwal et al. disclose as claimed, a memory expander, comprising: a compute express link (CXL) controller including an end point connected to a CXL root port based on a CXL (see fig. 1, showing compute nodes with HOST OS on them, including CPUs coupled to a far memory system. See para. 20, where the far memory system is a compute express link based specification. See para. 39, where the CXL root port connects to an end point. See para. 27, where fabric manager 280 may be implemented as a CXL specification compliant fabric manager and data center control plane 290 may specify which slices of memory are allowed to any particular compute node at a given time) and parsing a memory request from a received CXL flit (see para. 34-37, where CXL flits are transmitted and processed), a flash memory-based memory module (see para. 23, where the far memory system may include flash memory based modules), and a flash memory controller controlling the memory module according to the memory request transmitted from the CXL controller (see fig. 2, showing flash memory controllers (FMC) and flash memory modules coupled to each FMC.); wherein the memory module is a host-managed device memory (HDM) and is mapped to a cacheable memory address space that is accessed by load/store instructions in the host device (see para. 27, where the memory modules are type 3 CXL devices that may use load and store instructions associated with any of the CPUs. CXL type 3 devices support host-managed device memory. Also see para. 39, where a host may make a read request using a cache line address, which using the CXL specification is then mapped to a far memory containing that data).
Agarwal et al. disclose the claimed invention except for where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory
However, Das Sharma discloses where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory (see page 103, fig. a, which shows a memory hierarchy with CXL cache included, which would be a cacheable memory address space in the host device and included in the memory hierarchy of the CPU cache. See page 99, where CXL supports a unified coherent memory space between the host processor, sharing memory resources coherently. Type 2 devices may be mapped in part to the cacheable memory system. See page 102, where CXL.cache enables a device to cache data from the host memory, employing a simple request and response protocol)
Agarwal et al. and Das Sharma are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Das Sharma, page 99, regarding CXL being an interconnect offering high bandwidth low latency connectivity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory, as taught by Das Sharma, in order to allow both the CPU and the CXL device to share memory resources coherently for higher performance (See Das Sharma, page 99).
As to claim 13, Agarwal et al. and Das Sharma et al. also disclose the memory expander of claim 12, wherein the CXL controller includes a read/write interface of the CXL.mem protocol (See Agarwal et al., para. 27, where fabric manager 280 may be implemented as a CXL specification compliant fabric manager and includes the specification of CXL.mem protocol for a read/write interface).
Referring to claim 18, Agarwal et al. disclose as claimed, an operating method of a host device supporting a compute express link (CXL), comprising: mapping a memory module of a CXL storage (See para. 20, where the far memory system is a compute express link based specification) to a cacheable memory address space that is accessed by load/store instructions and managing the memory module as a host-managed device memory (HDM) (see para. 27, where the memory modules are type 3 CXL devices that may use load and store instructions associated with any of the CPUs. CXL type 3 devices support host-managed device memory. Also see para. 39, where a host may make a read request using a cache line address, which using the CXL specification is then mapped to a far memory containing that data); accessing the HDM through a cache for a memory request including the load/store instructions; and converting the memory request into a CXL flit when a cache miss occurs and transmitting the CXL flit to the CXL storage (see para. 39, where a host may make a read request to a cache line and if there is a cache miss, the request for the cache line would go to the CXL root port and is transmitted to the CXL storage. See fig. 3a and para. 35, showing the read request being sent to the CXL storage. See para. 34, where data is transported in flits).
Agarwal et al. disclose the claimed invention except for where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory
However, Das Sharma discloses where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory (see page 103, fig. a, which shows a memory hierarchy with CXL cache included, which would be a cacheable memory address space in the host device and included in the memory hierarchy of the CPU cache. See page 99, where CXL supports a unified coherent memory space between the host processor, sharing memory resources coherently. Type 2 devices may be mapped in part to the cacheable memory system. See page 102, where CXL.cache enables a device to cache data from the host memory, employing a simple request and response protocol)
Agarwal et al. and Das Sharma are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Das Sharma, page 99, regarding CXL being an interconnect offering high bandwidth low latency connectivity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise where the cacheable memory address space in the host device to be included in a memory hierarchy of the CPU cache and the local memory, as taught by Das Sharma, in order to allow both the CPU and the CXL device to share memory resources coherently for higher performance (See Das Sharma, page 99).
Claims 7, 10, 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. in view of Das Sharma and in view of Agarwal (U.S. Patent Application Publication No. 2024/0184477), herein referred to as Agarwal2.
As to claim 7, Agarwal et al. and Das Sharma disclose the claimed invention except for the CXL computing system of claim 5, wherein the CXL controller is implemented in a conversion device separate from the storage including the flash memory controller and the memory module, and the conversion device connects between the host device and the storage based on the CXL.
However, Agarwal2 discloses wherein the CXL controller is implemented in a conversion device separate from the storage including the flash memory controller and the memory module, and the conversion device connects between the host device and the storage based on the CXL (see fig. 2, showing the CXL controller implemented in a CXL operations ASIC separate from the flash memory dies, which would include the flash memory controllers, and from the host, and connecting them both).
Agarwal et al. and Agarwal2 are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Agarwal2, abstract, regarding transmitting data in flits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the CXL controller is implemented in a conversion device separate from the storage including the flash memory controller and the memory module, and the conversion device connects between the host device and the storage based on the CXL, as taught by Agarwal2, in order to route data effectively as well as interfacing with CXL transactions from the host and translating them to the memory.
As to claim 10, Agarwal et al. and Das Sharma disclose the claimed invention except for the CXL computing system of claim 9, wherein the CXL flit includes a hint instructing the CXL storage to perform an operation related to the memory request.
However, Agarwal2 discloses wherein the CXL flit includes a hint instructing the CXL storage to perform an operation related to the memory request. (see fig. 2, showing a FLIT header with a memopcode, which would be a hint to perform an operation related to the memory request).
Agarwal et al. and Agarwal2 are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Agarwal2, abstract, regarding transmitting data in flits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the CXL flit includes a hint instructing the CXL storage to perform an operation related to the memory request, as taught by Agarwal2, in order to route data effectively depending on the transaction.
As to claim 15, Agarwal et al. and Das Sharma disclose the claimed invention except for the memory expander of claim 11, wherein the CXL flit includes a hint instructing an operation related to the memory request.
However, Agarwal2 discloses wherein the CXL flit includes a hint instructing an operation related to the memory request (see fig. 2, showing a FLIT header with a memopcode, which would be a hint to perform an operation related to the memory request).
Agarwal et al. and Agarwal2 are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Agarwal2, abstract, regarding transmitting data in flits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the CXL flit includes a hint instructing an operation related to the memory request, as taught by Agarwal2, in order to route data effectively depending on the transaction.
As to claim 19, Agarwal et al. and Das Sharma disclose the claimed invention except for the operating method of claim 18, wherein the CXL flit includes a hint instructing the CXL storage to perform an operation related to the memory request.
However, Agarwal2 discloses wherein the CXL flit includes a hint instructing the CXL storage to perform an operation related to the memory request (see fig. 2, showing a FLIT header with a memopcode, which would be a hint to perform an operation related to the memory request).
Agarwal et al. and Agarwal2 are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Agarwal2, abstract, regarding transmitting data in flits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the CXL flit includes a hint instructing the CXL storage to perform an operation related to the memory request, as taught by Agarwal2, in order to route data effectively depending on the transaction.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. in view of Das Sharma and in view of Andreozzi et al. (U.S. Patent Application Publication No. 2021/0255981), herein referred to as Andreozzi et al.
As to claim 8, Agarwal et al. and Das Sharma disclose the claimed invention except for the CXL computing system of claim 1, wherein the host device and the CXL storage are connected through a CXL switch, and the CXL switch routes CXL flits incoming to an upstream port or a downstream port to the corresponding port according to an internal routing table.
However, Andreozzi et al. disclose wherein the host device and the CXL storage are connected through a CXL switch, and the CXL switch routes CXL flits incoming to an upstream port or a downstream port to the corresponding port according to an internal routing table. (see fig. 10 and 14, showing switches routing flits to upstream or downstream ports depending on the destination, which would rely on a routing table. See para. 36, where a header of a flit is analyzed to determine which port of a switch the data is routed to).
Agarwal et al. and Andreozzi et al. are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Andreozzi et al., para. 27-29, where data is transmitted in flits with headers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the host device and the CXL storage are connected through a CXL switch, and the CXL switch routes CXL flits incoming to an upstream port or a downstream port to the corresponding port according to an internal routing table., as taught by Andreozzi et al., in order to route data to the correct destination. Routing data to different ports in switches is well known in the art and would be obvious to include with Agarwal et al.
Claims 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. in view of Das Sharma and in view of Agarwal2 and in view of Radi et al. (U.S. Patent Application Publication No. 2021/0409506), herein referred to as Radi et al.
As to claim 16, Agarwal et al., Das Sharma and Agarwal2 disclose the claimed invention except for the memory expander of claim 15, wherein, when a request including a hint called deterministic (DT) arrives, the flash memory controller delays other internal tasks and first processes the corresponding request.
However, Radi et al. disclose wherein, when a request including a hint called deterministic (DT) arrives, the flash memory controller delays other internal tasks and first processes the corresponding request (see para. 52-58, where a priority indicator or hint may be part of the packet header and may indicate a class of service or a special priority in relation to other messages or requests, which would therefore delay other requests).
Agarwal et al. and Radi et al. are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Radi et al., abstract, regarding sending cache messages to memory devices through ports and switches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein, when a request including a hint called deterministic (DT) arrives, the flash memory controller delays other internal tasks and first processes the corresponding request, as taught by Radi et al., in order to give certain messages or requests faster service depending on priority. Prioritizing operations or requests is well known in the art and would be obvious to include in a data transmission system such as Agarwal’s.
As to claim 17, Agarwal et al., Das Sharma and Agarwal2 disclose the claimed invention except for the memory expander of claim 15, wherein, when a request including a hint called bufferable (BF) arrives, the flash memory controller caches or buffers the corresponding request in an internal memory, and when a request including a hint called non-bufferable (NB) arrives, the flash memory controller performs an operation of preferentially ensuring data persistency.
However, Radi et al. disclose wherein, when a request including a hint called bufferable (BF) arrives, the flash memory controller caches or buffers the corresponding request in an internal memory, and when a request including a hint called non-bufferable (NB) arrives, the flash memory controller performs an operation of preferentially ensuring data persistency corresponding request (see para. 52-58, where a priority indicator or hint may be part of the packet header and may indicate a class of service or a special priority in relation to other messages or requests, which would therefore delay other requests. The priority indicator may indicate a class of service for greater reliability which would preferentially ensure data persistency or the indicator may indicate if the packet is a cache message for a particular cache and therefore bufferable).
Agarwal et al. and Radi et al. are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Radi et al., abstract, regarding sending cache messages to memory devices through ports and switches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein, when a request including a hint called bufferable (BF) arrives, the flash memory controller caches or buffers the corresponding request in an internal memory, and when a request including a hint called non-bufferable (NB) arrives, the flash memory controller performs an operation of preferentially ensuring data persistency, as taught by Radi et al., in order to give certain messages or requests faster service depending on priority. Prioritizing operations or requests is well known in the art and would be obvious to include in a data transmission system such as Agarwal’s.
As to claim 20, Agarwal et al., Das Sharma and Agarwal2 disclose the claimed invention except for the operating method of claim 19, wherein the hint instructs to process the corresponding request before other internal tasks, instructs to cache or buffer the corresponding request in the internal memory of the CXL storage, or instructs to preferentially ensure data persistency for the corresponding request.
However, Radi et al. disclose wherein the hint instructs to process the corresponding request before other internal tasks, instructs to cache or buffer the corresponding request in the internal memory of the CXL storage, or instructs to preferentially ensure data persistency for the corresponding request (see para. 52-58, where a priority indicator or hint may be part of the packet header and may indicate a class of service or a special priority in relation to other messages or requests, which would therefore delay other requests. The priority indicator may indicate a class of service for greater reliability which would preferentially ensure data persistency or the indicator may indicate if the packet is a cache message for a particular cache).
Agarwal et al. and Radi et al. are analogous art because they are from the same field of endeavor of data transmission (see Agarwal et al., para. 34, where data is transmitted in flits with headers. See Radi et al., abstract, regarding sending cache messages to memory devices through ports and switches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the hint instructs to process the corresponding request before other internal tasks, instructs to cache or buffer the corresponding request in the internal memory of the CXL storage, or instructs to preferentially ensure data persistency for the corresponding request, as taught by Radi et al., in order to give certain messages or requests faster service depending on priority. Prioritizing operations or requests is well known in the art and would be obvious to include in a data transmission system such as Agarwal’s.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. in view of Das Sharma and in view of Myran et al. (U.S. Patent Application Publication No. 2019/0339904), herein referred to as Myran et al.
As to claim 21, Agarwal et al. and Das Sharma disclose the claimed invention except for the CXL computing system of claim 9, wherein the CXL storage further includes a CXL controller that converts the CXL flit into the memory request, and converts a byte address of the memory request into a block address for the memory module.
However, Myran et al. disclose wherein the CXL storage further includes a CXL controller that converts the CXL flit into the memory request, and converts a byte address of the memory request into a block address for the memory module (see para. 7, where a memory controller receives a logical address and converts it to a physical address using a two stage mapping table, where the first stage is byte-rewritable memory and the second is block-erasable memory, and therefore a byte address of the memory request would be converted to a block address for the memory module. When combined with Agarwal et al. and Das Sharma, which teach using CXL, this would allow a CXL flit to be converted, as traffic between the host and a device is transported using flits).
Agarwal et al. and Myran et al. are analogous art because they are from the same field of endeavor of memory systems (see Agarwal et al., para. 19-20, regarding memory systems and see Myran et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the CXL storage further includes a CXL controller that converts the CXL flit into the memory request, and converts a byte address of the memory request into a block address for the memory module, as taught by Myran et al., in order to allow for a block based memory such as a flash memory to access data properly.
As to claim 22, Agarwal et al. and Das Sharma disclose the claimed invention except for the memory expander of claim 11, wherein the CXL controller converts a byte address of the memory request into a block address for the memory module.
However, Myran et al. disclose wherein the CXL controller converts a byte address of the memory request into a block address for the memory module (see para. 7, where a memory controller receives a logical address and converts it to a physical address using a two stage mapping table, where the first stage is byte-rewritable memory and the second is block-erasable memory, and therefore a byte address of the memory request would be converted to a block address for the memory module. When combined with Agarwal et al. and Das Sharma, which teach using CXL, this would allow a CXL flit to be converted, as traffic between the host and a device is transported using flits).
Agarwal et al. and Myran et al. are analogous art because they are from the same field of endeavor of memory systems (see Agarwal et al., para. 19-20, regarding memory systems and see Myran et al., abstract, regarding memory systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarawal et al. to comprise wherein the CXL controller converts a byte address of the memory request into a block address for the memory module as taught by Myran et al., in order to allow for a block based memory such as a flash memory to access data properly.
Response to Arguments
Applicant’s arguments, filed 3/23/26, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Das Sharma.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1, 3-13 and 15-22 stand rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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