Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant's election with traverse of Figs. 6 and 7 in the reply filed on 5/8/2026 is acknowledged. The traversal is on the ground(s) that Species B and A have a common inventive concept because they can reduce the short-circuiting risk between adjacent first connection lines CL1 and the layout difficulty, and reduce the number of connection lines between the multiplexers MUX and the pints PIN electrically connected to the multiplexers MUX and short-circuiting risk and the layout difficulty of these connection lines. This is not found persuasive because the search and consideration required for the invention is serious search burden. While the embodiments share the common inventive concept, the embodiments teach different structure that cannot be shared with each other. Each embodiment teaches different structural methods of achieving the common inventive concept. In order to consider these difference, separate field of search and different search queries must be employed.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (PGPUB 2022/0199750 A1).
As to claim 1, Cho (Figs. 2 and 7) teaches, a display panel (display device, Fig. 1), comprising:
a non-display region (non-display area: i.e. all areas except for AA as shown in Fig. 2, ¶ 40) comprising a first non-display sub-region (i.e. bottom region) comprising multiplexers (multiplexer circuit unit MCP) and first connection lines (spider line DSPL1a, DSPL1b, DSPL2a and DSPL2b and connection lines CL2A_2, CL2b_2)(¶ 121), wherein one of the multiplexers comprises at least two selection output terminals (Fig. 7: i.e. MC1+MC2 and MC3+MC4 comprise four terminals as shown in Fig. 7) electrically connected to first ends (i.e. bottom ends as shown in Fig. 7) of the first connection lines (Fig. 7); and
a display region (display area AA) comprising a first display sub-region (i.e. edge area on the left side being driven by DSPL2a, DSPL2b) and a second display sub-region (i.e. center area driven by DSPL1a, DSPL1b) located on at least one side of the first display sub-region along a first direction (i.e. horizontal direction, Fig. 7),
wherein the first display sub-region and the first non-display sub-region are arranged along a second direction (i.e. vertical direction) that crosses the first direction (Fig. 7), each of the first display sub-region and the second display sub-region comprises first signal lines (i.e. data lines in entire area as shown in Fig. 7) arranged along the first direction, and the display region further comprises second connection lines (spider lines DSPL3a, DSPL3b, DSPL4a, DSPL4b, CL4a_2, and CL4b_2),
wherein the first connection lines comprise a first connection sub-line (DSPL2a, DSPL2b, CL2a_2 and CL2b_2) and a second connection sub-line (DSPL1a and DSPL1b), at least one of the first signal lines in the first display sub-region is electrically connected to a second end (i.e. upper ends of DSPL2a, DSPL2b and left ends of CL2a_2 and CL2b_2 connecting to DL) of the first connection sub-line, and at least one of the first signal lines in the second display sub-region is electrically connected to a second end (i.e. upper ends of DSPL1a and DSPL1b) of the second connection sub-line through the second connection line (Fig. 7).
As to claim 2, Cho (Fig. 7) teaches, wherein the first signal lines comprise Type-1 signal lines to Type-M signal lines, where M is a positive integer greater than 2 (Fig. 7: i.e. M is considered as 4. The four types are DSPL1a, DSPL1b, DSPL1b, and DSPL2b. The another identical four lines repeat as DSPL3a, DSPL3b, DSPL4a, DSPL4b),
wherein among the Type-1 signal lines to the Type-M signal lines, sub-pixels that are electrically connected to the first signal lines of a same type have a same color (Fig. 7: i.e. same colors are present for same type of signal lines. In other words, DSPL1a and DSPL3a both connect to SP_R and SP_B as shown in Fig. 7), and at least two of sub-pixels electrically connected to the first signal lines of different types have different colors (i.e. DSPL1a connect to red sub pixel and blue sub pixel)(¶124), and
wherein each of the multiplexers is electrically connected to the Type-1 signal line to the Type-M signal line (Fig. 7).
As to claim 3, Cho (Fig. 7) teaches, wherein the Type-1 signal line to the Type-M signal line electrically connected to each of the multiplexers are sequentially arranged
adjacent to one another along the first direction (Fig. 7: i.e. sequentially arranged in horizontal direction), and
wherein, for the Type-1 signal line to the Type-M signal line that are electrically
connected to a same one of the multiplexers, no other first signal line is arranged between any two first signal lines that are arranged adjacent along the first direction (Fig. 7: i.e. in each set of multiplexers, identical four patterns of spider lines are arranged).
As to claim 4, Cho (Fig. 7) teaches, wherein the multiplexers (MC1-MC4) comprise first multiplexers (MC1 and MC2) and second multiplexers (MC3 and MC4),
wherein the at least two selection output terminals of one of the first multiplexers are electrically connected to first signal lines in the first display sub-region through the first connection sub-lines (i.e. DSPL2a and DSPL2b are connected to the left display region from MC1 and MC2), and the at least two selection output terminals of the second multiplexer are electrically connected to the first signal lines in the second display sub-region through the second connection sub-lines and the second connection lines (i.e. DSPL3a and DSPL3b are connected to the center region from MC3 and MC4).
As to claim 5, Cho (Fig. 7) teaches, wherein the multiplexers further comprise a
third multiplexer (i.e. the MC1/MC2 and MC3/MC4 are repeating patterns. There must be third multiplexer in view of Fig. 7), at least one of the at least two selection output terminals of the third multiplexer is electrically connected to the first signal line in the second display sub-region through the first connection sub-line, and another at least one of the at least two selection output terminals of the third multiplexer is electrically connected to the first signal line in the first display sub-region through the second connection sub-line and the second connection line (Fig. 7: i.e. the third multiplexer would have identical structure as MC1, MC2 and MC3, MC4 in terms of connecting to the data line and subpixel color).
As to claim 6, Cho (Fig. 7) teaches, wherein the at least two selection output
terminals comprise Type-1 selection output terminal to Type-M selection output terminal, and the Type-1 signal line to the Type-M signal line are electrically connected to the Type-1 selection output terminal to the Type-M selection output terminal in a one-to-one correspondence manner (Fig. 7: i.e. each two multiplexers MC have one-to-one correspondence between input to output and each data line),
wherein, for the Type-1 signal line to the Type-M signal line and the Type-1 selection output terminal to the Type-M selection output terminal corresponding to a same one of the multiplexers, an arrangement sequence of the Type-1 signal line to the Type-M signal line along the first direction is the same as an arrangement sequence of the Type-1 selection output terminal to the Type-M selection output terminal along the first direction (Fig. 7: i.e. arrangement of multiplexers are identical as shown in Fig. 7).
As to claim 7, Cho (Fig. 7) teaches, wherein an arrangement sequence of the multiplexers along the first direction is the same as an arrangement sequence of Type-k signal lines along the first direction that are electrically connected to the multiplexers respectively, where 1<k<M (Fig. 7: i.e. arrangement sequence in horizontal direction of each multiplexer set is identical).
As to claim 8, Cho (Figs. 7, 9, 11) teaches, wherein a layer where the first connection sub-line is arranged is different from a layer where the second connection sub-line is arranged (Fig. 10: i.e. DSPL4a and DSPL3b overlap each other and are in different layers) as shown in Figs. 7, 9 and 11).
As to claim 9, Cho (Fig. 7) teaches, wherein one of the second connection lines comprises a first portion (DSPL4a and DSPL4b) and a second portion (CL4a_2 and CL4b_2), the second portion is connected between the first portion and one of the first signal lines in the second display sub-region (Fig. 7), and the first portions of the second connection lines are arranged along the first direction (i.e. DPLL are on horizontally right side of CL4),
wherein one of the multiplexers comprises selection output terminals (i.e. upper terminals as shown in Fig. 7), the first portion and the first signal line located in the first display sub-region are proximity signal lines (Fig. 7: i.e. DSPL are most proximate to multiplexer MCP), and an arrangement sequence of the selection output terminals along the first direction is the same as an arrangement sequence of the proximity signal lines electrically connected to the selection output terminals along the first direction (Fig. 7: i.e. arrangement sequence is identical in horizontal direction).
As to claim 10, Cho (Fig. 7) teaches, wherein the first non-display sub-region is
further provided with pins (pads PD1-PD4) arranged along the first direction and electrically connected to input terminals of the multiplexers (¶ 118, Fig. 7), and
wherein an arrangement sequence of the pins along the first direction is the same as the arrangement sequence of the multiplexers electrically connected to the pins along the first direction (Fig. 7).
As to claim 11, Cho (Fig. 7) teaches, wherein one of the multiplexers is electrically connected to at least three first signal lines (i.e. connects to four signal lines via MC1 and MC2), and at least one of the at least three first signal lines electrically connected to the multiplexer is located in the first display sub-region (Fig. 7: i.e. two of data lines are connected to the multiplexer from the left edge display region).
As to claim 12, Cho (Fig. 7) teaches, wherein one of the multiplexers is electrically connected to at least three first signal lines (Fig. 7: i.e. each multiplexer MC1 and MC2 connect to four data lines), and at least one of the at least three first signal lines electrically connected to the multiplexer is located in the second display sub-region (Fig. 7: i.e. each multiplexer connect to two data lines in the center display region).
As to claim 19, Cho (Figs. 2 and 7) teaches, a display apparatus (display device, Fig. 1), comprising a display panel (i.e. structure of display device in Fig. 7) comprising:
a non-display region (non-display area: i.e. all areas except for AA as shown in Fig. 2, ¶ 40) comprising a first non-display sub-region (i.e. bottom region) comprising multiplexers (multiplexer circuit unit MCP) and first connection lines (spider line DSPL1a, DSPL1b, DSPL2a and DSPL2b and connection lines CL2A_2, CL2b_2)(¶ 121), wherein one of the multiplexers comprises at least two selection output terminals (Fig. 7: i.e. MC1+MC2 and MC3+MC4 comprise four terminals as shown in Fig. 7) electrically connected to first ends (i.e. bottom ends as shown in Fig. 7) of the first connection lines (Fig. 7); and
a display region (display area AA) comprising a first display sub-region (i.e. edge area on the left side being driven by DSPL2a, DSPL2b) and a second display sub-region (i.e. center area driven by DSPL1a, DSPL1b) located on at least one side of the first display sub-region along a first direction (i.e. horizontal direction, Fig. 7),
wherein the first display sub-region and the first non-display sub-region are arranged along a second direction (i.e. vertical direction) that crosses the first direction (Fig. 7),
each of the first display sub-region and the second display sub-region is provided with first signal lines (i.e. data lines in entire area as shown in Fig. 7) arranged along the first direction, and the display region further comprises second connection lines (spider lines DSPL3a, DSPL3b, DSPL4a, DSPL4b, CL4a_2, and CL4b_2),
wherein the first connection lines comprise a first connection sub-line (DSPL2a, DSPL2b, CL2a_2 and CL2b_2) and a second connection sub-line (DSPL1a and DSPL1b), at least one of the first signal lines in the first display sub-region is electrically connected to a second end (i.e. upper ends of DSPL2a, DSPL2b and left ends of CL2a_2 and CL2b_2 connecting to DL) of the first connection sub-line, and at least one of the first signal lines in the second display sub-region is electrically connected to a second end (i.e. upper ends of DSPL1a and DSPL1b) of the second connection sub-line through the second connection line (Fig. 7).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623